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9ZML1232E

型号：

9ZML1232E

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

19 页

PDF大小：

401 K

下载PDF手册
2:12 DB1200ZL Derivative for  
PCIe Gen1–4 and UPI  
9ZML1232E / 9ZML1252E  
Datasheet  
Description  
Features  
▪ 2 configurable low drift I2O delays up to 2.9ns; maintain transport  
The 9ZML1232E / 9ZML1252E are a second generation  
2-input/12-output differential mux for Intel Purley and newer  
platforms. It exceeds the demanding DB1200ZL performance  
specifications and is backwards compatible to the 9ZML1232B. It  
utilizes Low-Power HCSL-compatible outputs to reduce power  
consumption and termination resistors. It is suitable for PCI-Express  
Gen1–4 or QPI/UPI applications, and provides 2 configurable  
low-drift I2O settings, one for each input channel, to allow I2O tuning  
for various topologies.  
delay for various topologies  
▪ LP-HCSL outputs; eliminate 24 resistors (9ZML1232E)  
▪ LP-HCSL outputs with Zout = 85Ω; eliminate 48 resistors  
(9ZML1252E)  
▪ 9 selectable SMBus addresses; multiple devices can share same  
SMBus segment  
▪ Separate VDDIO for outputs; allows maximum power savings  
▪ PLL or Bypass Mode; PLL can dejitter incoming clock  
PCIe Clocking Architectures  
Supported  
▪ Hardware or software-selectable PLL BW; minimizes jitter  
peaking in downstream PLLs  
▪ Spread spectrum compatible; tracks spreading input clock for EMI  
▪ Common Clocked (CC)  
reduction  
▪ Separate Reference No Spread (SRNS)  
▪ Separate Reference Independent Spread (SRIS)  
▪ SMBus interface; software can modify device settings without  
hardware changes  
▪ 10 x 10 mm 72-QFN package; small board footprint  
Typical Applications  
Servers, Storage, Networking, SSDs  
Key Specifications  
▪ Cycle-to-cycle jitter < 50ps  
▪ Output-to-output skew < 50ps  
Output Features  
▪ 12 Low-power HCSL (LP-HCSL) output pairs (9ZML1232E)  
▪ Input-to-output delay: Fixed at 0 ps  
▪ Input-to-output delay variation < 50ps  
▪ Phase jitter: PCIe Gen4 < 0.5ps rms  
▪ Phase jitter: UPI > 9.6GB/s < 0.1ps rms  
▪ 12 Low-power HCSL (LP-HCSL) output pairs with 85Ω Zout  
(9ZML1252E)  
Block Diagram  
I2O  
Delay  
Low Phase  
Noise Z-PLL  
FBOUT_NC  
^SEL_A_B#  
DIF_INA  
(SS-  
Compatible)  
DIF_11  
Bypass path  
DIF_INB  
12  
outputs  
^vHIBW_BYPM  
_LOBW#  
CKPWRGD_PD#  
vSMB_A0_tri  
vSMB_A1_tri  
SMBDAT  
DIF_0  
NOTE: Internal series resistors are  
only present on the 9ZML1252  
SMBCLK  
^OE(11:0)#  
©2018 Integrated Device Technology, Inc  
1
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
Pin Configuration  
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55  
^OE7#  
VDDA  
GNDA  
1
2
3
4
5
6
7
8
9
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
^OE6#  
VDDIO  
GND  
^SEL_A_B#  
^vHIBW_BYPM_LOBW#  
CKPWRGD_PD#  
DIF_INB  
DIF_7#  
DIF_7  
DIF_6#  
DIF_6  
GND  
DIF_INB#  
GND  
9ZML1232E  
9ZML1252E  
connect epad to GND  
VDDR  
VDD  
DIF_INA 10  
DIF_INA# 11  
vSADR0_tri 12  
SMBDAT 13  
SMBCLK 14  
DIF_5#  
DIF_5  
DIF_4#  
DIF_4  
VDDIO  
GND  
vSADR1_tri 15  
16  
NC  
^OE5#  
^OE4#  
FBOUT_NC# 17  
FBOUT_NC 18  
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36  
^ prefix indicates internal 120Kohm Pull Up  
v prefix indicates internal 120Kohm Pull down  
10mm x 10mm 72-VFQFPN 0.5mm pin pitch  
Power Management Table  
Inputs  
Outputs  
Control Bits  
SMBus  
PLL State  
CKPWRGD_PD#  
DIF_IN  
EN bit  
DIF_x  
FBOUT_NC  
Low/Low  
Running  
0
1
X
X
0
1
Low/Low  
Low/Low  
Running  
OFF  
ON  
ON  
Running  
Running  
PLL Operating Mode Table  
HIBW_BYPM_LOBW# Byte0[7:6]  
Power Connections  
Pin Number  
Description  
Low ( PLL Low BW)  
Mid (Bypass)  
High (PLL High BW)  
00  
01  
11  
VDD  
1
9
VDDIO  
GND  
2
8
Analog PLL  
Analog Input  
22, 27, 34,  
NOTE: PLL is off in Bypass mode  
28, 45, 64  
40, 52  
39, 46, 51, DIF clocks  
58, 63, 70  
Power Connections (for pin compatibility  
with 9ZML12xxB)  
Skew Programming Table  
Pin Number  
Description  
Skew  
VDD  
VDDIO  
GND  
Skew[2:0] Skew Steps  
(ps)  
1
9
2
8
Analog PLL  
Analog Input  
000  
001  
010  
011  
100  
101  
110  
111  
0
1
2
3
4
5
6
7
0
-416.67  
-833.33  
-1250.00  
-1666.67  
-2083.33  
-2500.00  
-2916.67  
DIF_INx  
, 22, 27,  
16  
tSKEW_PLL  
,
, 40,  
34, 39, 46,  
51, 58, 63,  
70  
21 33  
28, 45, 64  
DIF clocks  
52,  
,
57 69  
DIF_n  
©2018 Integrated Device Technology, Inc  
2
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
Pin Descriptions  
PIN #  
PIN NAME  
PIN TYPE  
PWR  
GND  
DESCRIPTION  
1
2
VDDA  
GNDA  
Power supply for PLL core.  
Ground pin for the PLL core.  
Input to select differential input clock A or differential input clock B. This input has  
an internal pull-up resistor.  
0 = Input B selected, 1 = Input A selected.  
Tri-level input to select High BW, Bypass or Low BW mode. This pin is biased to  
VDD/2 (Bypass mode) with internal pull up/pull down resistors. See PLL  
Operating Mode Table for Details.  
3.3V input notifies device to sample latched inputs and start up on first high  
assertion, or exit Power Down Mode on subsequent assertions. Low enters  
Power Down Mode.  
3
4
5
^SEL_A_B#  
IN  
LATCHE  
D IN  
^vHIBW_BYPM_LOBW#  
CKPWRGD_PD#  
IN  
6
7
8
DIF_INB  
DIF_INB#  
GND  
IN  
IN  
GND  
True input of differential clock  
Complement input of differential clock  
Ground pin.  
Power supply for differential input clock (receiver). This VDD should be treated  
as an analog power rail and filtered appropriately. Nominally 3.3V.  
True input of differential clock  
9
VDDR  
PWR  
10  
11  
DIF_INA  
DIF_INA#  
IN  
IN  
Complement input of differential clock  
SMBus address bit. This is a tri-level input that works in conjunction with other  
SADR pins, if present, to decode SMBus Addresses. It has an internal pull down  
resistor. See the SMBus Address Selection Table.  
Data pin of SMBUS circuitry  
12  
vSADR0_tri  
IN  
13  
14  
SMBDAT  
SMBCLK  
I/O  
IN  
Clock pin of SMBUS circuitry  
SMBus address bit. This is a tri-level input that works in conjunction with other  
SADR pins, if present, to decode SMBus Addresses. It has an internal pull down  
resistor. See the SMBus Address Selection Table.  
No connection.  
Complementary half of differential feedback output. This pin should NOT be  
connected to anything outside the chip. It exists to provide delay path matching to  
get 0 propagation delay.  
15  
16  
17  
vSADR1_tri  
NC  
IN  
N/A  
OUT  
FBOUT_NC#  
True half of differential feedback output. This pin should NOT be connected to  
anything outside the chip. It exists to provide delay path matching to get 0  
propagation delay.  
18  
FBOUT_NC  
OUT  
Active low input for enabling output 0. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 1. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
19  
20  
^OE0#  
^OE1#  
IN  
IN  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
NC  
GND  
N/A  
GND  
OUT  
OUT  
OUT  
OUT  
GND  
PWR  
OUT  
OUT  
OUT  
OUT  
N/A  
No connection.  
Ground pin.  
HCSL true clock output.  
HCSL complementary clock output.  
HCSL true clock output.  
HCSL complementary clock output.  
Ground pin.  
Power supply, nominally 3.3V.  
HCSL true clock output.  
HCSL complementary clock output.  
HCSL true clock output.  
HCSL complementary clock output.  
No connection.  
Ground pin.  
DIF_0  
DIF_0#  
DIF_1  
DIF_1#  
GND  
VDD  
DIF_2  
DIF_2#  
DIF_3  
DIF_3#  
NC  
GND  
GND  
Active low input for enabling output 2. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
35  
^OE2#  
IN  
©2018 Integrated Device Technology, Inc  
3
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
Pin Descriptions (cont.)  
PIN #  
PIN NAME  
PIN TYPE  
DESCRIPTION  
Active low input for enabling output 3. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 4. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 5. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
Ground pin.  
Power supply for differential outputs.  
HCSL true clock output.  
HCSL complementary clock output.  
HCSL true clock output.  
HCSL complementary clock output.  
Power supply, nominally 3.3V.  
Ground pin.  
HCSL true clock output.  
HCSL complementary clock output.  
HCSL true clock output.  
36  
^OE3#  
IN  
37  
38  
^OE4#  
^OE5#  
IN  
IN  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
GND  
GND  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
GND  
OUT  
OUT  
OUT  
OUT  
GND  
PWR  
VDDIO  
DIF_4  
DIF_4#  
DIF_5  
DIF_5#  
VDD  
GND  
DIF_6  
DIF_6#  
DIF_7  
DIF_7#  
GND  
HCSL complementary clock output.  
Ground pin.  
VDDIO  
Power supply for differential outputs.  
Active low input for enabling output 6. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 7. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 8. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 9. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
No connection.  
Ground pin.  
HCSL true clock output.  
HCSL complementary clock output.  
HCSL true clock output.  
HCSL complementary clock output.  
Ground pin.  
53  
54  
55  
56  
^OE6#  
^OE7#  
^OE8#  
^OE9#  
IN  
IN  
IN  
IN  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
NC  
GND  
N/A  
GND  
OUT  
OUT  
OUT  
OUT  
GND  
PWR  
OUT  
OUT  
OUT  
OUT  
N/A  
DIF_8  
DIF_8#  
DIF_9  
DIF_9#  
GND  
VDD  
Power supply, nominally 3.3V.  
HCSL true clock output.  
HCSL complementary clock output.  
HCSL true clock output.  
HCSL complementary clock output.  
No connection.  
DIF_10  
DIF_10#  
DIF_11  
DIF_11#  
NC  
GND  
GND  
Ground pin.  
Active low input for enabling output 10. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
71  
^OE10#  
IN  
Active low input for enabling output 11. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
72  
73  
^OE11#  
epad  
IN  
GND  
Connect to ground  
©2018 Integrated Device Technology, Inc  
4
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 9ZML1232E / 9ZML1252E. These ratings, which are standard  
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above  
those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended  
periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.  
PARAMETER  
Supply Voltage  
Input Low Voltage  
Input High Voltage  
Input High Voltage  
SYMBOL  
VDDx  
VIL  
CONDITIONS  
UNITS NOTES  
MIN  
TYP  
MAX  
3.9  
V
V
V
V
1,2  
1
GND-0.5  
VIH  
Except for SMBus interface  
SMBus clock and data pins  
VDD+0.5  
3.9  
1,3  
1
VIHSMB  
1
1
Storage Temperature  
Junction Temperature  
Ts  
Tj  
-65  
150  
125  
°C  
°C  
1
Input ESD protection  
ESD prot  
Human Body Model  
2000  
V
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
3 Not to exceed 3.9V.  
Electrical Characteristics–DIF_IN Clock Input Parameters  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
Input Crossover Voltage  
SYMBOL  
VCROSS  
CONDITIONS  
Cross Over Voltage  
MIN  
150  
TYP  
MAX  
900  
UNITS NOTES  
mV  
1
Input Swing - DIF_IN  
Input Slew Rate - DIF_IN  
Input Leakage Current  
Input Duty Cycle  
VSWING  
dv/dt  
IIN  
Differential value  
Measured differentially  
VIN = VDD , VIN = GND  
300  
0.35  
-5  
mV  
V/ns  
uA  
1
1,2  
8
5
dtin  
Measurement from differential waveform  
45  
55  
%
1
1
Input Jitter - Cycle to Cycle  
JDIFIn  
Differential Measurement  
0
125  
ps  
1 Guaranteed by design and characterization, not 100% tested in production.  
2Slew rate measured through +/-75mV window centered around differential zero  
Electrical Characteristics–SMBus  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
VILSMB  
CONDITIONS  
MIN  
TYP  
MAX  
0.8  
UNITS NOTES  
SMBus Input Low Voltage  
SMBus Input High Voltage  
V
V
VIHSMB  
2.1  
VDDSMB  
0.4  
SMBus Output Low Voltage VOLSMB  
@ IPULLUP  
@ VOL  
V
SMBus Sink Current  
Nominal Bus Voltage  
SCLK/SDATA Rise Time  
IPULLUP  
VDDSMB  
tRSMB  
4
mA  
2.7  
3.6  
1000  
300  
V
1
1
1
(Max VIL - 0.15) to (Min VIH + 0.15)  
(Min VIH + 0.15) to (Max VIL - 0.15)  
ns  
ns  
SCLK/SDATA Fall Time  
SMBus Operating  
Frequency  
tFSMB  
fMAXSMB  
Maximum SMBus operating frequency  
400  
kHz  
5
1Guaranteed by design and characterization, not 100% tested in production.  
2Control input must be monotonic from 20% to 80% of input swing.  
3Time from deassertion until outputs are >200 mV  
4DIF_IN input  
5The differential input clock must be running for the SMBus to be active  
©2018 Integrated Device Technology, Inc  
5
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
Electrical Characteristics–Input/Supply/Common Parameters  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
Supply Voltage  
SYMBOL  
VDDx  
CONDITIONS  
MIN  
3.135  
3.135  
TYP  
3.3  
MAX  
3.465  
3.465  
UNITS NOTES  
Supply voltage for core and analog  
Supply voltage for differential outputs  
V
V
VDDIO  
3.3  
Ambient Operating  
Temperature  
TAMB  
VIH  
Industrial range  
-40  
2
85  
VDD + 0.3  
0.8  
°C  
V
Single-ended inputs, except SMBus, tri-level  
Input High Voltage  
Input Low Voltage  
inputs  
Single-ended inputs, except SMBus, tri-level  
inputs  
VIL  
GND - 0.3  
V
Input High Voltage  
Input Mid Voltage  
Input Low Voltage  
VIH  
VIL  
VIL  
IIN  
Tri-Level Inputs (_tri suffix)  
2.2  
1.2  
VDD + 0.3  
V
V
Tri-Level Inputs (_tri suffix)  
Tri-Level Inputs (_tri suffix)  
VDD/2  
1.8  
0.8  
5
GND - 0.3  
-5  
V
Single-ended inputs, VIN = GND, VIN = VDD  
uA  
Single-ended inputs  
VIN = 0 V; Inputs with internal pull-up resistors  
IN = VDD; Inputs with internal pull-down resistors  
Input Current  
IINP  
-100  
100  
uA  
V
Fibyp  
Fipll  
VDD = 3.3 V, Bypass mode  
1
400  
102  
7
MHz  
Input Frequency  
Pin Inductance  
VDD = 3.3 V, 100MHz PLL mode  
98.5  
100.00  
MHz  
nH  
pF  
5
1
Lpin  
CIN  
Logic Inputs, except DIF_IN  
DIF_IN differential clock inputs  
Output pin capacitance  
1.5  
1.5  
5
1
Capacitance  
CINDIF_IN  
COUT  
2.7  
6
pF  
1,4  
1
pF  
From VDD Power-Up and after input clock  
stabilization or de-assertion of PD# to 1st clock  
Clk Stabilization  
TSTAB  
1.2  
1.8  
ms  
1,2  
Input SS Modulation  
Frequency PCIe  
Allowable Frequency for PCIe Applications  
(Triangular Modulation)  
fMODINPCIe  
tLATOE#  
tDRVPD  
30  
4
31.6  
5
33  
10  
kHz  
DIF start after OE# assertion  
DIF stop after OE# deassertion  
DIF output enable after  
OE# Latency  
Tdrive_PD#  
clocks 1,2,3  
85  
300  
us  
1,3  
PD# de-assertion  
Tfall  
tF  
Fall time of control inputs  
5
5
ns  
ns  
2
2
Trise  
tR  
Rise time of control inputs  
1Guaranteed by design and characterization, not 100% tested in production.  
2Control input must be monotonic from 20% to 80% of input swing.  
3Time from deassertion until outputs are >200 mV, PLL mode.  
4DIF_IN input  
5 This parameter reflects the operating range after locking to a 100MHz input.  
©2018 Integrated Device Technology, Inc  
6
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
Electrical Characteristics–DIF HCSL/LP-HCSL Outputs  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
INDUSTRY  
LIMIT  
0.6 - 4.0  
20  
PARAMETER  
SYMBOL  
dV/dt  
CONDITIONS  
MIN  
2.0  
TYP MAX  
UNITS NOTES  
V/ns  
%
Slew rate  
Slew rate matching  
Max Voltage  
Scope averaging on  
2.8  
4
4.0  
15  
1,2,3  
1,2,4,7  
7,8  
dV/dt  
Slew rate matching, Scope averaging on  
Measurement on single ended signal using  
absolute value. (Scope averaging off)  
Δ
Vmax  
Vmin  
660  
-111  
794  
-49  
870  
1150  
-300  
mV  
Min Voltage  
7,8  
Crossing Voltage (abs)  
Vcross_abs  
Scope averaging off  
302  
367  
32  
453  
74  
250 - 550  
140  
mV  
mV  
1,5,7  
1,6,7  
Crossing Voltage (var)  
-Vcross  
Δ
Scope averaging off  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Measured from differential waveform  
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around  
differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the  
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the  
oscilloscope is to use for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.  
Clock rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute)  
allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.  
Δ
7 At default SMBus settings.  
8 If driving a receiver with input terminations, the Vmax and Vmin values will be halved.  
Electrical Characteristics–Current Consumption  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
IDDx  
CONDITIONS  
MIN  
TYP  
22  
MAX UNITS NOTES  
All other VDD pins, All outputs @100MHz, CL =  
30  
65  
mA  
mA  
2
Ω
2pF; Zo=85  
VDDA+VDDR pins, All outputs @100MHz, CL =  
IDDA+R  
56  
1,2  
Operating Supply Current  
Ω
2pF; Zo=85  
VDDIO pins, All outputs @100MHz, CL = 2pF;  
IDDO  
84  
100  
mA  
2
Ω
Zo=85  
IDDx  
IDDA+R  
IDDO  
All other VDD pins, all outputs Low/Low  
VDDA+VDDR pins, all outputs Low/Low  
VDDIO pins, all outputs Low/Low  
mA  
mA  
mA  
1,2  
1,2  
1,2  
0.9  
4.3  
0.1  
2
6
Powerdown Current  
0.2  
1.  
Includes VDDR if applicable  
©2018 Integrated Device Technology, Inc  
7
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
Electrical Characteristics–Skew and Differential Jitter Parameters  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
SYMBOL  
tSKEW_PLL  
tPD_BYP  
CONDITIONS  
MIN  
-100  
2.2  
TYP  
-4  
MAX UNITS NOTES  
1,2,4,5,6,  
Input-to-Output Skew in PLL mode  
@100MHz, nominal temperature and voltage  
Input-to-Output Skew in Bypass mode  
@100MHz, nominal temperature and voltage  
Input-to-Output Skew Variation in PLL mode  
@100MHz, across voltage and temperature  
Input-to-Output Skew Variation in Bypass mode  
@100MHz, across voltage and temperature,  
100  
3.6  
50  
ps  
ns  
ps  
8
2.9  
0.0  
1,2,3,8  
tDSPO_PLL  
-50  
1,2,3,8  
1,2,3,8  
-250  
-350  
0.0  
0.0  
30  
250  
350  
50  
ps  
ps  
ps  
T
AMB = 0C to 70C, default slew rate  
Input-to-Output Skew Variation in Bypass mode  
@100MHz, across voltage and temperature,  
CLK_IN, DIF[x:0]  
tDSPO_BYP  
1,2,3,8  
1,2,3,8  
T
AMB = -40C to 85C, default slew rate  
Output-to-Output Skew across all outputs,  
common to PLL and Bypass mode, @100MHz,  
default slew rate  
DIF[x:0]  
tSKEW_ALL  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
jpeak-hibw  
jpeak-lobw  
pllHIBW  
pllLOBW  
tDC  
LOBW#_BYPASS_HIBW = 1  
0
0
1.3  
1.3  
2.6  
1.0  
50  
2.5  
2
dB  
dB  
7,8  
7,8  
8,9  
8,9  
1
LOBW#_BYPASS_HIBW = 0  
LOBW#_BYPASS_HIBW = 1  
LOBW#_BYPASS_HIBW = 0  
Measured differentially, PLL Mode  
Measured differentially, Bypass Mode @100MHz  
PLL mode  
2
4
MHz  
MHz  
%
PLL Bandwidth  
0.7  
45  
-1  
1.4  
55  
0
Duty Cycle  
Duty Cycle Distortion  
tDCD  
-0.2  
13  
%
1,10  
1,11  
1,11  
50  
5
ps  
Jitter, Cycle to cycle  
tjcyc-cyc  
Additive Jitter in Bypass Mode  
0.2  
ps  
1
2
3
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.  
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.  
4 This parameter is deterministic for a given device  
5
Measured with scope averaging on to find mean value.  
6.This value is programmable, see I2O Programming Table.  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8.  
Guaranteed by design and characterization, not 100% tested in production.  
9
Measured at 3 db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.  
11 Measured from differential waveform.  
©2018 Integrated Device Technology, Inc  
8
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common  
Clocked (CC) Architectures  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
INDUSTRY  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
13  
MAX  
30  
UNITS  
Notes  
1,2,3  
LIMIT  
86  
tjphPCIeG1-CC  
PCIe Gen 1  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
(PLL BW of 5-16MHz or 8-5MHz,  
CDR = 5MHz)  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
(PLL BW of 5-16MHz or 8-5MHz,  
CDR = 5MHz)  
ps (p-p)  
ps  
(rms)  
0.3  
0.7  
3
1,2  
tjphPCIeG2-CC  
ps  
(rms)  
1.6  
3.1  
Phase Jitter,  
PLL Mode  
1.0  
1,2  
1,2  
PCIe Gen 3  
(PLL BW of 2-4MHz or 2-5MHz,  
CDR = 10MHz)  
ps  
(rms)  
0.35  
1
tjphPCIeG3-CC  
0.24  
PCIe Gen 4  
(PLL BW of 2-4MHz or 2-5MHz,  
CDR = 10MHz)  
ps  
(rms)  
0.30  
0.5  
tjphPCIeG4-CC  
tjphPCIeG1-CC  
0.24  
0.01  
1,2  
1,2  
PCIe Gen 1  
0.05  
ps (p-p)  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
(PLL BW of 5-16MHz or 8-5MHz,  
CDR = 5MHz)  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
(PLL BW of 5-16MHz or 8-5MHz,  
CDR = 5MHz)  
ps  
(rms)  
0.01  
0.05  
0.05  
1,2,4  
1,2,4  
tjphPCIeG2-CC  
ps  
(rms)  
Additive Phase Jitter,  
Bypass mode  
0.000  
n/a  
PCIe Gen 3  
(PLL BW of 2-4MHz or 2-5MHz,  
CDR = 10MHz)  
PCIe Gen 4  
(PLL BW of 2-4MHz or 2-5MHz,  
CDR = 10MHz)  
ps  
(rms)  
tjphPCIeG3-CC  
0.01  
0.01  
0.05  
0.05  
1,2,4  
1,2,4  
ps  
(rms)  
tjphPCIeG4-CC  
1 Applies to all outputs, when driven by 9SQL4958 or equivalent.  
2 Based on PCIe Base Specification Rev4.0 version 0.7 draft. See http://www.pcisig.com for latest specifications.  
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12  
.
4 For RMS values additive jitter is calculated by solving the following equation for b [a^2 + b^2 = c^2] where "a" is rms input jitter and "c" is rms  
total jitter.  
©2018 Integrated Device Technology, Inc  
9
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Separate  
Reference Independent Spread (SRIS) Architectures  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
INDUSTRY  
PARAMETER  
SYMBOL  
tjphPCIeG1-  
CONDITIONS  
PCIe Gen 1  
MIN  
TYP  
n/a  
MAX  
UNITS  
Notes  
1,2,3  
LIMIT  
n/a  
ps (p-p)  
SRIS  
tjphPCIeG2-  
PCIe Gen 2  
(PLL BW of 16MHz , CDR = 5MHz)  
ps  
(rms)  
0.8  
0.6  
1.2  
2
1,2  
1,2  
SRIS  
Phase Jitter, PLL  
Mode  
PCIe Gen 3  
(PLL BW of 2-4MHz or 2-5MHz,  
CDR = 10MHz)  
tjphPCIeG3-  
ps  
(rms)  
0.68  
0.7  
SRIS  
PCIe Gen 4  
(PLL BW of 2-4MHz or 2-5MHz,  
CDR = 10MHz)  
tjphPCIeG4-  
ps  
(rms)  
n/a  
n/a  
1,2  
SRIS  
tjphPCIeG1-  
PCIe Gen 1  
n/a  
0.0  
ps (p-p)  
1,2,5  
1,2,4  
SRIS  
PCIe Gen 2  
(PLL BW of 16MHz , CDR = 5MHz)  
PCIe Gen 3  
(PLL BW of 2-4MHz or 2-5MHz,  
CDR = 10MHz)  
PCIe Gen 4  
(PLL BW of 2-4MHz or 2-5MHz,  
CDR = 10MHz)  
ps  
(rms)  
tjphPCIeG2-  
0.02  
SRIS  
Additive Phase Jitter,  
Bypass mode  
n/a  
tjphPCIeG3-  
ps  
(rms)  
0.02  
0.0  
n/a  
1,2,4  
SRIS  
tjphPCIeG4-  
ps  
(rms)  
1,2,4,5  
SRIS  
1 Applies to all outputs, when driven by 9SQL4958 or equivalent  
2 Based on PCIe Base Specification Rev3.1a. These filters are different than Common Clock filters. See http://www.pcisig.com for latest  
specifications. 0.7ps is the Intel specified limit, which may differ from the PCI SIG limit.  
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12  
.
4 For RMS values, additive jitter is calculated by solving the following equation for b [a^2 + b^2 = c^2] where "a" is rms input jitter and "c" is rms  
total jitter.  
5 SRIS is not currently defined for PCIe Gen1 and Gen4.  
Electrical Characteristics–Filtered Phase Jitter Parameters - QPI/UPI  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
QPI & SMI  
(100MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
MIN  
TYP  
MAX  
IND.LIMIT  
UNITS  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
Notes  
1,2  
0.15  
0.3  
0.5  
Phase Jitter, PLL  
Mode  
tjphQPI_UPI  
0.08  
0.07  
0.00  
0.02  
0.02  
0.1  
0.1  
0.3  
0.2  
1,2  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
QPI & SMI  
1,2  
0.05  
0.09  
0.08  
1,2,3  
1,2,3  
1,2,3  
(100MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
Additive Phase  
Jitter, Bypass mode  
tjphQPI_UPI  
n/a  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
(rms)  
?
1 Applies to all outputs, when driven by 9SQL4958 or equivalent  
2 Calculated from Intel-supplied Clock Jitter Tool  
3 For RMS values additive jitter is calculated by solving the following equation for b [a^2 + b^2 = c^2] where "a" is rms input jitter and "c" is rms  
total jitter.  
©2018 Integrated Device Technology, Inc  
10  
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
Electrical Characteristics–Unfiltered Phase Jitter Parameters - 12kHz to  
20MHz  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
Phase Jitter, PLL  
Mode  
Phase Jitter, PLL  
Mode  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
IND.LIMIT  
UNITS  
fs  
(rms)  
fs  
(rms)  
fs  
(rms)  
Notes  
1,2  
tjph12k-20MHi  
PLL High BW, SSC OFF, 100MHz  
171  
250  
n/a  
tjph12k-20MLo  
tjph12k-20MByp  
PLL Low BW, SSC OFF, 100MHz  
183  
109  
250  
150  
n/a  
n/a  
1,2  
Additive Phase  
Jitter, Bypass mode  
Bypass Mode, SSC OFF, 100MHz  
1,2,3  
1 Applies to all outputs. Wenzel clock source.  
2 12kHz to 20MHz brick wall filter.  
3 For RMS values additive jitter is calculated by solving the following equation for b [a^2 + b^2 = c^2] where "a" is rms input jitter and "c" is rms  
total jitter.  
Clock Periods–Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC OFF  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
DIF  
100.00  
9.94900  
9.99900  
10.00000  
10.00100  
10.05100  
ns  
1,2,3  
Clock Periods–Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC ON  
Units Notes  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
DIF  
99.75  
9.94906  
9.99906  
10.02406  
10.02506  
10.02607  
10.05107  
10.10107  
ns  
1,2,3  
Notes:  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ accuracy  
requirements (+/-100ppm). The 9ZML12xx does not contribute to ppm error.  
3
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode  
Test Loads  
Differential Output Terminations*  
9ZML Differential Test Loads  
Ω Ω  
Device  
DIF Zo ( ) Rs ( )  
9ZML123x  
9ZML123x  
9ZML125x  
9ZML125x  
85  
100  
85  
27  
33  
Internal  
7.5  
Zo = 85Dif.,  
10 inches  
Rs  
Rs  
100  
2pF  
2pF  
*Contact factory for versions of this device with Zo=100  
Ω
LP-HCSL  
Differential  
Output  
Rs are external on 9ZML123x devices  
and internal on 9ZML125x devices  
©2018 Integrated Device Technology, Inc  
11  
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
General SMBus Serial Interface Information for 9ZML1232E / 9ZML1252E  
How to Write  
How to Read  
▪ Controller (host) sends a start bit  
▪ Controller (host) will send a start bit  
▪ Controller (host) sends the write address  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the write address  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the beginning byte location = N  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the beginning byte location = N  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the byte count = X  
▪ IDT clock will acknowledge  
▪ Controller (host) will send a separate start bit  
▪ Controller (host) sends the read address  
▪ IDT clock will acknowledge  
▪ Controller (host) starts sending Byte N through Byte N+X-1  
▪ IDT clock will acknowledge each byte one at a time  
▪ Controller (host) sends a Stop bit  
▪ IDT clock will send the data byte count = X  
▪ IDT clock sends Byte N+X-1  
▪ IDT clock sends Byte 0 through Byte X (if X(H) was written to  
Index Block Write Operation  
Byte 8)  
Controller (Host)  
IDT (Slave/Receiver)  
▪ Controller (host) will need to acknowledge each byte  
▪ Controller (host) will send a not acknowledge bit  
▪ Controller (host) will send a stop bit  
T
starT bit  
Slave Address  
WR  
WRite  
Index Block Read Operation  
ACK  
ACK  
ACK  
ACK  
Controller (Host)  
starT bit  
IDT (Slave/Receiver)  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
T
Slave Address  
WR  
WRite  
ACK  
ACK  
Beginning Byte = N  
O
O
O
RT  
Repeat starT  
Slave Address  
ReaD  
O
O
O
RD  
Byte N + X - 1  
ACK  
ACK  
P
stoP bit  
Data Byte Count=X  
Beginning Byte N  
ACK  
ACK  
9ZML1232E / 9ZML1252E SMBus Addressing  
SMB_A(1:0)_tri SMBus Address (Rd/Wrt bit = 0)  
O
O
O
00  
0M  
01  
M0  
MM  
M1  
10  
D8  
DA  
DE  
C2  
C4  
C6  
CA  
CC  
CE  
O
O
O
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
1M  
11  
©2018 Integrated Device Technology, Inc  
12  
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
SMBusTable: PLL Mode, and Frequency Select Register  
Byte 0  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Pin #  
Name  
Control Function  
PLL Operating Mode Rd back 1  
PLL Operating Mode Rd back 0  
Input Select Readback  
Reserved  
Type  
R
R
0
1
Default  
Latch  
Latch  
Real  
0
PLL Mode bit [1]  
PLL Mode bit [0]  
SEL_A_B#  
See PLL Operating Mode  
Readback Table  
DIF_INB  
DIF_INA  
R
Enable S/W control of PLL BW and  
Input select  
PLL_InSEL_SW_EN  
RW  
Pin Control SMBus Control  
0
Bit 3  
PLL Mode bit [1]  
PLL Mode bit [0]  
PLL Operating Mode 1  
PLL Operating Mode 1  
Reserved  
RW  
RW  
See PLL Operating Mode  
Readback Table1  
1
1
1
Bit 2  
Bit 1  
Bit 0  
1. Note, Changing the PLL operating mode between HiBW or LoBW and Bypass mode or between Bypass mode and HiBW or LoBW  
requires a system reset. Changing the PLL operating mode between HiBW and LoBw or between LoBW and HiBW does not require a  
system reset.  
SMBusTable: Output Disable Register  
Byte 1  
Bit 7  
Pin #  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DIF_7_En  
DIF_6_En  
DIF_5_En  
DIF_4_En  
DIF_3_En  
DIF_2_En  
DIF_1_En  
DIF_0_En  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
1
1
1
1
1
1
1
1
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Low/Low  
Pin Control  
SMBusTable: Output Disable Register  
Byte 2  
Bit 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
1
1
1
1
Reserved  
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
DIF_11_En  
DIF_10_En  
DIF_9_En  
DIF_8_En  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
RW  
RW  
RW  
RW  
Low/Low  
Pin Control  
SMBusTable: Reserved Register  
Byte 3 Pin # Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
SMBusTable: Reserved Register  
Byte 4 Pin # Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
Bit 0  
©2018 Integrated Device Technology, Inc  
13  
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
SMBusTable: Vendor & Revision ID Register  
Byte 5  
Bit 7  
Pin #  
-
Name  
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
Control Function  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
0
1
0
0
0
0
0
1
-
-
-
-
-
-
-
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
REVISION ID  
E rev = 0100  
-
-
-
-
-
-
-
-
VENDOR ID  
SMBusTable: DEVICE ID  
Byte 6 Pin #  
Bit 7  
Name  
Control Function  
Device ID 7 (MSB)  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
-
1
1
1
X
1
1
0
X
-
-
-
-
-
-
-
Device ID 6  
Device ID 5  
Device ID 4  
Device ID 3  
Device ID 2  
Device ID 1  
Device ID 0  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
9ZML1232=EC  
9ZML1233=ED  
9ZML1252=FC  
9ZML1253=FD  
SMBusTable: Byte Count Register  
Byte 7  
Bit 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
1
0
0
0
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
-
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
Default value is 8 hex, so 9  
bytes (0 to 8) will be read back  
by default.  
-
-
-
-
Writing to this register configures how  
many bytes will be read back.  
SMBusTable:Output Skew RegisterA (when Input Clock A is selected)  
Byte 8  
Bit 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
I2O_FB_ASkew2  
I2O_FB_ASkew1  
I2O_FB_ASkew0  
Binary value of number of VCO  
periods that outputs will be  
pulled earlier than input.  
Channel A Output delay programming  
(early)  
RW  
RW  
0
0
Bit 1  
Bit 0  
Note: For example, at 2.4GHz, each VCO period is 416.7ps and there are 24 VCO periods in a 100MHz output. Each write to bits [2:0] will  
pull the output a early by that number of VCO periods. Writing '110' 4 times would pull the output back in phase with the input. Writing '001'  
twice will accomplish the same result as writing '010' once - pulling the output 2 VCO periods earlier.  
SMBusTable:Output Skew RegisterA (when Input Clock B is selected)  
Byte 9  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Binary value of number of VCO  
periods that outputs will be  
earlier than input. Default is 0.  
I2O_FB_BSkew2  
I2O_FB_BSkew1  
I2O_FB_BSkew0  
RW  
RW  
RW  
Channel B Output delay programming  
(early)  
0
Bit 0  
Note: For example, at 2.4GHz, each VCO period is 416.7ps and there are 24 VCO periods in a 100MHz output. Each write to bits [2:0] will  
pull the output a early by that number of VCO periods. Writing '110' 4 times would pull the output back in phase with the input. Writing '001'  
twice will accomplish the same result as writing '010' once - pulling the output 2 VCO periods earlier.  
©2018 Integrated Device Technology, Inc  
14  
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
Package Outline Drawings  
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is  
the most current data available.  
www.idt.com/document/psc/nlnlg72-package-outline-100-x-100-mm-body-epad-59-mm-sq-050-mm-pitch-vfqfpn-sawn  
Ordering Information  
Part Number  
9ZML1232EKILF  
9ZML1232EKILFT  
9ZML1252EKILF  
9ZML1252EKILFT  
Shipping Package  
Trays  
Package  
72-pin QFN  
72-pin QFN  
72-pin QFN  
72-pin QFN  
Temperature  
-40 to +85°C  
-40 to +85°C  
-40 to +85°C  
-40 to +85°C  
Tape and Reel  
Trays  
Tape and Reel  
“LF” designates PB-free configuration, RoHS compliant.  
“E” is the device revision designator (will not correlate with the datasheet revision).  
Marking Diagrams  
1. “L” denotes RoHS compliant package.  
2. “LOT” denotes the lot number.  
ICS  
3. “COO” denotes country of origin.  
9ZML1232EKIL  
LOT  
COO YYWW  
4. “YYWW” denotes the last two digits of the year and week the part was assembled.  
ICS  
9ZML1252EKIL  
LOT  
COO YYWW  
Revision History  
Issue Date Description  
1. Updated electrical tables with characterization data.  
2. Updated VDDIO minimum VDDIO value from 1.05V to 3.135V  
3. Updated block diagrams to remove color fill.  
4. Moved to Preliminary.  
1/27/2017  
1. Finalized Electrical Tables.  
2. Removed Byte 0, bit 0 from SMBus - only Hardware can select A or B input.  
3. Added notes about functionality of Byte 0 [2:1].  
4. Move to final  
1. Reverted back to original Device ID Scheme, byte 6 updated accordingly:  
9ZML1232=EC  
1/31/2017  
4/17/2017  
9ZML1252=FC  
12/1/2017  
4/12/2018  
Removed "5V tolerant" reference on pins 13 and 14 descriptions.  
Updated absolute maximum supply voltage rating and VIHSMB to 3.9V.  
©2018 Integrated Device Technology, Inc  
15  
April 12, 2018  
9ZML1232E / 9ZML1252E Datasheet  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.idt.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve to modify the products and/or specifications described herein at any time, without notice, at  
IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in  
customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any  
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-  
lectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.  
©2018 Integrated Device Technology, Inc  
16  
April 12, 2018  
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