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8SLVP2108

型号：

8SLVP2108

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

22 页

PDF大小：

847 K

下载PDF手册
Low Phase Noise, Dual 1-to-8, 3.3V,  
2.5V LVPECL Output Fanout Buffer  
8SLVP2108  
Datasheet  
General Description  
Features  
The 8SLVP2108 is a high-performance differential dual 1:8  
LVPECL fanout buffer. The device is designed for the fanout of  
high-frequency, very low additive phase-noise clock and data  
signals. The 8SLVP2108 is characterized to operate from a 3.3V or  
2.5V power supply. Guaranteed output-to-output and part-to-part  
skew characteristics make the 8SLVP2108 ideal for those clock  
distribution applications demanding well-defined performance and  
repeatability. Two independent buffers with eight low skew outputs  
each are available. The integrated bias voltage references enable  
easy interfacing of single-ended signals to the device inputs. The  
device is optimized for low power consumption and low additive  
phase noise.  
• Two 1:8, low skew, low additive jitter LVPECL fanout buffers  
• Two differential clock inputs  
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can  
accept the following differential input levels: LVDS, LVPECL,  
CML  
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can  
also accept single-ended LVCMOS levels. See Applications  
section Wiring the Differential Input Levels to Accept  
Single-ended Levels (Figure 1A and Figure 1B).  
• Maximum input clock frequency: 2GHz  
• Output bank skew: 15ps (typical)  
• Propagation delay: 390ps (maximum)  
• Low additive phase jitter, RMS: 54fs (maximum)  
(fREF = 156.25MHz, VPP = 1V, 12kHz – 20MHz, VCC = 3.3V)  
• Full 3.3V and 2.5V supply voltage  
• Maximum device current consumption (IEE): 143mA  
• Available in Lead-free (RoHS 6), 48-Lead VFQFN package  
• Supports case temperature 105°C operations  
• -40°C to 85°C ambient operating temperature  
Block Diagram  
QA0  
nQA0  
QA1  
nQA1  
V
CC  
QA2  
nQA2  
PCLKA  
nPCLKA  
  
  
  
  
  
  
  
  
Pin Assignment  
36 35 34 33 32 31 30 29 28 27 26 25  
Voltage  
Reference  
VCC  
37  
38  
39  
40  
24 VCC  
VREFA  
QA7  
nQA4  
QA4  
QB3  
nQB3  
QB4  
23  
22  
nQA7  
QB0  
nQB0  
21 nQA3  
8SLVP2108  
nQB4  
20  
19  
18  
17  
16  
QA3  
nQA2  
QA2  
41  
42  
43  
44  
45  
46  
48-lead VFQFN  
7mm x 7mm x 0.8mm  
package body  
QB5  
nQB5  
QB1  
nQB1  
QB6  
nQB6  
QB7  
nQA1  
QA1  
NL Package  
Top View  
V
CC  
QB2  
15 nQA0  
nQB2  
PCLKB  
QA0  
14  
47  
48  
1
nQB7  
VCC  
13 VCC  
2 3 4 5 6 7 8 9 10 11 12  
nPCLKB  
  
  
  
  
  
  
  
  
Voltage  
Reference  
VREFB  
QB7  
nQB7  
©2016 Integrated Device Technology, Inc.  
1
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Pin Descriptions and Characteristics  
Table 1. Pin Descriptions  
Number  
1, 12  
2, 11  
3
Name  
VEE  
Type  
Description  
Power  
Unused  
Input  
Negative supply pins.  
nc  
Do not connect.  
PCLKB  
Pulldown  
Non-inverting LVPECL differential clock/data input.  
Pullup/  
Pulldown  
4
5
nPCLKB  
VREFB  
VCC  
Input  
Output  
Power  
Output  
Input  
Inverting LVPECL differential clock input.  
Bias voltage reference for the PCLKB, nPCLKB input pair.  
6, 7, 13,  
24, 37, 48  
Power supply pins.  
8
VREFA  
nPCLKA  
Bias voltage reference for the PCLKA, nPCLKA input pair.  
Pullup/  
Pulldown  
9
Inverting LVPECL differential clock input.  
10  
PCLKA  
Input  
Pulldown  
Non-inverting LVPECL differential clock/data input.  
Differential output pair A0. LVPECL interface levels.  
Differential output pair A1. LVPECL interface levels.  
Differential output pair A2. LVPECL interface levels.  
Differential output pair A3. LVPECL interface levels.  
Differential output pair A4. LVPECL interface levels.  
Differential output pair A5. LVPECL interface levels.  
Differential output pair A6. LVPECL interface levels.  
Differential output pair A7. LVPECL interface levels.  
Differential output pair B0. LVPECL interface levels.  
Differential output pair B1. LVPECL interface levels.  
Differential output pair B2. LVPECL interface levels.  
Differential output pair B3. LVPECL interface levels.  
Differential output pair B4. LVPECL interface levels.  
Differential output pair B5. LVPECL interface levels.  
Differential output pair B6. LVPECL interface levels.  
Differential output pair B7. LVPECL interface levels.  
14, 15  
16, 17  
18, 19  
20, 21  
22, 23  
25, 26  
27, 28  
29, 30  
31, 32  
33, 34  
35, 36  
38, 39  
40, 41  
42, 43  
44, 45  
46, 47  
QA0, nQA0  
QA1, nQA1  
QA2, nQA2  
QA3, nQA3  
QA4, nQA4  
QA5, nQA5  
QA6, nQA6  
QA7, nQA7  
QB0, nQB0  
QB1, nQB1  
QB2, nQB2  
QB3, nQB3  
QB4, nQB4  
QB5, nQB5  
QB6, nQB6  
QB7, nQB7  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
pF  
Input Capacitance  
Input Pulldown Resistor  
Input Pullup Resistor  
2
RPULLDOWN  
RPULLUP  
51  
51  
k  
k  
©2016 Integrated Device Technology, Inc.  
2
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or  
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VCC  
Inputs, VI  
4.6V  
-0.5V to VCC + 0.5V  
Outputs, IO (LVPECL)  
Continuous Current  
Surge Current  
50mA  
100mA  
Input Sink/Source, IREF  
±2mA  
Maximum Junction Temperature, TJ,MAX  
Storage Temperature, TSTG  
125 C  
-65C to 150C  
2000V  
ESD - Human Body Model (NOTE 1)  
ESD - Charged Device Model (NOTE 1)  
1500V  
DC Electrical Characteristics  
Table 3A. Power Supply DC Characteristics, V = 3.3V ± 5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
Typical  
3.3V  
Maximum  
3.465  
Units  
V
Power Supply Voltage  
Power Supply Current  
3.135  
IEE  
120  
143  
mA  
QA[0:7] and QB[0:7]  
terminated 50to VCC – 2V  
ICC  
Power Supply Current  
595  
706  
mA  
Table 3B. Power Supply DC Characteristics, V = 2.5V ± 5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
Typical  
2.5V  
Maximum  
2.625  
Units  
V
Power Supply Voltage  
Power Supply Current  
2.375  
IEE  
113  
133  
mA  
QA[0:7] and QB[0:7]  
terminated 50to VCC – 2V  
ICC  
Power Supply Current  
594  
705  
mA  
©2016 Integrated Device Technology, Inc.  
3
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Table 3C. LVPECL DC Characteristics, V = 3.3V ± 5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input High PCLKA, nPCLKA  
IIH  
V
CC = VIN = 3.465V  
150  
µA  
Current  
PCLKB, nPCLKB  
PCLKA, PCLKB  
nPCLKA, nPCLKB  
VCC = 3.465V, VIN = 0V  
VCC = 3.465V, VIN = 0V  
-10  
µA  
µA  
Input Low  
Current  
IIL  
-150  
Reference Voltage for Input  
Bias  
VREFx  
IREF = 2mA  
VCC – 1.82  
VCC – 1.48  
VCC – 1.27  
V
VOH  
VOL  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
VCC – 1.25  
VCC – 1.70  
VCC – 1.00  
VCC – 1.47  
VCC – 0.76  
VCC – 1.25  
V
V
NOTE: V  
denotes V  
and V  
REFx  
REFA REFB.  
NOTE 1: Outputs terminated with 50  
to V – 2V.  
CC  
Table 3D. LVPECL DC Characteristics, V = 2.5V ± 5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
PCLKA, nPCLKA  
PCLKB, nPCLKB  
IIH Input High Current  
VCC = VIN = 2.625V  
150  
µA  
PCLKA, PCLKB  
VCC = 2.625V, VIN = 0V  
VCC = 2.625V, VIN = 0V  
IREF = 2mA  
-10  
µA  
µA  
V
IIL  
Input Low Current  
nPCLKA, nPCLKB  
-150  
VREFx  
VOH  
Reference Voltage for Input Bias; NOTE 2  
Output High Voltage; NOTE 1  
VCC – 1.81  
VCC – 1.26  
VCC – 1.67  
VCC – 1.47 VCC – 1.27  
VCC – 1.00  
VCC – 1.45  
VCC – 0.75  
VCC – 1.22  
V
VOL  
Output Low Voltage; NOTE 1  
V
NOTE: V  
denotes V  
and V  
REFx  
REFA REFB.  
NOTE 1: Outputs terminated with 50  
to V – 2V.  
CC  
NOTE 2: For V < 3V, the use of an alternate bias voltage source is recommended.  
CC  
©2016 Integrated Device Technology, Inc.  
4
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
AC Electrical Characteristics  
Table 4A. AC Electrical Characteristics, V = 3.3V ± 5% or 2.5V ± 5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol  
fREF  
Parameter  
Test Conditions  
Minimum  
Typical Maximum Units  
Input Frequency  
Input Edge Rate  
PCLKA, nPCLKA and PCLKB, nPCLKB  
PCLKA, nPCLKA and PCLKB, nPCLKB  
2
GHz  
V/ns  
V/t  
1.5  
PCLKA, nPCLKA to any QAx, nQAx or  
PCLKB, nPCLKB to any QBx, nQBx for  
VPP=0.1V or 0.3V  
tPD  
Propagation Delay; NOTE 1  
120  
255  
390  
ps  
tsk(o)  
tsk(b)  
tsk(p)  
tsk(pp)  
Output Skew; NOTE 2, 3  
Output Bank Skew; NOTE 3, 4  
Pulse Skew  
29  
15  
4
63  
43  
ps  
ps  
ps  
ps  
25  
Part-to-Part Skew; NOTE 3, 5  
70  
154  
f
QB0 = 500MHz, VPP(PCLKB) = 0.15V,  
VCMR(PCLKB) = 1V;  
-55  
dB  
fQA7 = 62.5MHz, VPP(PCLKA) = 1V,  
VCMR(PCLKA) = 1V  
Spurious Suppression,  
Coupling from QA7 to QB0  
tJIT, SP  
fQB0 = 500MHz, VPP(PCLKB) = 0.15V,  
VCMR(PCLKB) = 1V;  
fQA7 = 15.625MHz, VPP(PCLKA) = 1V,  
VCMR(PCLKA) = 1V  
-65  
dB  
ps  
Output Rise/ Fall Time;  
NOTE 6  
tR / tF  
VPP  
20% to 80%  
60  
100  
165  
fREF < 1.5GHz  
0.1  
0.2  
1.5  
1.5  
V
V
Differential Input Voltage;  
NOTE 7, 8  
fREF 1.5GHz  
Common Mode Input Voltage;  
NOTE 7, 8, 9  
VCMR  
VO(pp)  
1.0  
V
CC – 0.3  
V
fREF 2GHz, VCC = 2.5V ± 5%  
fREF 2GHz, VCC = 3.3V ± 5%  
fREF 2GHz, VCC = 2.5V ± 5%  
fREF 2GHz, VCC = 3.3V ± 5%  
0.29  
0.31  
0.58  
0.62  
0.46  
0.48  
0.92  
0.96  
0.63  
0.67  
1.26  
1.34  
V
V
V
V
Output Voltage Swing,  
Peak-to-Peak  
Differential Output Voltage  
Swing, Peak-to-Peak  
VDIFF_OUT  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.  
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 4: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. Measured at the differential  
crosspoints.  
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and  
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.  
NOTE 6: Characterized with input signal meeting the input edge rate minimum specification.  
NOTE 7: For single-ended LVCMOS input applications, please refer to the Applications Information, Wiring the Differential Input to Accept  
Single-ended Levels, Figures 1A and 1B.  
NOTE 8: VIL should not be less than -0.3V. VIH should not be higher than VCC  
.
NOTE 9: Common mode input voltage is defined at the crosspoint.  
©2016 Integrated Device Technology, Inc.  
5
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Table 4B. Buffer Additive Phase Jitter, t , V = 3.3V ± 5%, V = 0V, T = -40°C to 85°C  
JIT  
CC  
EE  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical Maximum Units  
fREF = 122.88MHz Square Wave, VPP = 1V  
Integration Range: 1kHz – 40MHz  
97  
64  
64  
62  
46  
46  
50  
43  
43  
128  
81  
81  
75  
54  
54  
81  
51  
51  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fREF = 122.88MHz Square Wave, VPP = 1V  
Integration Range: 10kHz – 20MHz  
fREF = 122.88MHz Square Wave, VPP = 1V  
Integration Range: 12kHz – 20MHz  
fREF = 156.25MHz Square Wave, VPP = 1V  
Integration Range: 1kHz – 40MHz  
Buffer Additive Phase Jitter,  
fREF = 156.25MHz Square Wave, VPP = 1V  
Integration Range: 10kHz – 20MHz  
tJIT  
RMS; refer to Additive Phase  
Jitter Section  
f
REF = 156.25MHz Square Wave, VPP = 1V  
Integration Range: 12kHz – 20MHz  
fREF = 156.25MHz Square Wave, VPP = 0.5V  
Integration Range: 1kHz – 40MHz  
fREF = 156.25MHz Square Wave, VPP = 0.5V  
Integration Range: 10kHz – 20MHz  
fREF = 156.25MHz Square Wave, VPP = 0.5V  
Integration Range: 12kHz – 20MHz  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
Table 4C. Buffer Additive Phase Jitter, t , V = 2.5V ± 5%, V = 0V, T = -40°C to 85°C  
JIT  
CC  
EE  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical Maximum Units  
fREF = 122.88MHz Square Wave, VPP = 1V  
Integration Range: 1kHz – 40MHz  
100  
68  
68  
65  
48  
48  
53  
45  
45  
132  
86  
86  
77  
57  
57  
81  
56  
56  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fREF = 122.88MHz Square Wave, VPP = 1V  
Integration Range: 10kHz – 20MHz  
f
REF = 122.88MHz Square Wave, VPP = 1V  
Integration Range: 12kHz – 20MHz  
fREF = 156.25MHz Square Wave, VPP = 1V  
Integration Range: 1kHz – 40MHz  
Buffer Additive Phase Jitter,  
fREF = 156.25MHz Square Wave, VPP = 1V  
Integration Range: 10kHz – 20MHz  
tJIT  
RMS; refer to Additive Phase  
Jitter Section  
f
REF = 156.25MHz Square Wave, VPP = 1V  
Integration Range: 12kHz – 20MHz  
fREF = 156.25MHz Square Wave, VPP = 0.5V  
Integration Range: 1kHz – 40MHz  
fREF = 156.25MHz Square Wave, VPP = 0.5V  
Integration Range: 10kHz – 20MHz  
fREF = 156.25MHz Square Wave, VPP = 0.5V  
Integration Range: 12kHz – 20MHz  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
©2016 Integrated Device Technology, Inc.  
6
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental  
compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot  
and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a  
specified offset from the fundamental frequency to the power value of  
the fundamental. This ratio is expressed in decibels (dBm) or a ratio  
of the power in the 1Hz band to the power in the fundamental. When  
the required offset is specified, the phase noise is called a dBc value,  
which simply means dBm at a specified offset from the fundamental.  
By investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the entire  
time record of the signal. It is mathematically possible to calculate an  
expected bit error rate given a phase noise plot.  
Additive Phase Jitter @ 156.25MHZ, VPP = 1V  
12kHz to 20MHz = 46fs (typical)  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements have  
issues relating to the limitations of the equipment. Often the noise  
floor of the equipment is higher than the noise floor of the device. This  
is illustrated above. The device meets the noise floor of what is  
shown, but can actually be lower. The phase noise is dependent on  
the input source and measurement equipment.  
Measured using a Wenzel 156.25MHz Oscillator as the input source.  
©2016 Integrated Device Technology, Inc.  
7
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Parameter Measurement Information  
2V  
2V  
SCOPE  
SCOPE  
V
V
Qx  
CC  
Qx  
CC  
nQx  
nQx  
VEE  
VEE  
-1.3V±0.165V  
-0.5V±0.125V  
3.3V LVPECL Output Load Test Circuit  
2.5V LVPECL Output Load Test Circuit  
V
CC  
nQx  
Qx  
nPCLKA,  
nPCLKB  
nQy  
Qy  
PCLKA,  
PCLKB  
V
EE  
Differential Input Level  
Output Skew  
nQx  
Qx  
Part 1  
nQx  
Qx  
nQy  
Qy  
Part 2  
nQy  
tPLH  
tPHL  
Qy  
tsk(pp)  
tsk(p)= |tPHL - tPLH  
|
Part-to-Part Skew  
Pulse Skew  
©2016 Integrated Device Technology, Inc.  
8
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Parameter Measurement Information, continued  
nQX[0:7]  
nPCLKA,  
nPCLKB  
QX[0:7]  
PCLKA,  
PCLKB  
nQX[0:7]  
QX[0:7]  
nQA[0:7],  
nQB[0:7]  
tsk(b)  
QA[0:7],  
QB[0:7]  
tPD  
Where X is either Bank A or Bank B  
Bank Skew  
Propagation Delay  
nQA[0:7],  
nQB[0:7]  
VDIFF_OUT  
VO(pp)  
QA[0:7],  
QB[0:7]  
Differential Voltage Swing = 2 x Single-ended VO(pp)  
Output Rise/Fall Time  
Differential Output Voltage Swing  
©2016 Integrated Device Technology, Inc.  
9
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Applications Information  
Wiring the Differential Input to Accept Single-Ended Levels  
The 8SLVP2108 inputs can be interfaced to LVPECL, LVDS, CML or  
LVCMOS drivers. Figure 1A illustrates how to DC couple a single  
LVCMOS input to the 8SLVP2108. The value of the series resistance  
RS is calculated as the difference between the transmission line  
impedance and the driver output impedance. This resistor should be  
placed close to the LVCMOS driver. To avoid cross-coupling of  
single-ended LVCMOS signals, apply the LVCMOS signals to no  
more than one PCLK input.  
VIH  
Vth  
VIL  
RS  
A practical method to implement Vth is shown in Figure 1B below.  
LVCMOS  
The reference voltage Vth = V1 = VCC/2, is generated by the bias  
resistors R1 and R2. The bypass capacitor (C1) is used to help filter  
noise on the DC bias. This bias circuit should be located as close to  
the input pin as possible.  
The ratio of R1 and R2 might need to be adjusted to position the V1  
in the center of the input voltage swing. For example, if the input clock  
swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted  
VIH + VIL  
2
Vth  
=
to set V1 at 1.25V. The values below apply when both the  
single-ended swing and VCC are at the same voltage.  
Figure 1A. DC-Coupling a Single LVCMOS Input to the  
8SLVP2108  
When using single-ended signaling, the noise rejection benefits of  
differential signaling are reduced. Even though the differential input  
can handle full rail LVCMOS signaling, it is recommended that the  
amplitude be reduced, particularly if both input references are  
LVCMOS to minimize cross talk. The datasheet specifies a lower  
differential amplitude, however this only applies to differential signals.  
For single-ended applications, the swing can be larger, however VIL  
This configuration requires that the sum of the output impedance of  
the driver (Ro) and the series resistance (Rs) equals the transmission  
line impedance. R3 and R4 in parallel should equal the transmission  
line impedance; for most 50applications, R3 and R4 will be 100.  
The values of the resistors can be increased to reduce the loading for  
slower and weaker LVCMOS driver.  
Though some of the recommended components of Figure 1B might  
not be used, the pads should be placed in the layout so that they can  
be utilized for debugging purposes. The datasheet specifications are  
characterized and guaranteed by using a differential signal.  
cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V.  
Figure 1B shows a way to attenuate the PCLK input level by a factor  
of two as well as matching the transmission line between the  
LVCMOS driver and the 8SLVP2108 at both the source and the load.  
VC C  
VC C  
VCC  
VCC  
R3  
100  
R1  
1K  
Ro  
RS  
Zo = 50 Ohm  
+
Receiv er  
Driver  
V1  
R4  
-
100  
R2  
1K  
Ro +Rs = Zo  
C1  
0.1uF  
Figure 1B. Alternative DC Coupling a Single LVCMOS Input to the 8SLVP2108  
©2016 Integrated Device Technology, Inc.  
10  
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
3.3V LVPECL Clock Input Interface  
The PCLK /nPCLK accepts LVPECL, LVDS and other differential  
signals. Both differential signals must meet the VPP and VCMR input  
requirements. Figures 2A to 2C show interface examples for the  
PCLK/ nPCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. If the driver is  
from another vendor, use their termination recommendation. Please  
consult with the vendor of the driver component to confirm the driver  
termination requirements.  
3.3V  
3.3V  
3.3V  
R3  
R4  
125Ω  
125Ω  
Zo = 50Ω  
Zo = 50Ω  
PCLK  
nPCLK  
LVPECL  
Input  
LVPECL  
R1  
R2  
84Ω  
84Ω  
Figure 2A. PCLK/nPCLK Input Driven by a  
3.3V LVPECL Driver  
Figure 2B. PCLK/nPCLK Input Driven by a  
3.3V LVPECL Driver with AC Couple  
3.3V  
3.3V  
Zo = 50  
PCLK  
R1  
100  
nPCLK  
Zo = 50  
LVPECL  
Input  
LVDS  
Figure 2C. PCLK/nPCLK Input Driven by a  
3.3V LVDS Driver  
©2016 Integrated Device Technology, Inc.  
11  
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
2.5V LVPECL Clock Input Interface  
The PCLK /nPCLK accepts LVPECL, LVDS and other differential  
signals. Both differential signals must meet the VPP and VCMR input  
requirements. Figures 3A to 3C show interface examples for the  
PCLK/ nPCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. If the driver is  
from another vendor, use their termination recommendation. Please  
consult with the vendor of the driver component to confirm the driver  
termination requirements.  
2.5V  
2.5V  
2.5V  
PCLK  
nPCLK  
LVPECL  
Input  
LVPECL  
Figure 3A. PCLK/nPCLK Input Driven by a  
2.5V LVPECL Driver  
Figure 3B. PCLK/nPCLK Input Driven by a  
2.5V LVPECL Driver with AC Couple  
PCLK  
nPCLK  
Figure 3C. PCLK/nPCLK Input Driven by a  
2.5V LVDS Driver  
©2016 Integrated Device Technology, Inc.  
12  
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 4. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
PIN  
SOLDER  
EXPOSED HEAT SLUG  
PIN  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
©2016 Integrated Device Technology, Inc.  
13  
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
transmission lines. Matched impedance techniques should be used  
to maximize operating frequency and minimize signal distortion.  
Figures 5A and 5B show two different layouts which are  
recommended only as guidelines. Other suitable clock layouts may  
exist and it would be recommended that the board designers  
simulate to guarantee compatibility across all printed circuit and clock  
component process variations.  
The differential outputs are a low impedance follower output that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are designed to drive 50  
3.3V  
R3  
R4  
125  
125  
3.3V  
3.3V  
Zo = 50  
+
_
Input  
Zo = 50  
R1  
84  
R2  
84  
Figure 5A. 3.3V LVPECL Output Termination  
Figure 5B. 3.3V LVPECL Output Termination  
©2016 Integrated Device Technology, Inc.  
14  
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Termination for 2.5V LVPECL Outputs  
Figure 6A and Figure 6B show examples of termination for 2.5V  
LVPECLdriver. These terminations are equivalent to terminating 50  
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground  
level. The R3 in Figure 6B can be eliminated and the termination is  
shown in Figure 6C.  
2.5V  
VCC = 2.5V  
2.5V  
2.5V  
VCC = 2.5V  
50Ω  
R1  
R3  
250Ω  
250Ω  
+
50Ω  
50Ω  
+
–
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
2.5V LVPECL Driver  
R2  
R4  
62.5Ω  
62.5Ω  
R3  
18Ω  
Figure 6A. 2.5V LVPECL Driver Termination Example  
Figure 6B. 2.5V LVPECL Driver Termination Example  
2.5V  
VCC = 2.5V  
50Ω  
+
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
Figure 6C. 2.5V LVPECL Driver Termination Example  
©2016 Integrated Device Technology, Inc.  
15  
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8SLVP2108.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8SLVP2108 is the sum of the core power plus the power dissipated at the output(s).  
The following is the power dissipation for VCC = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 143mA = 495.50mW  
Power (outputs)MAX = 37.6mW/Loaded Output pair  
If all outputs are loaded, the total power is 16 * 37.6mW = 601.6mW  
Total PowerMAX (3.465V, with all outputs switching) = 495.50mW + 601.6mW = 1097.1mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 30.5°C/W per Table 5 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 1.097W * 30.5°C/W = 118.5°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 5. Thermal Resistance for 48-Lead VFQFN, Forced Convection  
JA  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
30.5°C/W  
26.7°C/W  
23.9°C/W  
©2016 Integrated Device Technology, Inc.  
16  
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.  
LVPECL output driver circuit and termination are shown in Figure 7.  
VCC  
Q1  
VOUT  
RL  
VCC - 2V  
Figure 7. LVPECL Driver Circuit and Termination  
To calculate worst case power dissipation at the outputs, use the following equations which assume a 50load, and a termination voltage of  
VCC – 2V. These are typical calculations.  
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.76V  
(VCC_MAX – VOH_MAX) = 0.76V  
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.25V  
(VCC_MAX – VOL_MAX) = 1.25V  
Pd_H is the power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VCC_MA – 2V))/RL] * (VCC_MA – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =  
[(2V – 0.76V)/50] * 0.76V = 18.85mW  
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MA – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =  
[(2V – 1.25V)/50] * 1.25V = 18.75mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 37.6mW  
©2016 Integrated Device Technology, Inc.  
17  
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Case Temperature Considerations  
This device supports applications in a natural convection environment which does not have any thermal conductivity through ambient air. The  
printed circuit board (PCB) is typically in a sealed enclosure without any natural or forced air flow and is kept at or below a specific temperature.  
The device package design incorporates an exposed pad (ePad) with enhanced thermal parameters which is soldered to the PCB where most  
of the heat escapes from the bottom exposed pad. For this type of application, it is recommended to use the junction-to-board thermal  
characterization parameter JB (Psi-JB) to calculate the junction temperature (TJ) and ensure it does not exceed the maximum allowed  
junction temperature in the Absolute Maximum Rating table.  
The junction-to-board thermal characterization parameter, JB, is calculated using the following equation:  
TJ = TCB + JB x Pd, Where  
TJ = Junction temperature at steady state condition in (oC).  
TCB = Case temperature (Bottom) at steady state condition in (oC).  
JB = Thermal characterization parameter to report the difference between junction temperature and the temperature of the board  
measured at the top surface of the board.  
Pd = power dissipation (W) in desired operating configuration.  
T
J
T
CB  
The ePad provides a low thermal resistance path for heat transfer to the PCB and represents the key pathway to transfer heat away from the  
IC to the PCB. It’s critical that the connection of the exposed pad to the PCB is properly constructed to maintain the desired IC case temperature  
(TCB). A good connection ensures that temperature at the exposed pad (TCB) and the board temperature (TB) are relatively the same. An  
improper connection can lead to increased junction temperature, increased power consumption and decreased electrical performance. In  
addition, there could be long-term reliability issues and increased failure rate.  
Example Calculation for Junction Temperature (TJ): TJ = TCB + JB x Pd  
Package type:  
Body size:  
48-Lead VFQFN  
7mm x 7mm x0.8mm  
5.65mm x 5.65mm  
4 x 4 matrix  
ePad size:  
Thermal Via:  
JB  
TCB  
Pd  
1.0oC/W  
105oC  
1.097W  
For the variables above, the junction temperature is equal to 106.1oC. Since this is below the maximum junction temperature of 125oC, there  
are no long term reliability concerns. In addition, since the junction temperature at which the device was characterized using forced convection  
is 118.5oC, this device can function without the degradation of the specified AC or DC parameters.  
©2016 Integrated Device Technology, Inc.  
18  
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Reliability Information  
Table 6. vs. Air Flow Table for a 48 Lead VFQFN  
JA  
JA at 0 Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
30.5°C/W  
26.7°C/W  
23.9°C/W  
Transistor Count  
The transistor count for the 8SLVP2108 is: 7706  
©2016 Integrated Device Technology, Inc.  
19  
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
48-Lead VFQFN Package Outline and Package Dimensions  
©2016 Integrated Device Technology, Inc.  
20  
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Ordering Information  
Table 7. Ordering Information  
Part/Order Number  
8SLVP2108ANLGI  
8SLVP2108ANLGI8  
Marking  
Package  
Shipping Packaging  
Temperature  
IDT8SLVP2108ANLGI “Lead-Free” 48-Lead VFQFN  
Tray  
-40C to 85C  
IDT8SLVP2108ANLGI “Lead-Free” 48-Lead VFQFN Tape & Reel, Pin 1 Orientation: EIA-481-C -40C to 85C  
8SLVP2108ANLGI/W IDT8SLVP2108ANLGI “Lead-Free” 48-Lead VFQFN Tape & Reel, Pin 1 Orientation: EIA-481-D -40C to 85C  
Table 8. Pin 1 Orientation in Tape and Reel Packaging  
Part Number Suffix  
Pin 1 Orientation  
Illustration  
CARRIER TAPE TOPSIDE  
(Round Sprocket Holes)  
Correct Pin 1 ORIENTATION  
8
Quadrant 1 (EIA-481-C)  
USER DIRECTION OF FEED  
Correct Pin 1 ORIENTATION  
CARRIER TAPE TOPSIDE  
(Round Sprocket Holes)  
/W  
Quadrant 2 (EIA-481-D)  
USER DIRECTION OF FEED  
©2016 Integrated Device Technology, Inc.  
21  
Revision B, November 21, 2016  
8SLVP2108 Datasheet  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Date  
T7, T8  
20  
Ordering Information Table - added additional row.  
Added Orientation Packaging Table.  
A
8/02/2012  
1
5
10  
Features section - added Differential PCLK bullets.  
AC Characteristics Notes, added NOTE 7.  
Updated application note, Wiring the Differential Inputs to Accept Single-ended Levels.  
A
A
10/12/2012  
T4A  
Changed NOTE 8 to read: VIL should not be less than -0.3V. VIH should not be higher  
1/28/2014  
5/20/14  
T4A  
T4A  
5
5
than VCC  
.
VPP, Test Conditions; fixed symbol formating.  
VO(PP), Test Conditions; fixed symbol formating.  
VDIFF_OUT, Test Conditions; fixed symbol formating.  
Ordering Info; fixed formating.  
A
B
T7  
20  
22  
Updated Contact Info page.  
Features Section - added case temperature bullet.  
Added Case Temperature Considerations.  
Deleted “IDT” prefix and “I” suffix from the part number.  
Updated datasheet header/footer.  
1
18  
11/21/16  
Corporate Headquarters  
Sales  
Tech Support  
www.IDT.com/go/support  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance spec-  
ifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information  
contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied  
warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of  
IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-  
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property  
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.  
©2016 Integrated Device Technology, Inc.  
22  
Revision B, November 21, 2016  
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