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CYIS1SM1000AA-HWC

型号：

CYIS1SM1000AA-HWC

品牌：

CYPRESS[ CYPRESS ]

页数：

20 页

PDF大小：

1064 K

下载PDF手册
STAR1000  
1M Pixel Radiation Hard CMOS Image  
Sensor  
operation modes such as (multiple) windowing, subsampling,  
etc.  
Features  
The STAR1000 sensor has the following characteristics:  
Three versions of sensors are available: STAR1000,  
STAR1000BK7, and STAR1000SP. The STAR1000 has a quartz  
glass lid, and the cavity between the die and the glass lid is filled  
with air. The STAR1000BK7 has a BK7G18 glass lid, and the  
cavity is filled with N2 which increases the temperature operating  
range. The STAR1000SP is similar to the STAR1000BK7, it has  
a BK7G18 glass lid, and a N2 filled cavity, but is also screened  
and tested to space qualified device standards.  
■
■
■
■
■
■
■
■
■
■
■
Integrating 3-transistor Active Pixel Sensor.  
1024 by 1024 pixels on 15 mm pitch.  
Radiation tolerant design.  
On-chip double sampling circuit to cancel Fixed Pattern Noise.  
Electronic shutter.  
Read out rate: up to 11 full frames per second.  
Region of Interest (ROI) windowing.  
On-chip 10-bit ADC.  
Programmable gain amplifier.  
Ceramic JLCC-84 package.  
Available with BK7G18 glass and with N2 filled cavity  
Sensor Description  
The STAR1000 is a CMOS image sensor with 1024 by 1024  
pixels on a 15 mm pitch. It features on-chip Fixed Pattern Noise  
(FPN) correction, a programmable gain amplifier, and a 10-bit  
Analog-to-Digital Converter (ADC).  
All circuits are designed using the radiation tolerant design rules  
for CMOS image sensors, to allow a high tolerance against total  
dose effects.  
Registers that are directly accessed by the external controller  
contain the X- and Y- addresses of the pixels to be read. This  
architecture provides flexible operation and allows different  
Ordering Information  
Marketing Part Number  
Description  
Package  
84 pin JLCC  
Demo Kit  
CYIS1SM1000AA-HHC  
CYIS1SM1000AA-HHCS  
CYIS1SM1000AA-HQC  
CYIS1SM1000AA-HWC  
CYIS1SM1000-EVAL  
Mono with BK7G18 Glass  
Mono with BK7G18 Glass, Space Qualified  
Mono with Quartz fused Silica Glass  
Mono without Glass  
Mono Demo Kit  
Cypress Semiconductor Corporation  
Document Number: 38-05714 Rev. *D  
•
198 Champion Court  
•
San Jose  
,
CA 95134-1709  
•
408-943-2600  
Revised September 18, 2009  
[+] Feedback  
STAR1000  
Image Sensor Specifications  
General Specifications  
Table 1. General Specifications of the STAR1000 Sensor  
Parameter  
Detector technology  
Pixel structure  
Photodiode  
Specification  
CMOS active pixel sensor  
3-transistor active pixel  
High fill factor photodiode  
1024 x 1024 pixels  
Comment  
Radiation-tolerant pixel design.  
Using N-well technique.  
Sensitive area format  
Pixel size  
15 x15 μm2  
Pixel output rate  
Windowing  
12 MHz  
Speed can be altered for power consumption.  
X- and Y- addressing random programmable  
Electronic shutter  
Electronic rolling shutter.  
Range - 1:1024  
Integration time is variable in time steps equal to the  
row readout time.  
Total dose radiation  
tolerance  
> 250 Krad (Si)  
Pixel test structures with a similar design have  
shown total dose tolerance up to several Mrad.  
Note: Dark current and DSNU are dependent of  
radiation dose.  
Proton radiation tolerance 2,4.1011 proton/cm2  
At 60 MeV  
SEU tolerance  
> 127,8 MeV cm3 mg-1  
Electro-optical Specifications  
Table 2. Electro-optical Specifications of the STAR1000 Sensor  
Value  
Parameter  
Comment  
Typical Value  
400-1000  
20%  
Unit  
Spectral range  
nm  
Quantum efficiency x fill  
factor  
Average over the visual range. See spectral  
response curve.  
Full well capacity  
135.000  
99.000  
e-  
e-  
Saturation capacity to  
meet non-linearity within  
+ 5%  
Output signal swing  
Conversion gain  
kTC noise  
1.1  
11.4  
47  
V
μV/e-  
e-  
Dynamic range  
Fixed pattern noise  
69  
dB  
Local: 1σ < 0.30%  
Global: 1σ <0.56%  
of full well  
Photo response  
non-uniformity at Sat/  
2 (RMS)  
Local: 1σ < 0.67%  
Global: σ <3.93%  
of full well  
Document Number: 38-05714 Rev. *D  
Page 2 of 20  
[+] Feedback  
STAR1000  
Table 2. Electro-optical Specifications of the STAR1000 Sensor (continued)  
Value  
Parameter  
Comment  
Typical Value  
Unit  
Average dark current at  
293K  
223  
ρA/cm2  
Dark current signal  
DSNU signal  
3135  
e-/s  
Dark current rises 425 e-/s per Krad.  
DSNU rises 14 e-/s per Krad.  
1.055% of Vsat  
Optical cross-talk  
at 600 nm  
Vertical: 16%  
Horizontal: 17.5%  
Anti-blooming capacity  
Output amplifier gain  
x 1000  
x1, x2.47, x4.59 and x8.64  
9.5  
Controlled by 2 bits.  
Analogue input  
bandwidth  
MHz  
V
Analogue input signal  
range  
0.1 to 4.9  
10  
Analog-to-Digital  
converter  
bit  
Radiation-tolerant version of the ADC on Ibis4 and  
other image sensors.  
ADC Differential  
Non-Linearity (DNL)  
<= ±3.5  
<= ±5.8  
5
LSB  
LSB  
ADC Integral  
Non-Linearity (INL)  
Integral non-linearity of ADC is better than linearity  
of image sensor.  
Supply voltage  
V
Digital input signals are 3.3V compatible.  
Power dissipation  
<350  
<100  
mW  
With internal ADC powered.  
Without internal ADC powered.  
Both values measured at nominal speed (12 MHz).  
Document Number: 38-05714 Rev. *D  
Page 3 of 20  
[+] Feedback  
STAR1000  
Spectral Response  
Figure 1. Spectral Response Curve  
0.16  
0.14  
0.12  
0.1  
QE 0.3  
QE 0.2  
0.08  
0.06  
0.04  
0.02  
0
QE 0.1  
QE0.05  
QE 0.01  
400  
500  
600  
700  
800  
900  
1000  
Wavelenght [nm]  
Photo-Voltaic Response  
Figure 2. Photo Voltaic Response Curve  
1,2  
1
0,8  
0,6  
0,4  
0,2  
0
0
20000  
40000  
60000  
80000 100000 120000 140000 160000 180000  
Number of electrons  
Document Number: 38-05714 Rev. *D  
Page 4 of 20  
[+] Feedback  
STAR1000  
Absolute Maximum Ratings  
Table 3. Absolute Maximum Ratings STAR1000  
Limits  
Characteristics  
Min  
Units  
Remarks  
Max  
+7  
Any supply voltage  
-0.5  
-0.5  
0
V
V
R
Voltage on any input terminal  
Operating temperature  
Vdd + 0.5  
+60  
°C  
Temperature range confirmed by  
evaluation testing.  
Storage temperature  
-10  
NA  
+60  
125  
°C  
°C  
Not longer than 1 hour. Temperature range  
confirmed by evaluation testing.  
Sensor soldering temperature  
Hand soldering only. The sensor’s  
temperature may not rise above this limit.  
Read the Soldering and Handling  
Conditions on page 18 for more  
information.  
Table 4. Absolute Maximum Ratings STAR1000BK7 and STAR1000SP  
Limits  
Characteristics  
Units  
Remarks  
Min  
-0.5  
-0.5  
-40  
Max  
+7  
Any supply voltage  
V
V
Voltage on any input terminal  
Operating temperature  
Vdd + 0.5  
+85  
°C  
Temperature range confirmed by  
evaluation testing.  
Storage temperature  
-40  
+85  
°C  
°C  
Temperature range confirmed by  
evaluation testing.  
-40  
NA  
+120  
125  
Maximum 1 hour.  
Sensor soldering  
temperature  
Hand soldering only. The sensor’s  
temperature may not rise above this limit.  
Read the Soldering and Handling  
Conditions on page 18 for more  
information.  
Table 5. DC Operating Conditions  
Symbol  
Limits  
Parameter  
Units  
Min  
Typ  
5
Max  
VDDA  
Analog supply of the image core.  
Digital supply of the image core.  
Analog supply of the ADC circuitry.  
Digital supply of the ADC circuitry.  
Power supply of ADC digital output stage.  
Reset level for RESET signal.  
V
V
V
V
V
V
V
VDDD  
5
VDD_ADC_ANA  
VDD_ADC_DIG  
VDD_DIG_OUT  
VRES  
5
5
5
5
VREF  
Reset level for RESET_DS signal.  
4
5
Document Number: 38-05714 Rev. *D  
Page 5 of 20  
[+] Feedback  
STAR1000  
Table 5. DC Operating Conditions (continued)  
Limits  
Symbol  
GNDA  
Parameter  
Units  
Min  
Typ  
0
Max  
Analog ground of the image core.  
Digital ground of the image core.  
Analog ground of the ADC circuitry.  
Digital ground of the ADC circuitry.  
Logical '1' input voltage.  
V
V
V
V
V
V
V
V
GNDD  
0
GND_ADC_ANA  
0
GND_ADC_DIG  
0
VIH  
VIL  
1.8  
0
VDDD  
Logical '0' input voltage.  
1
VDDD  
1
VOH  
VOL  
Logical '1' output voltage.  
4.25  
Logical '0' output voltage.  
Document Number: 38-05714 Rev. *D  
Page 6 of 20  
[+] Feedback  
STAR1000  
Architecture  
Floor Plan  
Figure 3. STAR1000 Floor Plan  
10  
1024  
1024  
Reset  
Pixel Array  
1024 x 1024 pixels  
Reset_DS  
Vref  
D0...D9  
Rst  
Rd  
Ld_Y  
Y Address  
Decoder  
and Logic  
Col  
10-bit ADC  
Rst  
Rd  
10  
Clk_ADC  
Ain  
A0....A9  
1024  
10  
S
R
Column Amplifiers  
1024  
Rst  
Sig  
1024  
Progr. Gain  
Amplifier  
1024  
1024  
Buffer  
Aout  
X Register  
Clk_X  
10  
X Address Decoder  
Ld_X  
The image sensor contains five sections: the pixel array, the X-  
and Y- addressing logic, the column amplifiers, the output  
amplifier and the ADC. Figure 3 shows an outline diagram of the  
sensor, including an indication of the main control signals. The  
following paragraphs explain the function and operation of the  
different imager parts in detail.  
The reset lines and the read lines of the pixels in a row are  
connected together to the Y- decoder logic; the outputs of the  
pixels in a column are connected together to a column amplifier.  
Figure 4. Architecture of the 3T Pixel  
T1  
Pixel Array  
Read  
The pixel array contains 1024 by 1024 active pixels at 15 μm  
pitch. Each pixel contains one photo diode and three transistors  
(Figure 4).  
Reset  
T2  
The photo diode is always in reverse bias. At the beginning of  
the integration cycle, a pulse is applied to the reset line (gate of  
T1) bringing the cathode of D1 to the reset voltage level. During  
the integration period, photon-generated electrons accumulate  
on the diode capacitance reducing the voltage on the gate of T2.  
The real illumination dependent signal is the difference between  
the reset level and the output level after integration. This  
difference is created in the column amplifiers. T2 acts as a  
source follower and T3 allows connection of the pixel signal  
(reset level and output level) to the vertical output bus.  
T3  
Document Number: 38-05714 Rev. *D  
Page 7 of 20  
[+] Feedback  
 
 
STAR1000  
amplifier is AC coupled, it also contains a provision to maintain  
and restore the proper DC level.  
Addressing Logic  
The addressing logic allows direct addressing of rows and  
columns. Instead of the one-hot shift registers that are often  
used, address decoders are implemented. One can select a line  
by presenting the required address to the address input of the  
device and latching it to the Y- decoder logic. Presenting the  
X- address to the device address input and latching it to the  
X- address decoder can select a column.  
An analog signal multiplexing feeds the pixel signal to the final  
unity gain buffer, providing the required drive capability. Apart  
from the pixel signal, three other external analog signals can be  
fed to the output buffer. All these signals can be digitalised by the  
on-chip ADC if the output of this buffer is externally connected to  
the input of the ADC.  
The purpose of the additional analog inputs (A_IN1, A_IN2, and  
A_IN3) is to allow the possibility of processing other analog  
signals through the image sensors signal path. These signals  
can then be converted by the ADC and processed by the image  
controller FPGA. The additional analog inputs are intended for  
low frequency or DC signals and have a reduced bandwidth  
compared with the image signal path.  
A typical line read out sequence first selects a line by applying  
the Y-address to the Y-decoder. Activation of the LD_Y input on  
the Y-logic connects the pixel outputs of the selected line to the  
column amplifiers. The individual column amplifier outputs are  
connected to the output amplifier by applying the respective  
X- addresses to the X- address decoder. Applying the appro-  
priate Y- address to the Y- decoder and activating the “Reset”  
input reset a line. The integration time of a row is the time  
between the last reset of this row and the time when it is selected  
for read out.  
ADC  
The image sensor has a 10-bit ADC that is electrically separated  
from the rest of the image sensor circuits and can be powered  
down if an external ADC is used. The conversion takes place at  
the falling edge of the clock and the output pins can be disabled  
to allow operation of the device in a bus structure.  
The Y- decoder logic has two different reset inputs: RESET and  
RESET_DS. Activation of RESET resets the pixel to the Vdd  
level; activation of RESET_DS resets the pixel to the voltage  
level on the VREF input. This feature allows the application of  
the so called dual slope integration. If dual slope integration is  
not needed, VREF is tied to Vdd and RESET_DS must never be  
activated.  
Timing and Control Signals  
The pixels addressing is done by direct addressing of rows and  
columns. This approach has the advantage of full flexibility when  
accessing the pixel array: multiple windowing and subsampled  
read out are possible by proper programming.  
Column Amplifiers  
All outputs from the pixels in a column are connected in parallel  
to a column amplifier. This amplifier samples the output voltage  
and the reset level of the pixel whose row is selected at that  
moment and presents these voltage levels to the output  
amplifier. As a result, the pixels are always reset immediately  
after read out as part of the sample procedure. Note that the  
maximum integration time of a pixel is the time between two read  
cycles.  
The following paragraphs clarify the timing for row and column  
readout.  
Row Selection and Reset Timing  
Figure 5 on page 9 shows the timing of the line sequence control  
signals. The timing constraints are presented in Table 6 on page  
9
Output Amplifier and Analog Multiplexer  
The address, presented at the address IO pins (A0…A9) is  
latched in with the LD-Y pulse (active low). After latching, the  
external controller already produces a new address.  
The output amplifier combines subtraction of pixel signal level  
from reset level with a programmable gain amplifier. Since the  
Document Number: 38-05714 Rev. *D  
Page 8 of 20  
[+] Feedback  
STAR1000  
Figure 5. Line Selection and Reset Sequence  
A0......A9  
LD_Y  
Read Address  
Reset Address  
k
m
k
m
l
l
INTERNAL  
Row Selected for Reset  
Row Selected for Readout  
a
b
S
c
d
g
f
d
RESET  
e
b
R
h
i
CAL  
(Once each  
frame)  
ROW  
READOUT  
Idle  
Time Available for Readout of Row Y-1  
Time Available for X-readout of Row Y  
Latching in a Y- address selects the addressed row and connects  
the pixel outputs of that row to the column amplifiers. Through  
the sequence of the S and R pulse and the reset pulse in  
between the pixel output signal and reset level are sampled and  
produced at the output of the column amplifier (to do the FPN  
double sampling correction).  
At this time horizontal read out of the selected row is started and  
another row is reset to effectuate reduced integration time  
(electronic rolling shutter).  
Table 6. Timing Constraints of Line Sequence  
Symbol  
Min  
Typ  
Description  
a
3.6 μs  
Delay between selection of a new row and falling edge on S.  
Minimal value: For maximum, speed a new row can already be selected  
during X- read out of the previous row.  
b
c
d
0.4 μs  
0
Duration of S and R pulse.  
100 ns  
Delay between falling edge of S and rising edge of reset.  
Minimum duration of reset pulse.  
200 ns  
Document Number: 38-05714 Rev. *D  
Page 9 of 20  
[+] Feedback  
STAR1000  
Table 6. Timing Constraints of Line Sequence  
Symbol  
Min  
1.6 μs  
0
Typ  
Description  
e
f
Delay between falling edge of reset and falling edge of R.  
100 ns  
g
Minimum delay between falling edge on LD_Y and rising edge of reset.  
Minimum required extension of Y- address after falling edge of reset pulse.  
g
h
100 ns  
200 ns  
Position of cal pulse after rising edge of S.  
The cal pulse must only be given once per frame.  
i
k
l
100 ns  
10 ns  
20 ns  
10 ns  
1 μs  
Duration of cal pulse.  
Address set up time.  
Load register value.  
Address stable after load.  
m
Pixel Read Out Timing  
Figure 6 on page 11 shows the timing of the pixel readout  
sequence. The external digital controller presents a column  
address that is latched by the rising edge of the LD_X pulse. After  
decoding the X- address the column selection is clocked in the  
X- register by CLK-X. The output amplifier uses the same pulse  
to subtract the pixel output level from the pixel reset level and the  
signal level. This causes a pipeline effect such that the analog  
output of the first pixel is effectively present at the device output  
terminal at the third rising edge of the X-CLK signal.  
The ADC conversion starts at the falling edge of the CLK-ADC  
signal and produces a valid digital output 20 ns after this edge.  
The timing constraints are given in Table 7 on page 11  
Important note: The values of the X shift-register tend to leak  
away after a while. Therefore, it is very important to keep the  
CLK_X signal asserted for as long as the sensor is powered up.  
If the sensor sits idle and CLK_X is not asserted, the leakage of  
the X shift-register causeq multiple columns to be selected at  
once. This forces high current through the sensor and may cause  
damage.  
Document Number: 38-05714 Rev. *D  
Page 10 of 20  
[+] Feedback  
STAR1000  
Figure 6. Column Selection and Read Out Sequence  
Row Idle Time  
A0......A9  
X1  
X2  
X3  
X5  
X8  
X4  
X6  
X7  
LD_X  
a
b
CLK_X  
X6  
X2  
X4  
X1  
X3  
X5  
Undefined Output Level  
ANALOG  
OUTPUT  
CLK_ADC  
D9......D0  
c
X1  
X3  
X4  
X2  
Table 7. Timing Constraints of Column Read Out  
Symbol  
Min  
20 ns  
40 ns  
0
Typ  
Description  
a
b
c
Address setup time.  
Address valid time.  
20 ns  
ADC output valid after falling edge of CLK_ADC.  
Document Number: 38-05714 Rev. *D  
Page 11 of 20  
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STAR1000  
Pin List  
Figure 7 displays the pin connections of the STAR1000. The tables that follow group the connections by their functionality.  
Figure 7. STAR1000 Pin Connections  
Table 8. Pin List of the STAR1000 Sensor  
Pin  
1
Pin Name  
A3  
Pin Type  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Pin Description  
2
A4  
3
A5  
4
A6  
5
A7  
6
A8  
7
A9  
8
LD_Y  
Digital Input. Latch address (A0…A9) to Y-register (0 = track, 1 = hold).  
Document Number: 38-05714 Rev. *D  
Page 12 of 20  
[+] Feedback  
 
STAR1000  
Table 8. Pin List of the STAR1000 Sensor (continued)  
Pin  
9
Pin Name  
LD_X  
Pin Type  
Input  
Pin Description  
Digital input. Latch address (A0…A9) to X-register (0 = track, 1 = hold).  
Analog power supply of the imager (typical 5V).  
Digital ground of the imager.  
10  
11  
12  
13  
14  
VDDA  
Supply  
Ground  
Ground  
Input  
GNDD  
GNDA  
Analog ground of the imager.  
CLK_X  
Digital input. Clock X-register (output valid & stable when CLK_X is high).  
RESET_DS  
Input  
Digital input (active high). Resets row indicated by Y-address (see sensor  
timing diagram).  
RESET_DS is used for dual-slope integration (see FAQ).  
GND is used for normal operation.  
15  
16  
VDDD  
Supply  
Input  
Digital supply of the image sensor.  
RESET  
Digital input (active high). Resets row indicated by Y-address (see sensor  
timing diagram).  
17  
18  
19  
S
R
Input  
Input  
Input  
Digital input (active high). Control signal for column amplifier (see sensor  
timing diagram).  
Digital input (active high). Control signal for column amplifier (see sensor  
timing diagram).  
NBIAS_DEC  
Analog input. Biasing of address decoder.  
Connect with 100 kΩ to VDDA and decouple with 100nF to GND.  
20  
21  
22  
23  
24  
25  
A_IN2  
A_IN3  
Input  
Input  
Input  
Input  
Input  
Input  
Additional analog inputs. For proper conversion with on-chip ADC, the  
input signal must lie within the output signal range of the image sensor  
(approximately +2V to +4V).  
A_IN1  
A_SEL1  
A_SEL0  
NBIAS_OAMP  
Selection of analog channel: '00' selects image sensor ('01' selects A_IN1,  
'10' A_IN2, and '11' A_IN3).  
Analog input. Bias of output amplifier (speed/power control).  
Connect with 100 kΩ to VDDA and decouple with 100 nF to GND for 12.5  
MHz output rate (lower resistor values yield higher maximal pixel rates at  
the cost of extra power dissipation).  
26  
PBIAS  
Input  
Analog input. Biasing of the multiplexer circuitry.  
Connect with 20 kΩ to GND and decouple with 100 nF to VDD.  
27  
28  
29  
G1  
G0  
Input  
Input  
Input  
Digital input. Select output amplifier gain value: G0 = LSB, G1 = MSB ('00'  
= unity gain, '01' = x2, '10' = x4, '11' = x8).  
CAL  
Digital input (active high). Initialization of output amplifier. Output amplifier  
outputs BLACKREF in unity gain mode when CAL is high (1).  
Apply pulse pattern (see sensor timing diagram).  
30  
31  
OUT  
Output  
Input  
Analog Output Video Signal. Connected to the analog input of the internal  
(pin 52) 10-bit ADC or an external ADC.  
BLACKREF  
Analog input. Control voltage for output signal offset level. Buffered  
on-chip, the reference level can be generated by a 100 kΩ resistive divider.  
Connect to 2V DC for use with on-chip ADC.  
32  
33  
VDDA  
VDDD  
Supply  
Supply  
Analog power supply of image core (typical 5V).  
Digital power supply of image core (typical 5V).  
Document Number: 38-05714 Rev. *D  
Page 13 of 20  
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STAR1000  
Table 8. Pin List of the STAR1000 Sensor (continued)  
Pin  
34  
35  
36  
Pin Name  
GNDA  
Pin Type  
Ground  
Ground  
Input  
Pin Description  
Analog ground of image core.  
Digital ground of image core.  
GNDD  
NBIAS_ARRAY  
Analog input. Biasing of the pixel array. Connect with 1MΩ to VDDA and  
decouple with 100 nF capacitor to GND.  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
TESTPIXARRAY  
Output  
Output  
Analog output of an array of 20 x 35 test pixels where all photodiodes are  
connected in parallel. Is used for electro-optical evaluation.  
49  
PHOTODIODE  
Plain Photo Diode (without circuitry). Area of the photodiode = 20 x 35  
pixels. Is used for electro-optical evaluation.  
50  
51  
52  
NBIAS_ANA  
NBIAS_ANA2  
IN_ADC  
Input  
Input  
Input  
Analog input. Analog biasing of the ADC circuitry. Connect with 100 kΩ to  
VDDA and decouple with 100 nF to GND.  
Analog input of the internal ADC. Connect to analog output of image  
sensor (pin 30).  
Input range (typically 2V and 4V) of the internal ADC is set between by  
VLOW_ADC (pin 55) and VHIGH_ADC (pin 62).  
53  
54  
55  
VDD_ADC_ANA  
GND_ADC_ANA  
VLOW_ADC  
Supply  
Ground  
Input  
Analog power supply of the ADC (typical 5V).  
Analog ground of the ADC.  
Low reference voltage of internal ADC. Nominal input range of the ADC  
is between 2V and 4V. The resistance between VLOW_ADC and  
VHIGH_ADC is approximately 1.5 kΩ. Connect with 1.5 kΩ to GND and  
decouple with 100 nF to GND.  
56  
57  
58  
n.c.  
PBIASDIG2  
BITINVERT  
Input  
Input  
Connect with 20 kΩ to GND and decouple with 100nF to VDDA.  
Digital input. Inversion of the ADC output bits. 0 = invert output bits (0 =>  
black, 1023; white, 0), 1 = no inversion of output bits (black, 0; white, 1023).  
59  
TRI_ADC  
Input  
Digital input. Tri-state control of digital ADC outputs (1 = tri-state, 0 =  
normal mode).  
60  
61  
D0  
Input  
Input  
ADC output bits.#D0 = LSB, D9=MSB.  
CLK  
Digital input. ADC clock. ADC converts on falling edge.  
Document Number: 38-05714 Rev. *D  
Page 14 of 20  
[+] Feedback  
STAR1000  
Table 8. Pin List of the STAR1000 Sensor (continued)  
Pin  
Pin Name  
Pin Type  
Pin Description  
62  
VHIGH_ADC  
Input  
High reference voltage of internal ADC. Nominal input range of the ADC  
is between 2V and 4V. The resistance between VLOW_ADC and  
VHIGH_ADC is about 1.5 kΩ.  
Connect with 1.1 kΩ to VDDA and decouple with 100 nF to GND.  
63  
64  
65  
66  
67  
GND_ADC_ANA  
VDD_ADC_ANA  
VDD_ADC_DIG  
GND_ADC_DIG  
VDD_DIG_OUT  
Ground  
Supply  
Supply  
Output  
Supply  
Analog ground of the ADC circuitry.  
Analog supply of the ADC circuitry (typical 5V).  
Digital supply of the ADC circuitry (typical 5V).  
Digital ground of the ADC circuitry.  
Power supply of ADC digital output. Connect to 5V for normal operation.  
Can be brought to lower voltage when image sensor must be interfaced  
to low voltage periphery.  
68  
69  
70  
71  
72  
73  
74  
75  
D1  
D2  
Output  
Output  
Output  
Output  
Output  
Supply  
Ground  
Supply  
ADC output bits. #D0 = LSB, D9 = MSB.  
D3  
D4  
D5  
VDDA  
GNDA  
GND_AB  
Analog supply of the image core (typical 5V).  
Analog ground of the image core (typical 5V).  
Anti-blooming drain control voltage. Default: connect to ground where the  
anti-blooming is operational but not maximal. Apply 1V DC for improved  
anti-blooming.  
76  
VREF  
Supply  
Analog supply. Reset level for RESET_DS. Is used for extended optical  
dynamic range. See FAQ for more details.  
77  
78  
79  
80  
81  
82  
83  
84  
VRES  
D6  
Supply  
Output  
Output  
Output  
Output  
Input  
Analog supply. Reset level for RESET (typical 5V).  
ADC output bits. #D0 = LSB, D9 = MSB.  
D7  
D8  
D9  
A0  
Digital input. Address inputs for row and column addressing. A9 = LSB,  
A0 = MSB.  
A1  
Input  
A2  
Input  
Document Number: 38-05714 Rev. *D  
Page 15 of 20  
[+] Feedback  
STAR1000  
Packaging and Geometrical Constraints  
Package Drawing  
The detector is packaged in an 84-pin J-leaded package.  
The detector is positioned into the cavity such that the optical  
center of the detector coincides with the geometrical center of  
the cavity within a tolerance of ± 50 μm in X- and Y direction. The  
tolerance on the parallelism of the detector is ± 50 μm in X- and  
Y- direction.  
The detector is mounted into position with thermally and electri-  
cally conductive adhesive. The bottom plate of the cavity is  
electrically connected to a ground pin.  
Note: The dimensions in Figure 8 are in inches.  
Figure 8. Package Drawing  
Document Number: 38-05714 Rev. *D  
Page 16 of 20  
[+] Feedback  
 
STAR1000  
Die Alignment  
Figure 9. Die Alignment  
Parallelism in  
X and Y within  
+ 50 mm  
200 P  
Y
Pin 1  
Centre of Cavity  
and of FPA  
X
Centre of  
Silicium  
Offset Between Centre of  
Silicium and Centre of  
Cavity:  
X: 52 Pm  
Y: 200 Pm  
A
A
52 P  
Die:  
0.508+0.01  
Bonding Cavity:  
0.508+0.051  
Glass Window:  
1.0+/-0.05  
Window Adhesive:  
0.08+0.02  
Die Cavity:  
0.508+0.051  
A -  
Die Adhesive:  
0.08+0.02  
Section A  
Drawing Not to Scale  
Glass Lids  
There are 2 glass lid versions available:  
■
■
STAR1000 - Quartz glass with air inside the cavity  
STAR1000BK7 and STAR1000SP - BK7G18 glass with N2  
inside the cavity  
Document Number: 38-05714 Rev. *D  
Page 17 of 20  
[+] Feedback  
STAR1000  
Soldering and Handling  
Use a soldering iron with temperature control at the tip. The  
soldering iron tip temperature should not exceed 350°C.  
Soldering and Handling Conditions  
Take special care when soldering image sensors onto a circuit  
board. Prolonged heating at elevated temperatures may result in  
deterioration of the performance of the sensor. The following  
recommendations are made to ensure that sensor performance  
is not compromised during end users' assembly processes.  
The soldering period for each pin should be less than five  
seconds.  
Reflow Soldering  
Reflow soldering is not allowed.  
Board Assembly  
Precautions and Cleaning  
The STAR1000 is very sensitive to ESD. Device placement onto  
boards should be done in accordance with strict ESD controls for  
Class 0, JESD22 Human Body Model, and Class A, JESD22  
Machine Model devices. Assembly operators need to always  
wear all designated and approved grounding equipment;  
grounded wrist straps at ESD protected workstations are recom-  
mended including the use of ionized blowers. All tools should be  
ESD protected.  
Avoid spilling solder flux on the cover glass; bare glass and  
particularly glass with antireflection filters may be harmed by the  
flux. Avoid mechanical or particulate damage to the cover glass.  
Use isopropyl alcohol (IPA) as a solvent for cleaning the image  
sensor glass lid. When using other solvents, confirm whether the  
solvent does not damage the package and/or glass lid.  
RoHS (lead free) Compliance  
Manual Soldering  
This paragraph reports the use of Hazardous chemical  
substances as required by the RoHS Directive (excluding  
packing material).  
When a soldering iron is used the following conditions should be  
observed:  
Table 9. Chemical Substances in STAR250 Sensor  
If there is any intentional content, in which portion is  
it contained?  
Chemical Substance  
Any intentional content  
Lead  
NO  
NO  
NO  
NO  
NO  
NO  
-
-
-
-
-
-
Cadmium  
Mercury  
Hexavalent chromium  
PBB (Polybrominated biphenyls)  
PBDE (Polybrominated diphenyl ethers)  
The following case is not treated as "intentional content":  
Information on Lead Free Soldering  
A case that the above material is contained as an impurity into  
raw materials or parts of the intended product. The impurity is  
defined as a substance that cannot be removed industrially, or it  
is produced at a process like chemical composing or reaction  
and it cannot be removed technically.  
The product cannot withstand a lead free soldering process.  
Reflow or wave soldering is not recommended. Hand soldering  
is needed for this part type. Solder 1 pin on each side and let the  
sensor cool down for minimum 1 minute before continuing.  
Note: "Intentional Content" is defined as any material  
demanding special attention that is contained into the inquired  
product by these cases:  
Disclaimer  
Cypress image sensors are only warranteed to meet the specifi-  
cations as described in the production data sheet.  
1. A case that the above material is added as a chemical compo-  
sitionintotheinquiredproductintentionallyinordertoproduce  
and maintain the required performance and function of the  
intended product  
Cypress reserves the right to change any information contained  
herein without notice.  
2. A case that the above material, which is used intentionally in  
the manufacturing process, is contained in or adhered to the  
inquired product.  
Contact your local sales agent for more information.  
Document Number: 38-05714 Rev. *D  
Page 18 of 20  
[+] Feedback  
STAR1000  
APPENDIX A: STAR1000 Evaluation System  
For evaluating purposes, a STAR1000 evaluation kit is available.  
images can be stored in different file formats (8 or 16-bit). All  
settings can be adjusted dynamically to evaluate the sensors  
specs. Default register values can be loaded to start the software  
in a desired state.  
The STAR1000 evaluation kit consists of a multifunctional digital  
board (memory, sequencer, and IEEE 1394 Fire Wire interface)  
and an analog image sensor board.  
All products and company names mentioned in this document  
may be the trademarks of their respective holders.  
Visual Basic software (under Windows 2000 or XP) allows the  
grabbing and display of images from the sensor. All acquired  
Document Number: 38-05714 Rev. *D  
Page 19 of 20  
[+] Feedback  
STAR1000  
Document History Page  
Document Title: STAR1000 - 1M Pixel Radiation Hard CMOS Image Sensor  
Document Number: 38-05714  
Orig. of Submission  
Revision  
ECN  
Description of Change  
Change  
Date  
**  
310213  
603177  
649371  
SIL  
See ECN Initial Cypress release  
*A  
*B  
*C  
*D  
QGS  
FPW  
See ECN Converted to Framemaker Format  
See ECN Package spec label update + ordering information update  
2738591 FOSTMP2 See ECN Bond diagram update + review  
2765859 NVEA 09/18/09 Updated Ordering Information table  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
psoc.cypress.com  
clocks.cypress.com  
wireless.cypress.com  
memory.cypress.com  
image.cypress.com  
Clocks & Buffers  
Wireless  
Memories  
Image Sensors  
© Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 38-05714 Rev. *D  
Revised September 18, 2009  
Page 20 of 20  
All products and company names mentioned in this document may be the trademarks of their respective holders.  
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