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CYLE1049DV33-12ZSE

型号：

CYLE1049DV33-12ZSE

品牌：

CYPRESS[ CYPRESS ]

页数：

16 页

PDF大小：

1065 K

下载PDF手册
CYRS1049DV33  
4-Mbit (512 K × 8) Static RAM  
with RadStop™ Technology  
4-Mbit (512  
K × 8) Static RAM with RadStop™ Technology  
Radiation Performance  
Features  
❥ Temperature ranges  
Radiation Data  
❥ Military/Space: –55 °C to 125 °C  
❥ Total dose 300 Krad  
❥ High speed  
❥ tAA = 12 ns  
❥ Soft  
error rate (both heavy ion and proton)  
Heavy ions 1 × 10-10 upsets/bit-day with single-error  
correction, double error detection error detection and  
correction (SEC-DED EDAC)  
❥ Low active power  
❥ ICC = 95 mA at 12 ns (PMAX = 315 mW)  
❥ Neutron = 2.0 × 1014 N/cm2  
❥ Low CMOS standby power  
❥ ISB2 = 15 mA  
❥ Dose rate > 2.0 × 109 (rad(Si)/s)  
❥ Latch up immunity LET = 120 MeV.cm2/mg (125 C)  
❥ 2.0 V data retention  
❥ Automatic power-down when deselected  
❥ Transistor-transistor logic (TTL) compatible inputs and outputs  
❥ Easy memory expansion with CE and OE features  
❥ Available in Pb-free 36-pin ceramic flat package  
Processing Flows  
❥ V grade - Class V flow in compliance with MIL-PRF 38535  
Prototyping Options  
❥ Non qualified manufacturers list (QML)  
V
grade  
CYPT1049DV33 devices with same functional and timing  
characteristics in a 36-pin ceramic flat package  
Logic Block Diagram  
I/O  
0
INPUT BUFFER  
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
I/O  
1  
I/O  
2  
I/O  
512K x 8  
ARRAY  
3
4
5
6
I/O  
I/O  
A
A
9
I/O  
10  
CE  
POWER  
DOWN  
I/O  
7
COLUMN DECODER  
WE  
OE  
Cypress Semiconductor Corporation  
Document Number: 001-64292 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised March 19, 2012  
CYRS1049DV33  
Contents  
Functional Description .....................................................3  
Selection Guide ................................................................3  
Pin Configuration .............................................................3  
Maximum Ratings .............................................................4  
Operating Range ...............................................................4  
DC Electrical Characteristics ..........................................4  
Capacitance ......................................................................5  
Thermal Resistance ..........................................................5  
AC Test Loads and Waveforms .......................................5  
AC Switching Characteristics .........................................6  
Data Retention Characteristics .......................................7  
Data Retention Waveform ................................................7  
Switching Waveforms ......................................................8  
Truth Table ......................................................................11  
Ordering Information ......................................................12  
Ordering Code Definitions .........................................12  
Package Diagram ............................................................13  
Acronyms ........................................................................14  
Document Conventions .................................................14  
Units of Measure .......................................................14  
Glossary ..........................................................................14  
Document History Page .................................................15  
Sales, Solutions, and Legal Information ......................16  
Worldwide Sales and Design Support .......................16  
Products ....................................................................16  
PSoC Solutions .........................................................16  
Document Number: 001-64292 Rev. *C  
Page 2 of 16  
CYRS1049DV33  
Under these conditions, the contents of the memory location  
specified by the address pins appear on the I/O pins. See the  
Truth Table on page 11 for a complete description of read and  
write modes.  
Functional Description  
The CYRS1049DV33 is a high-performance complementary  
metal oxide semiconductor (CMOS) static RAM organized as  
512 K words by 8 bits with RadStop™ technology. Cypress’s  
state-of-the-art RadStop technology is radiation hardened  
through proprietary design and process hardening techniques.  
The 4-Mbit fast asynchronous SRAM with RadStop technology  
is also QML V certified with Defense Logistics Agency Land and  
Maritime (DLAM).  
The eight input or output pins (I/O0 through I/O7) are placed in a  
high impedance state when the device is deselected (CE HIGH),  
the outputs are disabled (OE HIGH), or during a write operation  
(CE LOW, and WE LOW)  
The CYRS1049DV33 is available in  
a ceramic 36-pin  
Flatpackage with center power and ground (revolutionary)  
pinout.  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)  
is then written into the location specified on the address pins (A0  
through A18).  
Easy memory expansion is provided by utilizing OE, CE, and  
tri-state drivers.  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.  
Selection Guide  
Description  
Maximum access time  
Military/Space  
Unit  
ns  
12  
95  
15  
Maximum operating current  
mA  
mA  
Maximum CMOS standby current  
Pin Configuration  
Figure 1. 36-pin Ceramic Flat Package (Top View) [1]  
A
A
A
A
A
1
2
3
4
5
6
7
8
9
NC  
A
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
0
1
2
3
18  
A
17  
A
16  
A
15  
OE  
4
CE  
IO  
IO  
7
0
IO  
1
IO  
6
GND  
V
CC  
V
CC  
IO  
GND 10  
IO  
IO  
2
3
11  
12  
13  
14  
15  
16  
17  
18  
5
IO  
4
14  
A
WE  
A
A
13  
5
A
6
A
12  
A
A
11  
7
A
A
10  
DNU  
8
A
9
Note  
1. NC pins are not connected on the die.  
Document Number: 001-64292 Rev. *C  
Page 3 of 16  
CYRS1049DV33  
DC input voltage [2] ............................. –0.5 V to VCC + 0.5 V  
Current into outputs (LOW) ........................................ 20 mA  
Maximum Ratings  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Static discharge voltage  
(MIL-STD-883, Method 3015) .................................>2001 V  
Storage temperature ................................ –65 C to +150 C  
Latch up current .....................................................> 140 mA  
Ambient temperature with  
power applied .......................................... –55 C to +125 C  
Operating Range  
Supply voltage on  
VCC relative to GND [2] ................................–0.3 V to +4.6 V  
Ambient  
Temperature  
Range  
VCC  
Speed  
DC voltage applied to outputs  
in High Z state [2] ................................–0.5 V to VCC + 0.5 V  
Military/Space  
–55 C to +125 C 3.3 V 0.3 V 12 ns  
DC Electrical Characteristics  
Over the Operating Range  
Military/Space  
Parameter  
Description  
Output high voltage  
Test Conditions  
Unit  
Min  
2.4  
–
Max  
VOH  
VOL  
VCC = Min, IOH = –4.0 mA  
–
0.4  
V
V
Output low voltage  
VCC = Min, IOL = 8.0 mA  
[2]  
VIH  
VIL  
IIX  
Input high voltage  
2.0  
–0.3  
–1  
–1  
–
VCC + 0.3  
0.8  
V
[2]  
Input low voltage  
V
Input leakage current  
Output leakage current  
VCC operating supply current  
GND < VI < VCC  
+1  
A  
A  
mA  
mA  
mA  
mA  
IOZ  
ICC  
GND < VOUT < VCC, output disabled  
VCC = Max, f = fMAX = 1/tRC  
+1  
83 MHz  
66 MHz  
40 MHz  
95  
–
85  
–
75  
ISB1  
ISB2  
Automatic CE power-down  
current – TTL inputs  
Max VCC, CE > VIH  
–
15  
V
IN > VIH or VIN < VIL, f = fMAX  
Max VCC, CE > VCC – 0.3 V,  
IN > VCC – 0.3 V, or VIN < 0.3 V, f = 0  
Automatic CE power-down  
current – CMOS inputs  
–
15  
mA  
V
Note  
2.  
V
= –2.0 V and V  
= V + 2 V for pulse durations of less than 20 ns.  
IL(min)  
IH(max) CC  
Document Number: 001-64292 Rev. *C  
Page 4 of 16  
CYRS1049DV33  
Capacitance  
Parameter [3]  
Description  
Input capacitance  
I/O capacitance  
Test Conditions  
TA = 25 C, f = 1 MHz, VCC = 3.3 V  
Max  
8
Unit  
pF  
CIN  
COUT  
8
pF  
Thermal Resistance  
CeramicFlat  
Package  
Parameter [3]  
Description  
Test Conditions  
Unit  
JC  
Thermal resistance  
(junction to case)  
Test according to MIL-PRF 38538  
3.6  
C/W  
AC Test Loads and Waveforms  
Figure 2. AC Test Loads and Waveforms [4]  
All Input Pulses  
Z = 50  
3.0 V  
Output  
90%  
10%  
90%  
10%  
50   
1.5 V  
30 pF*  
GND  
* Capacitive load consists  
of all components of the  
test environment  
Fall Time: 1 V/ns  
Rise Time: 1 V/ns  
(a)  
(b)  
High-Z Characteristics  
R 317  
3.3 V  
OUTPUT  
5 pF  
R2  
351   
(c)  
Notes  
3. Tested initially and after any design or process changes that may affect these parameters.  
4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 2 (a). High Z characteristics are tested for all speeds using the test load shown  
in Figure 2 (c).  
Document Number: 001-64292 Rev. *C  
Page 5 of 16  
CYRS1049DV33  
AC Switching Characteristics  
Over the Operating Range  
Military/Space  
Unit  
Parameter [5]  
Description  
Min  
Max  
Read Cycle  
[6]  
tpower  
tRC  
VCC (typical) to the first access  
Read cycle time  
100  
12  
–
–
–
s  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to data valid  
12  
–
tOHA  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
Data hold from address change  
CE LOW to data valid  
OE LOW to data valid  
OE LOW to Low Z [7]  
OE HIGH to High Z [7, 8]  
CE LOW to Low Z [7]  
CE HIGH to High Z [7, 8]  
CE LOW to Power-up  
CE HIGH to Power-down  
3
–
12  
6
–
0
–
–
6
3
–
–
6
0
–
tPD  
–
12  
Write Cycle [9, 10]  
tWC  
Write cycle time  
12  
8
–
–
–
–
–
–
–
–
–
6
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCE  
tAW  
CE LOW to write end  
Address setup to write end  
Address hold from write end  
Address setup to write start  
WE pulse width  
8
tHA  
0
tSA  
0
tPWE  
tSD  
8
Data setup to write end  
Data hold from write end  
WE HIGH to Low Z [7]  
WE LOW to High Z [7, 8]  
6
tHD  
0
tLZWE  
tHZWE  
3
–
Notes  
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I /I  
OL OH  
and 30-pF load capacitance.  
t gives the minimum amount of time that the power supply should be at typical V values until the first memory access is performed.  
POWER  
6.  
CC  
7. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given  
LZWE  
HZCE  
LZCE HZOE  
LZOE HZBE  
LZBE  
HZWE  
device.  
8.  
t
, t  
, t  
and t  
are specified with a load capacitance of 5 pF as in part (c) of Figure 2 on page 5. Transition is measured when the outputs enter a high  
HZWE  
HZOE HZCE HZBE,  
impedance state.  
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write and the transition of either of  
these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.  
10. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of t  
and t  
.
SD  
HZWE  
Document Number: 001-64292 Rev. *C  
Page 6 of 16  
CYRS1049DV33  
Data Retention Characteristics  
Over the Operating Range  
Parameter  
VDR  
ICCDR  
Description  
VCC for data retention  
Data retention current  
Conditions [11]  
Min  
2.0  
–
Max  
–
Unit  
–
V
VCC = VDR = 2.0 V,  
15  
CE > VCC – 0.3 V,  
mA  
VIN > VCC – 0.3 V or VIN < 0.3 V  
Chip deselect to data retention  
time  
[12]  
tCDR  
–
–
0
–
–
ns  
ns  
[13]  
tR  
Operation recovery time  
12  
Data Retention Waveform  
Figure 3. Data Retention Waveform  
Data Retention Mode  
3.0 V  
3.0 V  
V
DR  
> 2 V  
VCC  
CE  
t
t
R
CDR  
Notes  
11. No input may exceed V + 0.3 V.  
CC  
12. Tested initially and after any design or process changes that may affect these parameters.  
13. Full device operation requires linear V ramp from V to V  
> 50 s or stable at V  
> 50 s.  
CC  
DR  
CC(min)  
CC(min)  
Document Number: 001-64292 Rev. *C  
Page 7 of 16  
CYRS1049DV33  
Switching Waveforms  
Figure 4. Read Cycle No. 1 [14, 15]  
t
RC  
Address  
t
AA  
t
OHA  
Data out  
Previous Data Valid  
Data Valid  
Figure 5. Read Cycle No. 2 (OE Controlled) [15, 16]  
Address  
CE  
t
RC  
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
High  
Impedance  
High Impedance  
Data OUT  
Data Valid  
t
LZCE  
t
PD  
ICC  
ISB  
t
PU  
VCC  
Supply  
Current  
50%  
50%  
Notes  
14. Device is continuously selected. OE, CE = V  
15. WE is HIGH for read cycle.  
.
IL  
16. Address valid prior to or coincident with CE transition LOW.  
Document Number: 001-64292 Rev. *C  
Page 8 of 16  
CYRS1049DV33  
Switching Waveforms(continued)  
Figure 6. Write Cycle No. 1 (CE Controlled) [17, 18]  
t
WC  
Address  
t
SCE  
CE  
t
SA  
t
SCE  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA I/O  
DataIN Valid  
Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [17, 18]  
t
WC  
Address  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
OE  
t
t
SD  
HD  
Data  
Valid  
Data I/O  
IN  
NOTE 19  
t
HZOE  
Notes  
17. Data I/O is high impedance if OE = V  
IH.  
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.  
19. During this period the I/Os are in the output state and input signals should not be applied.  
Document Number: 001-64292 Rev. *C  
Page 9 of 16  
CYRS1049DV33  
Switching Waveforms(continued)  
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)  
t
WC  
Address  
t
SCE  
CE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
NOTE 20  
Data I/O  
DataIN Valid  
t
t
LZWE  
HZWE  
Note  
20. During this period the I/Os are in the output state and input signals should not be applied.  
Document Number: 001-64292 Rev. *C  
Page 10 of 16  
CYRS1049DV33  
Truth Table  
I/O0–I/O7  
Mode  
Power-down  
Power  
CE  
OE  
WE  
H
X
X
High Z  
Data out  
Data in  
High Z  
Standby (ISB1or ISB2  
)
L
L
L
L
X
H
H
L
Read  
Write  
Active (ICC  
)
Active (ICC  
)
H
Selected, Outputs disabled Active (ICC)  
Document Number: 001-64292 Rev. *C  
Page 11 of 16  
CYRS1049DV33  
Ordering Information  
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local  
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at  
http://www.cypress.com/products  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office  
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
CYRS1049DV33-12CZSE  
CYPT1049DV33-12CZSE  
5962F1123501VXA  
Package Type  
12  
12  
12  
12  
12  
001-67583 36-pin ceramic flat package  
001-67583 36-pin ceramic flat package, Prototype part  
001-67583 36-pin ceramic flat package, DLAM part  
51-85087 44-pin plastic TSOP II  
Military/Space  
Military/Space  
Military/Space  
Military/Space  
Military/Space  
CYLE1049DV33-12ZSE  
CYLE1049DV33-12VE  
51-85090 36-pin plastic SOP  
Contact your local Cypress sales representative for availability of these parts  
Ordering Code Definitions  
CY RS 1 04 9 D V33 12 XXX X  
-
X
Temperature range: X = E or A  
E or A = Military/Space grade  
Pb-free  
Package type: XXX = CZS or V or ZS  
CZS = 36-pin Ceramic FP, V = 36-pin SOP, ZS = 44-pin TSOP II  
Speed: 12 = 12 ns  
V33 = Voltage range (3 V to 3.6 V)  
D= 90 nm Technology  
Data width: 9 = × 8 bits  
Density: 04 = 4-Mbit  
1 = Fast Asynchronous SRAM family  
RS = RadStop, PT = Prototype, LE = Low Earth Orbit  
CY = Cypress  
Document Number: 001-64292 Rev. *C  
Page 12 of 16  
CYRS1049DV33  
Package Diagram  
Figure 9. 36-pin Ceramic Flat Pack F36A/FZ36A (Solder Seal Lid) Package Outline, 001-67583  
001-67583 *A  
Document Number: 001-64292 Rev. *C  
Page 13 of 16  
CYRS1049DV33  
Acronyms  
Document Conventions  
Units of Measure  
Acronym  
Description  
CE  
chip enable  
Symbol  
°C  
Unit of Measure  
CMOS  
DLAM  
DNU  
EDAC  
I/O  
complementary metal oxide semiconductor  
defense logistics agency land and maritime  
do not use  
degree Celsius  
megahertz  
microampere  
microsecond  
milliampere  
nanosecond  
percent  
MHz  
µA  
µs  
mA  
ns  
error detection and correction  
input/output  
LET  
linear energy transfer  
OE  
output enable  
%
QML  
qualified manufacturers list  
pF  
V
picofarad  
volt  
SEC-DED single error correction – double error detection  
SEL  
single-event latch up  
static random access memory  
thin small outline package  
transistor-transistor logic  
write enable  
SRAM  
TSOP  
TTL  
W
watt  
WE  
Glossary  
Total Dose  
Heavy Ion  
LET  
Permanent device damage due to ions over device life  
Instantaneous device latch up due to single ion  
Linear energy transfer (measured in MeVcm2)  
Krad  
Unit of measurement to determine device life in radiation environments.  
Permanent device damage due to energetic neutrons or protons  
Neutron  
Prompt Dose  
Data loss of permanent device damage due to X-rays and gamma rays <20 ns  
RadStop Technology Cypress's patented Rad Hard design methodology  
QML V  
DLAM  
LSBU  
LMBU  
Space level certification from DSCC.  
Defense Logistics Agency Land and Maritime  
Logical Single Bit Upset. Single bits in a single correction word are in error.  
Logical Multi Bit Upset. Multiple bits in a single correction word are in error  
Document Number: 001-64292 Rev. *C  
Page 14 of 16  
CYRS1049DV33  
Document History Page  
Document Title: CYRS1049DV33, 4-Mbit (512 K × 8) Static RAM with RadStop™ Technology  
Document Number: 001-64292  
Origin of Submission  
Rev.  
ECN No.  
Description of Change  
Change  
Date  
**  
3098986  
3181475  
HRP  
12/01/2010 New data sheet.  
*A  
PRAS  
02/24/2011 Updated Package Diagram (Replaced 44-pin TSOP II package with 36-pin flat  
package).  
*B  
*C  
3438781  
3554946  
HRP  
HRP  
11/14/2011 Updated Package Diagram (to current revision).  
03/19/2012 Changed status from Preliminary to Final.  
Updated Radiation Performance (Updated Radiation Data, Prototyping  
Options).  
Updated Features (Added (PMAX = 315 mW)).  
Updated Functional Description (Added the paragraph “Easy memory  
expansion is provided by utilizing OE, CE, and tri-state drivers.”).  
Updated Maximum Ratings (DC voltage applied to outputs in High Z state, DC  
input voltage).  
Updated AC Switching Characteristics(Changed the maximum value of tDOE  
parameter from 7 ns to 6 ns).  
Updated Ordering Information (Additional part numbers added).  
Document Number: 001-64292 Rev. *C  
Page 15 of 16  
CYRS1049DV33  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office  
closest to you, visit us at Cypress Locations.  
Products  
Automotive  
cypress.com/go/automotive  
cypress.com/go/clocks  
cypress.com/go/interface  
cypress.com/go/powerpsoc  
cypress.com/go/plc  
PSoC Solutions  
Clocks & Buffers  
Interface  
psoc.cypress.com/solutions  
PSoC 1 | PSoC 3 | PSoC 5  
Lighting & Power Control  
Memory  
cypress.com/go/memory  
cypress.com/go/image  
cypress.com/go/psoc  
Optical & Image Sensing  
PSoC  
Touch Sensing  
USB Controllers  
Wireless/RF  
cypress.com/go/touch  
cypress.com/go/USB  
cypress.com/go/wireless  
© Cypress Semiconductor Corporation, 2010-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-64292 Rev. *C  
Revised March 19, 2012  
Page 16 of 16  
RadStop™ is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.  
厂商 型号 描述 页数 下载

EDI

 		CYL 高压缸硅整流[ HIGH VOLTAGE CYLINDER SILICON RECTIFIERS ] 2 页

CYPRESS

 		CYL008M162FFBU-1ABAI [ Synchronous DRAM, 8MX16, 8ns, CMOS, PBGA54, 8 X 8 MM, 1 MM HEIGHT, 0.80 MM PITCH, VFBGA-54 ] 46 页

ETC

 		CYL2T0201-AIP 成帧器和映射器\n[ Framers and Mappers ] 4 页

CYPRESS

 		CYLE1049DV33-12VE [ Standard SRAM, 512KX8, 12ns, CMOS, PDSO36, PLASTIC, SOP-36 ] 16 页

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