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8SLVP1102ANLG

型号：

8SLVP1102ANLG

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

23 页

PDF大小：

943 K

下载PDF手册
Low Phase Noise, 1-to-2, 3.3V, 2.5V  
LVPECL Output Fanout Buffer  
8SLVP1102  
Datasheet  
Description  
Features  
The 8SLVP1102 is a high-performance differential LVPECL fanout  
buffer. The device is designed for the fanout of high-frequency, very  
low additive phase-noise clock and data signals. The 8SLVP1102 is  
characterized to operate from a 3.3V or 2.5V power supply.  
• Two low skew, low additive jitter LVPECL output pairs  
• Differential PCLK, nPCLK pair can accept the following differential  
input levels: LVDS, LVPECL, CML  
• Maximum input clock frequency: 2GHz  
• Output skew: 5ps (typical)  
• Propagation delay: 250ps (maximum)  
Guaranteed output-to-output and part-to-part skew characteristics  
make the 8SLVP1102 ideal for those clock distribution applications  
demanding well-defined performance and repeatability. One  
differential input and two low skew outputs are available. The  
integrated bias voltage reference enables easy interfacing of  
single-ended signals to the device input. The device is optimized for  
low power consumption and low additive phase noise.  
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,  
12kHz - 20MHz: 49fs (maximum)  
• Full 3.3V or 2.5V supply voltage  
• Maximum device current consumption (IEE): 34mA (maximum)  
• Available in lead-free (RoHS 6), 16-Lead VFQFPN package  
• -40°C to 85°C ambient operating temperature  
• Supports case temperature ≤ 105°C operations  
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also  
accept single-ended LVCMOS levels. See Applications section  
Wiring the Differential Input Levels to Accept Single-ended Levels  
(Figure 1A and Figure 1B)  
Block Diagram  
Pin Assignment  
V
CC  
16 15 14 13  
1
2
3
VEE  
nc  
12  
11  
10  
nQ1  
Q1  
Q0  
nQ0  
PCLK  
nPCLK  
nc  
nQ0  
Q0  
Q1  
nQ1  
nc  
4
9
5
6
7
8
Voltage  
Reference  
VREF  
8SLVP1102  
16-Lead VFQFPN  
3.0mm x 3.0mm x 0.925mm package body  
NL Package  
Top View  
8SLVP1102 May 8, 2020  
1
©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
Pin Descriptions and Characteristics  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
1, 16  
VEE  
Power  
Negative supply pins.  
2, 3, 4,  
13, 14, 15  
nc  
Unused  
Do not connect.  
5
6
VCC  
Power  
Input  
Power supply pin.  
PCLK  
Pulldown  
Non-inverting differential LVPECL clock/data input.  
Pullup/  
Pulldown/  
Inverting differential LVPECL clock/data input. VCC/2 default when left  
floating.  
7
nPCLK  
Input  
8
VREF  
Output  
Output  
Output  
Bias voltage reference for the PCLK input.  
9, 10  
11, 12  
Q0, nQ0  
Q1, nQ1  
Differential output pair 0. LVPECL interface levels.  
Differential output pair 1. LVPECL interface levels.  
NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
pF  
Input Capacitance  
Input Pulldown Resistor  
Input Pullup Resistor  
2
RPULLDOWN  
RPULLUP  
51  
51  
k  
k  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum  
Ratings may cause permanent damage to the device. These ratings  
are stress specifications only. Functional operation of product at  
these conditions or any conditions beyond those listed in the DC  
Characteristics or AC Characteristics is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect  
product reliability.  
Item  
Rating  
Supply Voltage, VCC  
Inputs, VI  
3.63V  
-0.5V to VCC + 0.5V  
Outputs, IO (LVPECL)  
Continuous Current  
Surge Current  
50mA  
100mA  
Input Sink/Source, IREF  
±2mA  
Maximum Junction Temperature, TJ,MAX  
Storage Temperature, TSTG  
125°C  
-65C to 150C  
2000V  
ESD - Human Body Model, NOTE 1  
ESD - Charged Device Model, NOTE 1  
1500V  
NOTE 1: According to JEDEC/JESD 22-A114/22-C101.  
DC Electrical Characteristics  
Table 3A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
3.465  
34  
Units  
V
Power Supply Voltage  
Power Supply Current  
3.135  
3.3V  
IEE  
mA  
Q0 and Q1 terminated  
ICC  
Power Supply Current  
106  
mA  
50to VCC – 2V  
Table 3B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
2.625  
31  
Units  
V
Power Supply Voltage  
Power Supply Current  
2.375  
2.5V  
IEE  
mA  
Q0 and Q1 terminated  
ICC  
Power Supply Current  
103  
mA  
50to VCC – 2V  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
Table 3C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input High  
Current  
IIH  
PCLK, nPCLK  
VCC = VIN = 3.465V  
150  
µA  
PCLK  
V
CC = 3.465V, VIN = 0V  
-10  
µA  
µA  
Input Low  
Current  
IIL  
nPCLK  
VCC = 3.465V, VIN = 0V  
REF = ±1mA  
-150  
Reference Voltage for Input  
Bias  
VREF  
I
VCC – 1.6  
VCC – 1.3  
VCC – 1.1  
V
VOH  
VOL  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
VCC – 1.1  
VCC – 2.0  
VCC – 0.9  
VCC – 0.7  
VCC – 1.5  
V
V
VCC – 1.65  
NOTE 1: Outputs terminated with 50to VCC – 2V.  
Table 3D. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input High  
Current  
IIH  
PCLK, nPCLK  
VCC = VIN = 2.625V  
150  
µA  
PCLK  
V
CC = 2.625V, VIN = 0V  
-10  
µA  
µA  
Input Low  
Current  
IIL  
nPCLK  
VCC = 2.625V, VIN = 0V  
-150  
Reference Voltage for Input  
Bias  
VREF  
I
REF = ±1mA  
VCC – 1.6  
VCC – 1.3  
VCC – 1.1  
V
VOH  
VOL  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
VCC – 1.1  
VCC – 2.0  
VCC – 0.9  
VCC – 1.6  
VCC – 0.7  
VCC – 1.5  
V
V
NOTE 1: Outputs terminated with 50to VCC – 2V.  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
AC Electrical Characteristics  
Table 4. AC Electrical Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
PCLK,  
nPCLK  
fREF  
Input Frequency  
2
GHz  
V/ns  
ps  
PCLK,  
nPCLK  
V/t  
Input Edge Rate  
1.5  
70  
PCLK, nPCLK to any Qx, nQx  
for VPP = 0.1V or 0.3V  
tPD  
Propagation Delay; NOTE 1  
140  
250  
tsk(o)  
tsk(p)  
tsk(pp)  
Output Skew; NOTE 2, 3  
Output Pulse Skew  
5
6
15  
10  
ps  
ps  
ps  
fREF = 100MHz  
Part-to-Part Skew; NOTE 3, 4  
80  
230  
f
REF = 122.88MHz Sine Wave, VPP = 1V,  
157  
92  
91  
38  
36  
36  
60  
49  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
Integration Range: 1kHz – 40MHz  
fREF = 122.88MHz Sine Wave, VPP = 1V,  
Integration Range: 10kHz – 20MHz  
fREF = 122.88MHz Sine Wave, VPP = 1V,  
Integration Range: 12kHz – 20MHz  
fREF = 156.25MHz Square Wave, VPP = 1V,  
Integration Range: 1kHz – 40MHz  
51  
49  
49  
77  
63  
63  
Buffer Additive Phase Jitter,  
RMS; refer to Additive Phase  
Jitter Section  
fREF = 156.25MHz Square Wave, VPP = 1V,  
Integration Range: 10kHz – 20MHz  
tJIT  
fREF = 156.25MHz Square Wave, VPP = 1V,  
Integration Range: 12kHz – 20MHz  
fREF = 156.25MHz Square Wave, VPP = 0.5V,  
Integration Range: 1kHz – 40MHz  
fREF = 156.25MHz Square Wave, VPP = 0.5V,  
Integration Range: 10kHz – 20MHz  
fREF = 156.25MHz Square Wave, VPP = 0.5V,  
Integration Range: 12kHz – 20MHz  
49  
tR / tF  
VPP  
Output Rise/ Fall Time  
20% to 80%  
fREF < 1.5GHz  
fREF > 1.5GHz  
35  
0.1  
0.2  
110  
180  
1.5  
1.5  
ps  
V
Peak-to-Peak Input Voltage;  
NOTE 5, 7  
V
Common Mode Input  
Voltage; NOTE 5, 6, 7  
VCMR  
1.0  
VCC – 0.6  
V
VCC = 3.3V, fREF 2GHz  
VCC = 2.5V, fREF 2GHz  
VCC = 3.3V, fREF 2GHz  
VCC = 2.5V, fREF 2GHz  
0.45  
0.4  
0.75  
0.65  
1.5  
1.0  
1.0  
2.0  
2.0  
V
V
V
V
Output Voltage Swing,  
Peak-to-Peak  
VO(pp)  
0.9  
Differential Output Voltage  
Swing, Peak-to-Peak  
VDIFF_OUT  
0.8  
1.3  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE 1: Measured from the differential input crossing point to the differential output crosspoint.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.  
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and  
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.  
NOTE 5: VIL should not be less than -0.3V. VIH should not be higher than VCC  
.
NOTE 6: Common mode input voltage is defined as the crosspoint.  
NOTE 7: For single-ended LVCMOS input applications, please refer to the Applications Information, Wiring the Differential Input to accept  
single-ended levels, Figures 1A and 1B.  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental  
compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot  
and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a  
specified offset from the fundamental frequency to the power value of  
the fundamental. This ratio is expressed in decibels (dBm) or a ratio  
of the power in the 1Hz band to the power in the fundamental. When  
the required offset is specified, the phase noise is called a dBc value,  
which simply means dBm at a specified offset from the fundamental.  
By investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the entire  
time record of the signal. It is mathematically possible to calculate an  
expected bit error rate given a phase noise plot.  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements have  
issues relating to the limitations of the equipment. Often the noise  
floor of the equipment is higher than the noise floor of the device. This  
is illustrated above. The device meets the noise floor of what is  
shown, but can actually be lower. The phase noise is dependent on  
the input source and measurement equipment.  
Measured using a Wenzel 156.25MHz Oscillator as the input source.  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
Parameter Measurement Information  
2V  
2V  
SCOPE  
SCOPE  
VCC  
VCC  
Qx  
Qx  
nQx  
nQx  
VEE  
VEE  
-1.3V ± 0.165V  
-0.5V ± 0.125V  
3.3V LVPECL Output Load AC Test Circuit  
2.5V LVPECL Output Load AC Test Circuit  
V
CC  
nQx  
Qx  
nPCLK  
VPP  
Cross Points  
nQy  
Qy  
PCLK  
VCMR  
V
EE  
Differential Input Level  
Output Skew  
nPCLK  
PCLK  
Part 1  
nQx  
Qx  
nQy  
Qy  
Part 2  
nQy  
tPLH  
tPHL  
Qy  
tsk(pp)  
tsk(p)= |tPHL - tPLH  
|
Part-to-Part Skew  
Pulse Skew  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
Parameter Measurement Information, continued  
nPCLK  
nQ0, nQ1  
PCLK  
nQ0, nQ1  
Q0, Q1  
Q0, Q1  
tPD  
Propagation Delay  
Output Rise/Fall Time  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
Applications Information  
Wiring the Differential Input to Accept Single-Ended Levels  
The 8SLVP1102 inputs can be interfaced to LVPECL, LVDS, CML or  
LVCMOS drivers. Figure 1A illustrates how to DC couple a single  
LVCMOS input to the 8SLVP1102. The value of the series resistance  
RS is calculated as the difference between the transmission line  
impedance and the driver output impedance. This resistor should be  
placed close to the LVCMOS driver. To avoid cross-coupling of  
single-ended LVCMOS signals, apply the LVCMOS signals to no  
more than one PCLK input.  
A practical method to implement Vth is shown in Figure 1B below.  
The reference voltage Vth = V1 = VCC/2, is generated by the bias  
resistors R1 and R2. The bypass capacitor (C1) is used to help filter  
noise on the DC bias. This bias circuit should be located as close to  
the input pin as possible.  
The ratio of R1 and R2 might need to be adjusted to position the V1  
in the center of the input voltage swing. For example, if the input clock  
swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted  
to set V1 at 1.25V. The values below apply when both the  
single-ended swing and VCC are at the same voltage.  
Figure 1A. DC-Coupling a Single LVCMOS Input to the  
SLVP1102  
When using single-ended signaling, the noise rejection benefits of  
differential signaling are reduced. Even though the differential input  
can handle full rail LVCMOS signaling, it is recommended that the  
amplitude be reduced, particularly if both input references are  
LVCMOS to minimize cross talk. The datasheet specifies a lower  
differential amplitude, however this only applies to differential signals.  
For single-ended applications, the swing can be larger, however VIL  
This configuration requires that the sum of the output impedance of  
thedriver (Ro) and the series resistance (Rs) equals the transmission  
line impedance. R3 and R4 in parallel should equal the transmission  
line impedance; for most 50applications, R3 and R4 will be 100.  
The values of the resistors can be increased to reduce the loading for  
slower and weaker LVCMOS driver.  
Though some of the recommended components of Figure 1B might  
not be used, the pads should be placed in the layout so that they can  
be utilized for debugging purposes. The datasheet specifications are  
characterized and guaranteed by using a differential signal.  
cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V.  
Figure 1B shows a way to attenuate the PCLK input level by a factor  
of two as well as matching the transmission line between the  
LVCMOS driver and the 8SLVP1102 at both the source and the load.  
VCC  
VC C  
VCC  
VCC  
R3  
100  
R1  
1K  
Ro  
RS  
Zo = 50 Ohm  
+
Receiv er  
Driver  
V1  
R4  
-
100  
R2  
1K  
Ro +Rs = Zo  
C1  
0.1uF  
Figure 1B. Alternative DC Coupling a Single LVCMOS Input to the 8SLVP1102  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
Recommendations for Unused Output Pins  
Outputs:  
LVPECL Outputs  
All unused LVPECL outputs can be left floating. We recommend that  
there is no trace attached. Both sides of the differential output pair  
should either be left floating or terminated.  
8SLVP1102 May 8, 2020  
10  
©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
3.3V LVPECL Clock Input Interface  
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other  
differential signals. Both signals must meet the VPP and VCMR input  
requirements. Figures 2A to 2E show interface examples for the  
PCLK/ nPCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. If the driver is  
from another vendor, use their termination recommendation. Please  
consult with the vendor of the driver component to confirm the driver  
termination requirements.  
3.3V  
3.3V  
3.3V  
3.3V  
Zo = 50  
3.3V  
PCLK  
PCLK  
R1  
100  
nPCLK  
Zo = 50  
nPCLK  
LVPECL  
LVPECL  
Input  
CML  
CML Built-In Pullup  
Input  
Figure 2A. PCLK/nPCLK Input Driven by a CML Driver  
Figure 2B. PCLK/nPCLK Input Driven by a  
Built-In Pullup CML Driver  
3.3V  
3.3V  
3.3V  
R3  
R4  
125  
125  
Zo = 50  
Zo = 50  
PCLK  
nPCLK  
LVPECL  
Input  
LVPECL  
R1  
84  
R2  
84  
Figure 2C. PCLK/nPCLK Input Driven by a  
3.3V LVPECL Driver  
Figure 2D. PCLK/nPCLK Input Driven by a  
3.3V LVPECL Driver with AC Couple  
3.3V  
3.3V  
Zo = 50Ω  
PCLK  
R1  
100Ω  
nPCLK  
Zo = 50Ω  
LVPECL  
Input  
LVDS  
Figure 2E. PCLK/nPCLK Input Driven by a  
3.3V LVDS Driver  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
2.5V LVPECL Clock Input Interface  
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other  
differential signals. Both signals must meet the VPP and VCMR input  
requirements. Figures 3A to 3E show interface examples for the  
PCLK/ nPCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. If the driver is  
from another vendor, use their termination recommendation. Please  
consult with the vendor of the driver component to confirm the driver  
termination requirements.  
2.5V  
2.5V  
2.5V  
2.5V  
2.5V  
PCLK  
PCLK  
nPCLK  
nPCLK  
LVPECL  
CML Built-In Pullup  
LVPECL  
Input  
CML  
Input  
Figure 3A. PCLK/nPCLK Input Driven by a CML Driver  
Figure 3B. PCLK/nPCLK Input Driven by a  
Built-In Pullup CML Driver  
2.5V  
2.5V  
2.5V  
PCLK  
nPCLK  
LVPECL  
Input  
LVPECL  
Figure 3C. PCLK/nPCLK Input Driven by a  
2.5V LVPECL Driver  
Figure 3D. PCLK/nPCLK Input Driven by a  
2.5V LVPECL Driver with AC Couple  
PCLK  
nPCLK  
Figure 3E. PCLK/nPCLK Input Driven by a  
2.5V LVDS Driver  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
VFQFPN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 4. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
PIN  
SOLDER  
EXPOSED HEAT SLUG  
PIN  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
transmission lines. Matched impedance techniques should be used  
to maximize operating frequency and minimize signal distortion.  
Figures 5A and 5B show two different layouts which are  
recommended only as guidelines. Other suitable clock layouts may  
exist and it would be recommended that the board designers  
simulate to guarantee compatibility across all printed circuit and clock  
component process variations.  
The differential outputs are a low impedance follower output that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are designed to drive 50  
3.3V  
R3  
R4  
125Ω  
125Ω  
3.3V  
3.3V  
Z
o = 50Ω  
+
_
Input  
Zo = 50Ω  
R1  
84Ω  
R2  
84Ω  
Figure 5A. 3.3V LVPECL Output Termination  
Figure 5B. 3.3V LVPECL Output Termination  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
Termination for 2.5V LVPECL Outputs  
Figure 6A and Figure 6B show examples of termination for 2.5V  
LVPECLdriver. These terminations are equivalent to terminating 50  
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground  
level. The R3 in Figure 6B can be eliminated and the termination is  
shown in Figure 6C.  
2.5V  
VCC = 2.5V  
2.5V  
2.5V  
VCC = 2.5V  
50  
R1  
R3  
250  
250  
+
50  
50  
+
–
50  
–
2.5V LVPECL Driver  
R1  
50  
R2  
50  
2.5V LVPECL Driver  
R2  
62.5  
R4  
62.5  
R3  
18  
Figure 6A. 2.5V LVPECL Driver Termination Example  
Figure 6B. 2.5V LVPECL Driver Termination Example  
2.5V  
VCC = 2.5V  
50  
+
50  
–
2.5V LVPECL Driver  
R1  
50  
R2  
50  
Figure 6C. 2.5V LVPECL Driver Termination Example  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8SLVP1102.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8SLVP1102 is the sum of the core power plus the power dissipated in the load(s).  
The following is the power dissipation for VCC = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 34mA = 117.81mW  
Power (outputs)MAX = 33.2mW/Loaded Output pair  
If all outputs are loaded, the total power is 2 * 33.2mW = 66.4mW  
Total Power_MAX (3.465V, with all outputs switching) = 117.81mW + 66.4mW = 184.21mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 74.7°C/W per Table 5 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.184W * 74.7°C/W = 98.7°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 5. Thermal Resistance JA for 16-Lead VFQFPN, Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
8SLVP1102 May 8, 2020  
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8SLVP1102 DATASHEET  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.  
LVPECL output driver circuit and termination are shown in Figure 7.  
VCC  
Q1  
VOUT  
RL  
VCC - 2V  
Figure 7. LVPECL Driver Circuit and Termination  
To calculate power dissipation into the load, use the following equations which assume a 50load, and a termination voltage of VCC – 2V.  
These are typical calculations.  
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.7V  
(VCC_MAX – VOH_MAX) = 0.7V  
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.5V  
(VCC_MAX – VOL_MAX) = 1.5V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =  
[(2V – 0.7V)/50] * 0.7V = 18.2mW  
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =  
[(2V – 1.5V)/50] * 1.5V = 15mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 33.2mW  
8SLVP1102 May 8, 2020  
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Case Temperature Considerations  
This device supports applications in a natural convection environment which does not have any thermal conductivity through ambient air. The  
printed circuit board (PCB) is typically in a sealed enclosure without any natural or forced air flow and is kept at or below a specific temperature.  
The device package design incorporates an exposed pad (ePad) with enhanced thermal parameters which is soldered to the PCB where most  
of the heat escapes from the bottom exposed pad. For this type of application, it is recommended to use the junction-to-board thermal  
characterization parameter ΨJB (Psi-JB) to calculate the junction temperature (TJ) and ensure it does not exceed the maximum allowed  
junction temperature in Absolute Maximum Ratings.  
The junction-to-board thermal characterization parameter, ΨJB, is calculated using the following equation:  
TJ = TCB + ΨJB x Pd, where  
TJ = Junction temperature at steady state condition in (oC).  
TCB = Case temperature (Bottom) at steady state condition in (oC).  
ΨJB = Thermal characterization parameter to report the difference between junction temperature and the temperature of the board  
measured at the top surface of the board.  
Pd = Power dissipation (W) in desired operating configuration.  
The ePad provides a low thermal resistance path for heat transfer to the PCB and represents the key pathway to transfer heat away from the  
IC to the PCB. Its critical that the connection of the exposed pad to the PCB is properly constructed to maintain the desired IC case temperature  
(TCB). A good connection ensures that temperature at the exposed pad (TCB) and the board temperature (TB) are relatively the same. An  
improper connection can lead to increased junction temperature, increased power consumption, and decreased electrical performance. In  
addition, there could be long-term reliability issues and increased failure rate.  
Example calculation for junction temperature (TJ): TJ = TCB + ΨJB x Pd  
Package type:  
16-Lead VFQFN  
1.0 C/W  
ΨJB  
TCB  
Pd  
105oC  
0.184W  
For the variables above, the junction temperature is equal to 105.2oC. Since this is below the maximum junction temperature of 125oC, there  
are no long-term reliability concerns. In addition, since the junction temperature at which the device was characterized using forced convection  
is 98.7oC, this device can function without the degradation of the specified AC or DC parameters.  
8SLVP1102 May 8, 2020  
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©2020 Renesas Electronics Corporation  
8SLVP1102 DATASHEET  
Reliability Information  
Table 6. JA vs. Air Flow Table for a 16-Lead VFQFPN  
JA at 0 Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
Transistor Count  
The transistor count for the 8SLVP1102 is: 204  
Package Outline Drawings  
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is  
the most current data available.  
www.idt.com/document/psc/16-vfqfpn-package-outline-drawing-30-x-30-x-09-mm-05-mm-170-x-170-mm-epad-nlnlg16p2  
Ordering Information  
Table 7. Ordering Information  
Part/Order Number  
8SLVP1102ANLGI  
8SLVP1102ANLGI8  
8SLVP1102ANLGI/W  
Marking  
102AI  
102AI  
Package  
Shipping Packaging  
Tube  
Tape & Reel, Pin 1 Orientation: EIA-481-C  
Tape & Reel, Pin 1 Orientation: EIA-481-D  
Temperature  
-40C to 85C  
-40C to 85C  
-40C to 85C  
“Lead-Free” 16-Lead VFQFPN  
“Lead-Free” 16-Lead VFQFPN  
“Lead-Free” 16-Lead VFQFPN  
102AI  
NOTE: Parts that are ordered with an “G” suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
Table 8. Pin 1 Orientation in Tape and Reel Packaging  
Part Number Suffix  
Pin 1 Orientation  
Illustration  
8
Quadrant 1 (EIA-481-C)  
/W  
Quadrant 2 (EIA-481-D)  
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8SLVP1102 DATASHEET  
Revision History  
Revision Date  
Description of Change  
May 8, 2020  
Added Case Temperature Considerations  
Updated the package outline drawings; however, no technical changes  
Completed other minor changes  
March 13, 2018  
February 25, 2014 Ordering Information: changed Tray to Tube.  
January 23, 2014 Changed NOTE 5 to read: VIL should not be less than -0.3V. VIH should not be higher than VCC  
.
Added Features Bullet: Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also accept single-ended  
LVCMOS levels.  
February 1, 2013  
August 2, 2012  
Added NOTE 7 to VPP, VCMR.  
Updated the “Wiring the Differential Input to Accept Single-Ended Levels” note.  
Changed datasheet title to Low Phase Noise, 1-to-2, 3.3V, 2.5V LVPECL Output Fanout Buffer  
Ordering Information Table - added additional row.  
Added Orientation Packaging Table.  
8SLVP1102 May 8, 2020  
20  
©2020 Renesas Electronics Corporation  
16-VFQFPN Package Outline Drawing  
3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad  
NL/NLG16P2, PSC-4169-02, Rev 05, Page 1  
16-VFQFPN Package Outline Drawing  
3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad  
NL/NLG16P2, PSC-4169-02, Rev 05, Page 2  
Package Revision History  
Description  
Rev 04 Remove Bookmak at Pdf Format & Update Thickness Tolerance  
Change QFN to VFQFPN  
Date Created Rev No.  
Oct 25, 2017  
Jan 18, 2018  
Rev 05  
IMPORTANT NOTICE AND DISCLAIMER  
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL  
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING  
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND  
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,  
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A  
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible  
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)  
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These  
resources are subject to change without notice. Renesas grants you permission to use these resources only for  
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prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.  
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,  
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject  
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources  
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.  
(Rev.1.0 Mar 2020)  
Corporate Headquarters  
Contact Information  
TOYOSU FORESIA, 3-2-24 Toyosu,  
Koto-ku, Tokyo 135-0061, Japan  
www.renesas.com  
For further information on a product, technology, the most  
up-to-date version of a document, or your nearest sales  
office, please visit:  
www.renesas.com/contact/  
Trademarks  
Renesas and the Renesas logo are trademarks of Renesas  
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© 2020 Renesas Electronics Corporation. All rights reserved.  
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