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YW80486DX4WB100

型号：

YW80486DX4WB100

品牌：

INTEL[ INTEL ]

页数：

49 页

PDF大小：

1342 K

下载PDF手册
EMBEDDED WRITE-BACK ENHANCED  
IntelDX4™ PROCESSOR  
■ Up to 100 MHz Operation  
■ SL Technology  
■ Integrated Floating-Point Unit  
■ Speed-Multiplying Technology  
■ 32-Bit RISC Technology Core  
■ 16-Kbyte Write-Back Cache  
■ Data Bus Parity Generation and Checking  
■ Boundary Scan (JTAG)  
■ 3.3-Volt Processor, 75 MHz, 25 MHz CLK  
— 208-Lead Shrink Quad Flat Pack (SQFP)  
■ 3.3-Volt Processor, 100 MHz, 33 MHz CLK  
— 208-Lead Shrink Quad Flat Pack (SQFP)  
— 168-Pin Pin Grid Array (PGA)  
■ 3.3 V Core Operation with 5 V Tolerant  
I/O Buffers  
■ Burst Bus Cycles  
■ Binary Compatible with Large Software  
■ Dynamic Bus Sizing for 8- and 16-bit  
Base  
Data Bus Devices  
64-Bit Interunit Transfer Bus  
32-Bit Data Bus  
CLKMUL  
Core  
Clock  
CLK  
Clock  
Multiplier  
32-Bit Data Bus  
Linear Address  
32  
PCD  
PWT  
Bus Interface  
Base/  
Index  
Bus  
A31-A2 BE3#- BE0#  
Barrel  
Shifter  
Segmentation  
2
Cache Unit  
Unit  
Paging  
Unit  
Address  
Drivers  
20  
Descriptor  
Registers  
Register  
File  
32  
Write Buffers  
4 x 32  
Physical  
Address  
16 Kbyte  
Cache  
32  
D31-D0  
Translation  
Lookaside  
Buffer  
Limit and  
Attribute PLA  
Data Bus  
Transceivers  
ALU  
ADS# W/R# D/C# M/IO# PCD  
PWT RDY# LOCK# PLOCK#  
BOFF# A20M# BREQ HOLD  
HLDA RESET SRESET INTR  
NMI SMI# SMIACT# FERR#  
IGNNE# STPCLK#  
Bus Control  
Displacement Bus  
32  
Request  
Sequencer  
Prefetcher  
Micro-  
Instruction  
BRDY# BLAST#  
BS16# BS8#  
Burst Bus  
Control  
32-Byte Code  
Queue  
Bus Size  
Control  
Code  
Stream  
KEN# FLUSH# AHOLD EADS#  
CACHE# HITM# INV WB/WT#  
2 x 16 Bytes  
Control &  
Protection  
Test Unit  
Cache  
Control  
Floating  
Point Unit  
Instruction  
Decode  
24  
Parity  
Generation  
and Control  
PCHK# DP3-DP0  
Floating  
Point  
Register File  
Decoded  
Instruction  
Path  
Control  
ROM  
Boundary  
Scan  
TCK TMS TDI TDO  
Control  
A3232-01  
Figure 1. Embedded Write-Back Enhanced IntelDX4™ Processor Block Diagram  
© INTEL CORPORATION, 2004 August 2004 Order Number: 272771-003  
Information in this document is provided in connection with Intel products. No license, express or implied, by  
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in  
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel  
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or  
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright  
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life  
sustaining applications.  
Intel may make changes to specifications and product descriptions at any time, without notice.  
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or  
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or  
incompatibilities arising from future changes to them.  
The Embedded Write-Back Enhanced IntelDX4™ processor may contain design defects or errors known as  
errata which may cause the product to deviate from published specifications. Current characterized errata are  
available on request.  
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your  
product order.  
Copies of documents which have an ordering number and are referenced in this document, or other Intel  
literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.  
Copyright © Intel Corporation, 1997, 2004  
*Third-party brands and names are the property of their respective owners.  
Contents  
EMBEDDED WRITE-BACK ENHANCED  
IntelDX4™ PROCESSOR  
1.0 INTRODUCTION ........................................................................................................................................ 1  
1.1 Features ............................................................................................................................................. 1  
1.2 Family Members ................................................................................................................................. 2  
2.0 HOW TO USE THIS DOCUMENT ............................................................................................................. 3  
3.0 PIN DESCRIPTIONS ................................................................................................................................. 3  
3.1 Pin Assignments ................................................................................................................................. 3  
3.2 Pin Quick Reference ......................................................................................................................... 16  
4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW ............................................................................. 26  
4.1 CPUID Instruction ............................................................................................................................. 26  
4.1.1 Operation of the CPUID Instruction ....................................................................................... 26  
4.2 Identification After Reset .................................................................................................................. 28  
4.3 Boundary Scan (JTAG) .................................................................................................................... 28  
4.3.1 Device Identification ............................................................................................................... 28  
4.3.2 Boundary Scan Register Bits and Bit Order ........................................................................... 29  
5.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 30  
5.1 Maximum Ratings ............................................................................................................................. 30  
5.2 DC Specifications ............................................................................................................................. 30  
5.3 AC Specifications ............................................................................................................................. 33  
5.4 Capacitive Derating Curves .............................................................................................................. 40  
6.0 MECHANICAL DATA .............................................................................................................................. 42  
6.1 Package Dimensions ........................................................................................................................ 42  
6.2 Package Thermal Specifications ...................................................................................................... 44  
FIGURES  
Figure 1.  
Embedded Write-Back Enhanced IntelDX4™ Processor Block Diagram ................................... i  
Figure 2.  
Package Diagram for 208-Lead SQFP Embedded Write-Back Enhanced  
IntelDX4™ Processor ................................................................................................................ 4  
Figure 3.  
Package Diagram for 168-Pin PGA Embedded Write-Back Enhanced  
IntelDX4™ Processor .............................................................................................................. 10  
Figure 4.  
Figure 5.  
Figure 6.  
Figure 7.  
Figure 8.  
Figure 9.  
Figure 10.  
Figure 11.  
CLK Waveform ........................................................................................................................ 36  
Input Setup and Hold Timing ................................................................................................... 36  
Input Setup and Hold Timing ................................................................................................... 37  
PCHK# Valid Delay Timing ...................................................................................................... 37  
Output Valid Delay Timing ....................................................................................................... 38  
Maximum Float Delay Timing .................................................................................................. 38  
TCK Waveform ........................................................................................................................ 39  
Test Signal Timing Diagram .................................................................................................... 39  
iii  
Contents  
Figure 12.  
Figure 13.  
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions  
for a Low-to-High Transition .....................................................................................................40  
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions  
for a High-to-Low Transition .....................................................................................................40  
Figure 14.  
Figure 15.  
Figure 16.  
Typical Loading Delay versus Load Capacitance in Mixed Voltage System ...........................41  
208-Lead SQFP Package Dimensions .................................................................................... 42  
Principal Dimensions and Data for 168-Pin Grid Array Package .............................................43  
TABLES  
Table 1.  
Table 2.  
Table 3.  
Table 4.  
Table 5.  
Table 6.  
Table 7.  
Table 8.  
Table 9.  
Table 10.  
Table 11.  
Table 12.  
Table 13.  
Table 14.  
Table 15.  
Table 16.  
Table 17.  
Table 18.  
Table 19.  
Table 20.  
Table 21.  
Table 22.  
Table 23.  
Table 24.  
Table 25.  
Table 26.  
The Embedded Write-Back Enhanced IntelDX4™ Processor Family .......................................2  
Pinout Differences for 208-Lead SQFP Package ......................................................................5  
Pin Assignment for 208-Lead SQFP Package ...........................................................................6  
Pin Cross Reference for 208-Lead SQFP Package ...................................................................8  
Pinout Differences for 168-Pin PGA Package .........................................................................11  
Pin Assignment for 168-Pin PGA Package ..............................................................................12  
Pin Cross Reference for 168-Pin PGA Package ......................................................................14  
Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions .............................16  
Output Pins ..............................................................................................................................24  
Input/Output Pins .....................................................................................................................24  
Test Pins ..................................................................................................................................25  
Input Pins .................................................................................................................................25  
CPUID Instruction Description .................................................................................................26  
Boundary Scan Component Identification Code (Write-Through/Standard Bus Mode) ...........28  
Boundary Scan Component Identification Code (Write-Back/Enhanced Bus Mode) ...............29  
Absolute Maximum Ratings .....................................................................................................30  
Operating Supply Voltages ......................................................................................................30  
DC Specifications .....................................................................................................................31  
I
CC Values ................................................................................................................................32  
AC Characteristics ...................................................................................................................33  
AC Specifications for the Test Access Port .............................................................................35  
168-Pin Ceramic PGA Package Dimensions ...........................................................................43  
Ceramic PGA Package Dimension Symbols ...........................................................................44  
Thermal Resistance, θJA (°C/W) .............................................................................................45  
Thermal Resistance, θJC (°C/W) .............................................................................................45  
Maximum Tambient, TA max (°C) ...............................................................................................45  
iv  
Embedded Write-Back Enhanced IntelDX4™ Processor  
1.0 INTRODUCTION  
1.1 Features  
The embedded Write-Back Enhanced IntelDX4™  
processor provides high performance to 32-bit,  
embedded applications. Designed for applications  
that need a floating-point unit, the processor is ideal  
for embedded designs running DOS*, Microsoft  
Windows*, OS/2*, or UNIX* applications written for  
the Intel architecture. Projects can be completed  
quickly using the wide range of software tools,  
utilities, assemblers and compilers that are available  
for desktop computer systems. Also, developers can  
find advantages in using existing chipsets and  
peripheral components in their embedded designs.  
The Embedded Write-Back Enhanced IntelDX4  
processor offers these features:  
• 32-bit RISC-Technology Core — The Embedded  
Write-Back Enhanced IntelDX4 processor  
performs a complete set of arithmetic and logical  
operations on 8-, 16-, and 32-bit data types using  
a full-width ALU and eight general purpose  
registers.  
• Single Cycle Execution — Many instructions  
execute in a single clock cycle.  
• Instruction Pipelining — Overlapped instruction  
fetching, decoding, address translation and  
execution.  
The Embedded Write-Back Enhanced IntelDX4  
processor is binary compatible with the Intel386™  
and earlier Intel processors. Compared with the  
Intel386 processor, it provides faster execution of  
many commonly-used instructions. It also provides  
the benefits of an integrated, 16-Kbyte, write-back  
cache for code and data. Its data bus can operate in  
burst mode which provides up to 106-Mbyte-per-  
second transfers for cache-line fills and instruction  
prefetches.  
• On-Chip Floating-Point Unit — Intel486™  
processors support the 32-, 64-, and 80-bit formats  
specified in IEEE standard 754. The unit is binary  
compatible with the 8087, Intel287™, Intel387™  
coprocessors, and Intel OverDrive® processor.  
• On-Chip Cache with Cache Consistency  
Support — A 16-Kbyte internal cache is used for  
both data and instructions. It is configurable to be  
write-back or write-through on a line-by-line basis.  
The internal cache implements a modified MESI  
protocol, which is applicable to uniprocessor  
Intel’s SL technology is incorporated in the  
Embedded  
Write-Back  
Enhanced  
IntelDX4  
systems. Cache hits provide zero wait-state  
access times for data within the cache. Bus activity  
is tracked to detect alterations in the memory  
represented by the internal cache. The internal  
cache can be invalidated or flushed so that an  
external cache controller can maintain cache  
consistency.  
processor. Utilizing Intel’s System Management  
Mode (SMM) enables designers to develop energy-  
efficient systems.  
Two component packages are available:  
• 168-pin Pin Grid Array (PGA)  
• 208-lead Shrink Quad Flat Pack (SQFP)  
• External Cache Control — Write-back and flush  
controls for an external cache are provided so the  
processor can maintain cache consistency.  
The processor operates at either two or three times  
the external bus frequency. At two times the external  
bus frequency the processor operates up to 66 MHz,  
(33-MHz CLK). At three times the external bus  
frequency the processor operates up to 100 MHz  
(33-MHz CLK).  
• On-Chip Memory Management Unit — Address  
management and memory space protection  
mechanisms maintain the integrity of memory in a  
multitasking and virtual memory environment. Both  
memory segmentation and paging are supported.  
• Burst Cycles — Burst transfers allow a new  
double-word to be read from memory on each bus  
clock cycle. This capability is especially useful for  
instruction prefetch and for filling the internal  
cache. Data written from the processor to memory  
can also be burst transfers.  
• Write Buffers — The processor contains four  
write buffers to enhance the performance of  
consecutive writes to memory. The processor can  
continue internal operations after a write to these  
buffers, without waiting for the write to be  
completed on the external bus.  
1
Embedded Write-Back Enhanced IntelDX4™ Processor  
• Bus Backoff — When another bus master needs  
control of the bus during a processor initiated bus  
cycle, the Embedded Write-Back Enhanced  
IntelDX4 processor floats its bus signals, then  
restarts the cycle when the bus becomes available  
again.  
• Stop Clock — The Embedded Write-Back  
Enhanced IntelDX4 processor has a stop clock  
control mechanism that provides two low-power  
states: a Stop Grant state (20–50 mA typical,  
depending on input clock frequency) and a Stop  
Clock state (~600 µA typical, with input clock  
frequency of 0 MHz).  
• Instruction Restart — Programs can continue  
execution following an exception generated by an  
unsuccessful attempt to access memory. This  
feature is important for supporting demand-paged  
virtual memory applications.  
• Auto HALT Power Down — After the execution of  
a HALT instruction, the Embedded Write-Back  
Enhanced IntelDX4 processor issues a normal  
Halt bus cycle and the clock input to the processor  
core is automatically stopped, causing the  
processor to enter the Auto HALT Power Down  
state (20–50 mA typical, depending on input clock  
frequency).  
• Dynamic Bus Sizing — External controllers can  
dynamically alter the effective width of the data  
bus. Bus widths of 8, 16, or 32 bits can be used.  
• Boundary Scan (JTAG) — Boundary Scan  
provides in-circuit testing of components on  
printed circuit boards. The Intel Boundary Scan  
implementation conforms with the IEEE Standard  
Test Access Port and Boundary Scan Architecture.  
• Auto Idle Power Down — This function allows the  
processor to reduce the core frequency to the bus  
frequency when both the core and bus are idle.  
Auto Idle Power Down is software transparent and  
does not affect processor performance. Auto Idle  
Power Down provides an average power savings  
of 10% and is only applicable to clock multiplied  
processors.  
• Enhanced Bus Mode — The definitions of some  
signals have been changed to support write-back  
cache mode.  
Intel’s SL technology provides these features:  
• Intel System Management Mode (SMM) — A  
unique Intel architecture operating mode provides  
a dedicated special purpose interrupt and address  
space that can be used to implement intelligent  
power management and other enhanced functions  
in a manner that is completely transparent to the  
operating system and applications software.  
1.2 Family Members  
Table 1 shows the Embedded Write-Back Enhanced  
IntelDX4 processors and briefly describes their  
characteristics.  
• I/O Restart — An I/O instruction interrupted by a  
System Management Interrupt (SMI#) can  
automatically be restarted following the execution  
of the RSM instruction.  
Table 1. The Embedded Write-Back Enhanced IntelDX4™ Processor Family  
Maximum  
Processor  
Frequency  
Maximum  
External Bus  
Frequency  
Supply Voltage  
Product  
Package  
V
CC  
x80486DX4WB75  
x80486DX4WB100  
x80486DX4WB100  
MHz  
75  
25 MHz  
33 MHz  
33 MHz  
208-Lead SQFP  
208-Lead SQFP  
168-Pin PGA  
3.3 V  
3.3 V  
3.3 V  
100 MHz  
100 MHz  
NOTE: To address the fact that many of the package prefix variables have changed, all package prefix variables  
in this document are now indicated with an "x".  
2
 
Embedded Write-Back Enhanced IntelDX4™ Processor  
2.0 HOW TO USE THIS DOCUMENT  
3.0 PIN DESCRIPTIONS  
For a complete set of documentation related to the  
Embedded  
Write-Back  
Enhanced  
IntelDX4  
3.1 Pin Assignments  
processor, use this document in conjunction with the  
following reference documents:  
The following figures and tables show the pin assign-  
ments of each package type for the Embedded  
Write-Back Enhanced IntelDX4 processor. Tables  
are provided showing the pin differences between  
the Embedded Write-Back Enhanced IntelDX4  
processor and other embedded Intel486 processor  
products.  
• Embedded Intel486™ Processor Family  
Developer’s Manual — Order No. 273021  
• Embedded Intel486™ Processor Hardware  
Reference Manual — Order No. 273025  
• Intel486 Microprocessor Family Programmer’s  
Reference Manual — Order No. 240486  
208-Lead SQFP - Quad Flat Pack  
• Intel Application Note AP-485 — Intel Processor  
Identification with the CPUID Instruction —  
Order No. 241618  
• Figure 2, Package Diagram for 208-Lead SQFP  
Embedded Write-Back Enhanced IntelDX4™  
Processor (pg. 4)  
The information in the reference documents for the  
IntelDX4 processor applies to the Embedded Write-  
Back Enhanced IntelDX4 processor. Some of the  
IntelDX4 processor information is duplicated in this  
document to minimize the dependence on the  
reference documents.  
• Table 2, Pinout Differences for 208-Lead SQFP  
Package (pg. 5)  
• Table 3, Pin Assignment for 208-Lead SQFP  
Package (pg. 6)  
• Table 4, Pin Cross Reference for 208-Lead SQFP  
Package (pg. 8)  
168-Pin PGA - Pin Grid Array  
• Figure 3, Package Diagram for 168-Pin PGA  
Embedded Write-Back Enhanced IntelDX4™  
Processor (pg. 10)  
• Table 5, Pinout Differences for 168-Pin PGA  
Package (pg. 11)  
• Table 6, Pin Assignment for 168-Pin PGA  
Package (pg. 12)  
• Table 7, Pin Cross Reference for 168-Pin PGA  
Package (pg. 14)  
3
Embedded Write-Back Enhanced IntelDX4™ Processor  
V
V
V
1
156  
155  
154  
153  
152  
151  
150  
149  
148  
147  
146  
145  
144  
143  
142  
141  
140  
139  
138  
137  
136  
135  
134  
133  
132  
131  
130  
129  
128  
127  
126  
125  
124  
123  
122  
121  
120  
119  
118  
117  
116  
115  
114  
113  
112  
111  
110  
109  
108  
107  
106  
105  
SS  
CC  
SS  
V
2
CC  
CC5  
V
3
A25  
A26  
A27  
A28  
PCHK#  
BRDY#  
BOFF#  
BS16#  
BS8#  
4
5
6
V
CC  
7
8
A29  
A30  
A31  
V
9
CC  
SS  
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
V
SS  
CLKMUL  
RDY#  
DP0  
D0  
D1  
D2  
D3  
D4  
KEN#  
V
CC  
SS  
V
HOLD  
AHOLD  
TCK  
V
SS  
CC  
V
V
CC  
208-Lead SQFP  
Embedded Write-Back Enhanced  
IntelDX4™ Processor  
V
V
CC  
CC  
V
CC  
V
SS  
V
CC  
V
CC  
SS  
V
CC  
V
V
SS  
CLK  
CC  
V
V
CC  
V
CC  
HLDA  
W/R#  
D5  
V
CC  
D6  
SS  
V
V
CC  
BREQ  
BE0#  
BE1#  
BE2#  
BE3#  
NC  
D7  
Top View  
DP1  
D8  
D9  
V
V
CC  
SS  
V
CC  
SS  
V
V
SS  
M/IO#  
V
CC  
D10  
D11  
D12  
D13  
D/C#  
PWT  
PCD  
V
V
CC  
SS  
V
CC  
SS  
V
V
D14  
CC  
V
D15  
CC  
V
SS  
EADS#  
A20M#  
RESET  
FLUSH#  
INTR  
CC  
V
DP2  
D16  
V
CC  
SS  
V
NMI  
V
SS  
V
SS  
A3230-01  
Figure 2. Package Diagram for 208-Lead SQFP Embedded Write-Back Enhanced IntelDX4™ Processor  
4
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 2. Pinout Differences for 208-Lead SQFP Package  
Embedded  
Intel486™ SX  
Processor  
Embedded  
IntelDX2™  
Processor  
Embedded Write-Back  
Enhanced IntelDX4™  
Processor  
Pin #  
1
3
VCC  
INC  
VCC5  
CLKMUL  
HITM#  
V
CC  
2
11  
INC  
63  
64  
INC  
INC  
INC  
INC  
INC  
INC  
INC  
INC  
WB/WT#  
FERR#  
CACHE#  
INV  
66  
FERR#  
INC  
70  
71  
INC  
72  
IGNNE#  
IGNNE#  
NOTES:  
1. This pin location is for the VCC5 pin on the embedded IntelDX4 processor. For compatibility with 3.3V processors that  
have 5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this pin should be connected to a VCC trace, not to  
the VCC plane.  
2. INC. Internal No Connect. These pins are not connected to any internal pad. However, signals are defined for the loca-  
tion of the INC pins in the embedded IntelDX4 processor. One system design can accommodate any one of these pro-  
cessors provided the purpose of each INC pin is understood before it is used.  
5
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 1 of 2)  
Pin#  
1
Description  
Pin#  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
Description  
Pin#  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
Description  
Pin#  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
191  
Description  
VSS  
VSS  
VSS  
VSS  
A24  
A23  
A22  
A21  
2
V
V
V
CC  
CC  
CC  
3
V
VSS  
VSS  
D16  
DP2  
VSS  
5
CC  
4
PCHK#  
BRDY#  
BOFF#  
BS16#  
BS8#  
V
CC  
5
VSS  
6
SRESET  
SMIACT#  
V
CC  
CC  
7
V
V
CC  
8
D15  
D14  
A20  
A19  
A18  
TMS  
TDI  
V
CC  
9
V
VSS  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
VSS  
CLKMUL  
RDY#  
V
V
CC  
CC  
HITM#  
WB/WT#  
SMI#  
VSS  
D13  
D12  
D11  
D10  
VSS  
KEN#  
V
CC  
V
FERR#  
NC1  
VSS  
A17  
CC  
VSS  
HOLD  
AHOLD  
TCK  
TDO  
V
CC  
V
A16  
A15  
VSS  
V
CC  
CC  
CACHE#  
INV  
VSS  
D9  
V
V
CC  
CC  
IGNNE#  
STPCLK#  
D31  
D8  
V
CC  
VSS  
DP1  
D7  
A14  
A13  
V
CC  
V
D30  
NC1  
V
CC  
CC  
CLK  
VSS  
V
A12  
VSS  
A11  
CC  
V
D6  
D5  
V
CC  
CC  
HLDA  
W/R#  
VSS  
D29  
D28  
V
V
CC  
CC  
V
VSS  
VSS  
CC  
V
VSS  
V
V
CC  
CC  
CC  
CC  
BREQ  
BE0#  
BE1#  
BE2#  
BE3#  
V
A10  
A9  
V
CC  
D27  
D26  
D25  
VSS  
V
V
CC  
CC  
V
VSS  
A8  
CC  
VSS  
V
CC  
V
D24  
V
V
CC  
CC  
CC  
6
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 2 of 2)  
Pin#  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
Description  
VSS  
Pin#  
88  
Description  
Pin#  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
Description  
Pin#  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
202  
203  
204  
205  
206  
207  
208  
Description  
VSS  
D4  
D3  
A7  
M/IO#  
89  
A6  
V
CC  
V
90  
DP3  
D23  
D22  
D21  
VSS  
D2  
RESERVED#  
CC  
D/C#  
PWT  
PCD  
91  
D1  
A5  
A4  
A3  
92  
D0  
93  
DP0  
VSS  
A31  
A30  
A29  
V
94  
V
CC  
CC  
VSS  
95  
VSS  
V
CC  
NC1  
VSS  
V
96  
V
CC  
CC  
V
97  
VSS  
A2  
CC  
EADS#  
A20M#  
RESET  
FLUSH#  
INTR  
98  
V
V
CC  
CC  
99  
D20  
D19  
D18  
A28  
A27  
A26  
A25  
ADS#  
BLAST#  
100  
101  
102  
103  
104  
V
CC  
V
PLOCK#  
LOCK#  
VSS  
CC  
NMI  
D17  
VSS  
V
CC  
VSS  
VSS  
NOTE:  
1. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to VCC, or VSS or to any other  
signal can result in component malfunction or incompatibility with future steppings of the Intel486 processors.  
7
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 1 of 2)  
Address  
A2  
Pin #  
202  
197  
196  
195  
193  
192  
190  
187  
186  
182  
180  
178  
177  
174  
173  
171  
166  
165  
164  
161  
160  
159  
158  
154  
153  
152  
151  
149  
148  
147  
Data  
D0  
Pin #  
144  
143  
142  
141  
140  
130  
129  
126  
124  
123  
119  
118  
117  
116  
113  
112  
108  
103  
101  
100  
99  
Control  
A20M#  
ADS#  
AHOLD  
BE0#  
Pin #  
47  
203  
17  
31  
32  
33  
34  
204  
6
NC  
67  
VCC5  
VCC  
2
VSS  
1
3
A3  
D1  
96  
9
10  
A4  
D2  
127  
14  
19  
20  
22  
23  
25  
29  
35  
38  
42  
44  
45  
54  
56  
60  
62  
69  
77  
80  
82  
86  
89  
95  
98  
102  
106  
111  
114  
121  
128  
131  
15  
A5  
D3  
21  
A6  
D4  
BE1#  
28  
A7  
D5  
BE2#  
36  
A8  
D6  
BE3#  
43  
A9  
D7  
BLAST#  
BOFF#  
BRDY#  
BREQ  
BS16#  
BS8#  
52  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
D8  
53  
D9  
5
55  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
D19  
D20  
D21  
D22  
D23  
D24  
D25  
D26  
D27  
D28  
D29  
D30  
D31  
30  
7
57  
61  
8
76  
CACHE#  
CLK  
70  
24  
11  
39  
145  
125  
109  
90  
46  
66  
49  
63  
26  
16  
72  
50  
71  
13  
207  
37  
81  
88  
CLKMUL  
D/C#  
94  
97  
DP0  
104  
105  
107  
110  
115  
120  
122  
132  
135  
138  
146  
156  
157  
170  
175  
181  
DP1  
DP2  
DP3  
93  
EADS#  
FERR#  
FLUSH#  
HITM#  
HLDA  
HOLD  
IGNNE#  
INTR  
92  
91  
87  
85  
84  
83  
79  
78  
INV  
75  
KEN#  
LOCK#  
M/IO#  
74  
8
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 2 of 2)  
Address  
Pin #  
Data  
Pin #  
Control  
NMI  
Pin #  
51  
NC  
VCC5  
VCC  
133  
134  
136  
137  
139  
150  
155  
162  
163  
169  
172  
176  
179  
183  
185  
188  
191  
198  
200  
205  
VSS  
184  
189  
199  
201  
208  
PCD  
41  
PCHK#  
PLOCK#  
PWT  
4
206  
40  
RDY#  
12  
RESERVED#  
RESET  
SMI#  
194  
48  
65  
SMIACT#  
SRESET  
STPCLK#  
TCK  
59  
58  
73  
18  
TDI  
168  
68  
TDO  
TMS  
167  
64  
WB/WT#  
W/R#  
27  
9
Embedded Write-Back Enhanced IntelDX4™ Processor  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
V
V
V
V
V
V
D9  
DP1  
V
D20  
D19  
D11  
A28  
A27  
D2  
D0  
A31  
SS  
SS  
SS  
CC5  
SS  
SS  
D6  
D7  
SS  
1
2
3
4
5
6
7
1
2
3
4
V
V
D8  
V
V
D22  
D21  
D18  
CLK  
D13  
D17  
D3  
V
A25  
VCC  
VSS  
A26  
D1  
A29  
A30  
D5  
CC  
CC  
CC  
SS  
CC  
V
D15  
D12  
D4  
DP0  
A17  
A19  
TCK  
D23  
DP3  
D24  
D10  
DP2  
D16  
D14  
A23  
SS  
V
V
VOLDET  
SS  
CC  
V
V
A18  
A14  
A21  
A24  
SS  
CC  
5
6
7
V
V
D25  
D27  
CC  
SS  
V
V
A22  
A20  
A15  
A12  
D26  
D28  
D30  
SS  
CC  
168-Pin PGA  
Embedded Write-Back Enhanced  
IntelDX4™ Processor  
D29  
VSS  
D31  
VCC  
V
V
CC  
SS  
8
9
8
V
V
A16  
A13  
CC  
SS  
9
INV  
SMI# SRESET  
VCC  
V
V
CC  
SS  
10  
11  
12  
13  
14  
15  
10  
Pin Side View  
VSS  
V
V
RESERVED#  
A9  
A5  
A7  
A2  
CC  
SS  
11  
12  
13  
SMIACT#  
NC  
V
HITM#  
CACHE#  
A11  
A8  
SS  
A10  
VSS  
A6  
INC WB/WT#  
TDI  
VCC  
A3  
TMS FERR#  
14  
15  
IGNNE# NMI FLUSH# A20M# HOLD KEN# STPCLK# BRDY# BE2#  
D/C# LOCK# HLDA BREQ  
BE0#  
PWT  
V
RDY#  
BE3#  
V
V
V
V
V
V
V
CC  
A4  
INTR  
TDO RESET BS8#  
M/IO#  
W/R#  
PLOCK# BLAST#  
BE1#  
PCD  
CC  
CC  
CC  
CC  
CC  
CC  
16  
17  
16  
17  
V
V
V
V
V
V
SS  
BOFF#  
D
AHOLD EADS# BS16#  
CLKMUL ADS#  
PCHK#  
Q
SS  
SS  
SS  
H
SS  
SS  
SS  
A
B
C
E
F
G
J
K
L
M
N
P
R
S
A3231-01  
Figure 3. Package Diagram for 168-Pin PGA Embedded Write-Back Enhanced IntelDX4™ Processor  
10  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 5. Pinout Differences for 168-Pin PGA Package  
Embedded Write-Back Enhanced  
IntelDX4™ Processor  
Pin #  
Embedded IntelDX2™ Processor  
A10  
A12  
B12  
B13  
J1  
INC  
INC  
INC  
INC  
VCC  
INC  
NC  
INV  
HITM#  
CACHE#  
WB/WT#  
VCC5  
R17  
S4  
CLKMUL  
VOLDET  
11  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 1 of 2)  
Pin #  
A1  
Description  
D20  
Pin #  
D17  
E1  
Description  
BOFF#  
VSS  
Pin #  
P2  
Description  
A29  
A2  
D22  
P3  
A30  
A3  
TCK  
D23  
E2  
V
P15  
P16  
P17  
Q1  
HLDA  
CC  
A4  
E3  
D10  
V
CC  
VSS  
A31  
VSS  
A5  
DP3  
D24  
E15  
E16  
E17  
F1  
HOLD  
A6  
V
CC  
VSS  
VSS  
DP1  
D8  
A7  
Q2  
A8  
D29  
Q3  
A17  
A19  
A21  
A24  
A22  
A20  
A16  
A13  
A9  
VSS  
A9  
F2  
Q4  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
B1  
INV  
F3  
D15  
Q5  
VSS  
F15  
F16  
F17  
G1  
KEN#  
RDY#  
BE3#  
VSS  
Q6  
HITM#  
INC  
Q7  
Q8  
TDI  
Q9  
IGNNE#  
INTR  
AHOLD  
D19  
G2  
V
Q10  
Q11  
Q12  
Q13  
Q14  
Q15  
Q16  
Q17  
R1  
CC  
G3  
D12  
G15  
G16  
G17  
H1  
STPCLK#  
A5  
V
A7  
CC  
VSS  
VSS  
B2  
D21  
A2  
VSS  
B3  
BREQ  
PLOCK#  
PCHK#  
A28  
A25  
VSS  
B4  
H2  
D3  
VSS  
B5  
H3  
DP2  
BRDY#  
B6  
D25  
H15  
H16  
H17  
J1  
B7  
V
V
R2  
CC  
CC  
VSS  
B8  
D31  
R3  
V
CC  
VSS  
B9  
V
V
R4  
CC  
CC5  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
C1  
SMI#  
J2  
D5  
R5  
A18  
V
J3  
D16  
BE2#  
BE1#  
PCD  
VSS  
R6  
V
CC  
CC  
CACHE#  
WB/WT#  
TMS  
J15  
J16  
J17  
K1  
R7  
A15  
R8  
V
V
V
V
CC  
CC  
CC  
CC  
R9  
NMI  
R10  
R11  
R12  
R13  
R14  
R15  
R16  
R17  
TDO  
K2  
V
CC  
EADS#  
D11  
K3  
D14  
A11  
A8  
K15  
K16  
K17  
L1  
BE0#  
C2  
D18  
V
V
CC  
CC  
VSS  
VSS  
D6  
C3  
CLK  
A3  
C4  
V
V
BLAST#  
CLKMUL  
CC  
CC  
C5  
L2  
12  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 2 of 2)  
Pin #  
C6  
Description  
D27  
Pin #  
L3  
Description  
D7  
Pin #  
S1  
Description  
A27  
C7  
D26  
L15  
L16  
L17  
M1  
PWT  
S2  
A26  
C8  
D28  
V
S3  
A23  
CC  
VSS  
VSS  
C9  
D30  
S4  
VOLDET  
A14  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
D1  
SRESET  
RESERVED#  
SMIACT#  
NC  
S5  
VSS  
M2  
V
S6  
CC  
M3  
D4  
S7  
A12  
VSS  
VSS  
VSS  
VSS  
VSS  
M15  
M16  
M17  
N1  
D/C#  
S8  
FERR#  
FLUSH#  
RESET  
BS16#  
D9  
V
S9  
CC  
VSS  
D2  
S10  
S11  
S12  
S13  
S14  
S15  
S16  
S17  
N2  
D1  
N3  
DP0  
LOCK#  
M/IO#  
W/R#  
D0  
A10  
VSS  
D2  
D13  
N15  
N16  
N17  
P1  
D3  
D17  
A6  
A4  
D15  
D16  
A20M#  
BS8#  
ADS#  
13  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 1 of 2)  
Addres  
s
Pin #  
Data  
Pin #  
Control  
Pin #  
NC  
INC  
Vcc5  
Vcc  
Vss  
A2  
Q14  
R15  
S16  
Q12  
S15  
Q13  
R13  
Q11  
S13  
R12  
S7  
D0  
D1  
P1  
N2  
N1  
H2  
M3  
J2  
A20M#  
ADS#  
AHOLD  
BE0#  
D15  
S17  
A17  
K15  
J16  
J15  
F17  
R16  
D17  
H15  
Q15  
C17  
D16  
C3  
C13  
A13  
J1  
B7  
B9  
A7  
A9  
A3  
A4  
D2  
B11  
C4  
A11  
B3  
A5  
D3  
A6  
D4  
BE1#  
C5  
B4  
A7  
D5  
BE2#  
E2  
B5  
A8  
D6  
L2  
L3  
F2  
D1  
E3  
C1  
G3  
D2  
K3  
F3  
J3  
BE3#  
E16  
G2  
E1  
A9  
D7  
BLAST#  
BOFF#  
BRDY#  
BREQ  
BS16#  
BS8#  
E17  
G1  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
D8  
G16  
H16  
K2  
D9  
G17  
H1  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
D19  
D20  
D21  
D22  
D23  
D24  
D25  
D26  
D27  
D28  
D29  
D30  
D31  
Q10  
S5  
K16  
L16  
M2  
H17  
K1  
R7  
CLK  
K17  
L1  
Q9  
CLKMUL  
CACHE#  
D/C#  
R17  
B12  
M15  
N3  
M16  
P16  
R3  
Q3  
L17  
M1  
M17  
P17  
Q2  
R5  
Q4  
D3  
C2  
B1  
A1  
B2  
A2  
A4  
A6  
B6  
C7  
C6  
C8  
A8  
C9  
B8  
DP0  
R6  
Q8  
DP1  
F1  
R8  
Q5  
DP2  
H3  
R9  
Q7  
DP3  
A5  
R10  
R11  
R14  
R4  
S3  
EADS#  
FERR#  
FLUSH#  
HITM#  
HLDA  
HOLD  
IGNNE#  
INTR  
B17  
C14  
C15  
A12  
P15  
E15  
A15  
A16  
A10  
F15  
N15  
N16  
S6  
Q6  
S8  
R2  
S9  
S2  
S10  
S11  
S12  
S14  
S1  
R1  
P2  
P3  
Q1  
INV  
KEN#  
LOCK#  
M/IO#  
14  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 2 of 2)  
Addres  
s
Pin #  
Data  
Pin #  
Control  
Pin #  
NC  
INC  
Vcc5  
Vcc  
Vss  
NMI  
PCD  
B15  
J17  
Q17  
Q16  
L15  
F16  
C11  
C16  
B10  
C12  
C10  
G15  
A3  
PCHK#  
PLOCK#  
PWT  
RDY#  
RESERVED#  
RESET  
SMI#  
SMIACT#  
SRESET  
STPCLK#  
TCK  
TDI  
A14  
B16  
B14  
S4  
TDO  
TMS  
VOLDET  
WB/WT#  
W/R#  
B13  
N17  
15  
Embedded Write-Back Enhanced IntelDX4™ Processor  
3.2 Pin Quick Reference  
The following is a brief pin description. For detailed signal descriptions refer to Appendix A, “Signal Descrip-  
tions,” in the Embedded Intel486™ Processor Family Developer’s Manual, order No. 273021.  
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 1 of 8)  
Symbol  
CLK  
Type  
Name and Function  
I
Clock provides the fundamental timing and internal operating frequency for the  
Embedded Write-Back Enhanced IntelDX4 processor. All external timing  
parameters are specified with respect to the rising edge of CLK.  
ADDRESS BUS  
A31-A4  
A3–A2  
I/O  
O
Address Lines A31–A2, together with the byte enable signals, BE3#–BE0#,  
define the physical area of memory or input/output space accessed. Address lines  
A31–A4 are used to drive addresses into the Embedded Write-Back Enhanced  
IntelDX4 processor to perform cache line invalidation. Input signals must meet  
setup and hold times t22 and t23. A31–A2 are not driven during bus or address  
hold.  
BE3#  
BE2#  
BE1#  
BE0#  
O
O
O
O
Byte Enable signals indicate active bytes during read and write cycles. During the  
first cycle of a cache fill, the external system should assume that all byte enables  
are active. BE3#–BE0# are active LOW and are not driven during bus hold.  
BE3# applies to D31–D24  
BE2# applies to D23–D16  
BE1# applies to D15–D8  
BE0# applies to D7–D0  
DATA BUS  
D31–D0  
I/O  
I/O  
Data Lines. D7–D0 define the least significant byte of the data bus; D31–D24  
define the most significant byte of the data bus. These signals must meet setup  
and hold times t22 and t23 for proper operation on reads. These pins are driven  
during the second and subsequent clocks of write cycles.  
DATA PARITY  
DP3–DP0  
There is one Data Parity pin for each byte of the data bus. Data parity is generated  
on all write data cycles with the same timing as the data driven by the Embedded  
Write-Back Enhanced IntelDX4 processor. Even parity information must be driven  
back into the processor on the data parity pins with the same timing as read  
information to ensure that the correct parity check status is indicated by the  
Embedded Write-Back Enhanced IntelDX4 processor. The signals read on these  
pins do not affect program execution.  
Input signals must meet setup and hold times t22 and t23. DP3–DP0 must be  
connected to VCC through a pull-up resistor in systems that do not use parity.  
DP3–DP0 are active HIGH and are driven during the second and subsequent  
clocks of write cycles.  
PCHK#  
O
Parity Status is driven on the PCHK# pin the clock after ready for read operations.  
The parity status is for data sampled at the end of the previous clock. A parity error  
is indicated by PCHK# being LOW. Parity status is only checked for enabled bytes  
as indicated by the byte enable and bus size signals. PCHK# is valid only in the  
clock immediately after read data is returned to the processor. At all other times  
PCHK# is inactive (HIGH). PCHK# is never floated.  
16  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 2 of 8)  
Symbol  
Type  
Name and Function  
BUS CYCLE DEFINITION  
M/IO#  
D/C#  
O
O
O
Memory/Input-Output, Data/Control and Write/Read lines are the primary bus  
definition signals. These signals are driven valid as the ADS# signal is asserted.  
M/IO#  
D/C#  
W/R#  
Bus Cycle Initiated  
Interrupt Acknowledge  
HALT/Special Cycle (see details below)  
I/O Read  
W/R#  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
I/O Write  
Code Read  
Reserved  
Memory Read  
Memory Write  
HALT/Special Cycle  
BE3# - BE0#  
Cycle Name  
Shutdown  
A4-A2  
000  
1110  
1011  
1011  
HALT  
000  
Stop Grant bus cycle  
100  
LOCK#  
O
O
Bus Lock indicates that the current bus cycle is locked. The Embedded Write-  
Back Enhanced IntelDX4 processor does not allow a bus hold when LOCK# is  
asserted (address holds are allowed). LOCK# goes active in the first clock of the  
first locked bus cycle and goes inactive after the last clock of the last locked bus  
cycle. The last locked cycle ends when Ready is returned. LOCK# is active LOW  
and not driven during bus hold. Locked read cycles are not transformed into cache  
fill cycles when KEN# is returned active.  
PLOCK#  
Pseudo-Lock indicates that the current bus transaction requires more than one  
bus cycle to complete. For the Embedded Write-Back Enhanced IntelDX4  
processor, examples of such operations are segment table descriptor reads (64  
bits) and cache line fills (128 bits). For Intel486 processors with on-chip Floating-  
Point Unit, floating-point long reads and writes (64 bits) also require more than one  
bus cycle to complete.  
The Embedded Write-Back Enhanced IntelDX4 processor drives PLOCK# active  
until the addresses for the last bus cycle of the transaction are driven, regardless of  
whether RDY# or BRDY# have been returned.  
Normally PLOCK# and BLAST# are inverse of each other. However, during the  
first bus cycle of a 64-bit floating-point write (for Intel486 processors with on-chip  
Floating-Point Unit) both PLOCK# and BLAST# are asserted.  
PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be  
sampled only in the clock in which Ready is returned. PLOCK# is active LOW and  
is not driven during bus hold.  
BUS CONTROL  
ADS#  
O
Address Status output indicates that a valid bus cycle definition and address are  
available on the cycle definition lines and address bus. ADS# is driven active in the  
same clock in which the addresses are driven. ADS# is active LOW and not driven  
during bus hold.  
17  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 3 of 8)  
Symbol  
Type  
Name and Function  
RDY#  
I
Non-burst Ready input indicates that the current bus cycle is complete. RDY#  
indicates that the external system has presented valid data on the data pins in  
response to a read or that the external system has accepted data from the  
Embedded Write-Back Enhanced IntelDX4 processor in response to a write. RDY#  
is ignored when the bus is idle and at the end of the first clock of the bus cycle.  
RDY# is active during address hold. Data can be returned to the Embedded Write-  
Back Enhanced IntelDX4 processor while AHOLD is active.  
RDY# is active LOW and is not provided with an internal pull-up resistor. RDY#  
must satisfy setup and hold times t16 and t17 for proper chip operation.  
BURST CONTROL  
BRDY#  
I
Burst Ready input performs the same function during a burst cycle that RDY#  
performs during a non-burst cycle. BRDY# indicates that the external system has  
presented valid data in response to a read or that the external system has  
accepted data in response to a write. BRDY# is ignored when the bus is idle and at  
the end of the first clock in a bus cycle.  
BRDY# is sampled in the second and subsequent clocks of a burst cycle. Data  
presented on the data bus is strobed into the Embedded Write-Back Enhanced  
IntelDX4 processor when BRDY# is sampled active. If RDY# is returned simulta-  
neously with BRDY#, BRDY# is ignored and the burst cycle is prematurely  
aborted.  
BRDY# is active LOW and is provided with a small pull-up resistor. BRDY# must  
satisfy the setup and hold times t16 and t17  
.
BLAST#  
O
I
Burst Last signal indicates that the next time BRDY# is returned, the burst bus  
cycle is complete. BLAST# is active for both burst and non-burst bus cycles.  
BLAST# is active LOW and is not driven during bus hold.  
INTERRUPTS  
RESET  
Reset input forces the Embedded Write-Back Enhanced IntelDX4 processorto  
begin execution at a known state. The processor cannot begin executing instruc-  
tions until at least 1 ms after VCC, and CLK have reached their proper DC and AC  
specifications. The RESET pin must remain active during this time to ensure  
proper processor operation. However, for warm resets, RESET should remain  
active for at least 15 CLK periods. RESET is active HIGH. RESET is asynchronous  
but must meet setup and hold times t20 and t21 for recognition in any specific clock.  
INTR  
I
Maskable Interrupt indicates that an external interrupt has been generated. When  
the internal interrupt flag is set in EFLAGS, active interrupt processing is initiated.  
The Embedded Write-Back Enhanced IntelDX4 processorgenerates two locked  
interrupt acknowledge bus cycles in response to the INTR pin going active. INTR  
must remain active until the interrupt acknowledges have been performed to  
ensure processor recognition of the interrupt.  
INTR is active HIGH and is not provided with an internal pull-down resistor. INTR is  
asynchronous, but must meet setup and hold times t20 and t21 for recognition in  
any specific clock.  
NMI  
I
Non-Maskable Interrupt request signal indicates that an external non-maskable  
interrupt has been generated. NMI is rising-edge sensitive and must be held LOW  
for at least four CLK periods before this rising edge. NMI is not provided with an  
internal pull-down resistor. NMI is asynchronous, but must meet setup and hold  
times t20 and t21 for recognition in any specific clock.  
18  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 4 of 8)  
Symbol  
Type  
Name and Function  
SRESET  
I
Soft Reset pin duplicates all functionality of the RESET pin except that the  
SMBASE register retains its previous value. For soft resets, SRESET must remain  
active for at least 15 CLK periods. SRESET is active HIGH. SRESET is  
asynchronous but must meet setup and hold times t20 and t21 for recognition in any  
specific clock.  
SMI#  
I
System Management Interrupt input invokes System Management Mode (SMM).  
SMI# is a falling-edge triggered signal which forces the Embedded Write-Back  
Enhanced IntelDX4 processorinto SMM at the completion of the current instruction.  
SMI# is recognized on an instruction boundary and at each iteration for repeat  
string instructions. SMI# does not break LOCKed bus cycles and cannot interrupt a  
currently executing SMM. The Embedded Write-Back Enhanced IntelDX4 proces-  
sorlatches the falling edge of one pending SMI# signal while it is executing an  
existing SMI#. The nested SMI# is not recognized until after the execution of a  
Resume (RSM) instruction.  
SMIACT#  
STPCLK#  
O
I
System Management Interrupt Active, an active LOW output, indicates that the  
Embedded Write-Back Enhanced IntelDX4 processoris operating in SMM. It is  
asserted when the processor begins to execute the SMI# state save sequence and  
remains active LOW until the processor executes the last state restore cycle out of  
SMRAM.  
Stop Clock Request input signal indicates a request was made to turn off or  
change the CLK input frequency. When the Embedded Write-Back Enhanced  
IntelDX4 processorrecognizes a STPCLK#, it stops execution on the next  
instruction boundary (unless superseded by a higher priority interrupt), empties all  
internal pipelines and write buffers, and generates a Stop Grant bus cycle.  
STPCLK# is active LOW. STPCLK# must be pulled high via a 10-KW pullup  
resistor. STPCLK# is an asynchronous signal, but must remain active until  
the Embedded Write-Back Enhanced IntelDX4 processor issues the Stop  
Grant bus cycle. STPCLK# may be de-asserted at any time after the  
processor has issued the Stop Grant bus cycle.  
BUS ARBITRATION  
BREQ  
O
Bus Request signal indicates that the Embedded Write-Back Enhanced IntelDX4  
processorhas internally generated a bus request. BREQ is generated whether or  
not the processor is driving the bus. BREQ is active HIGH and is never floated.  
HOLD  
I
Bus Hold Request allows another bus master complete control of the Embedded  
Write-Back Enhanced IntelDX4 processorbus. In response to HOLD going active,  
the processor floats most of its output and input/output pins. HLDA is asserted after  
completing the current bus cycle, burst cycle or sequence of locked cycles. The  
Embedded Write-Back Enhanced IntelDX4 processorremains in this state until  
HOLD is de-asserted. HOLD is active HIGH and is not provided with an internal  
pull-down resistor. HOLD must satisfy setup and hold times t18 and t19 for proper  
operation.  
HLDA  
O
Hold Acknowledge goes active in response to a hold request presented on the  
HOLD pin. HLDA indicates that the Embedded Write-Back Enhanced IntelDX4  
processor has given the bus to another local bus master. HLDA is driven active in  
the same clock that the processor floats its bus. HLDA is driven inactive when  
leaving bus hold. HLDA is active HIGH and remains driven during bus hold.  
19  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 5 of 8)  
Symbol  
Type  
Name and Function  
BOFF#  
I
Backoff input forces the Embedded Write-Back Enhanced IntelDX4 processor to  
float its bus in the next clock. The processor floats all pins normally floated during  
bus hold but HLDA is not asserted in response to BOFF#. BOFF# has higher  
priority than RDY# or BRDY#; if both are returned in the same clock, BOFF# takes  
effect. The Embedded Write-Back Enhanced IntelDX4 processor remains in bus  
hold until BOFF# is negated. If a bus cycle is in progress when BOFF# is asserted  
the cycle is restarted. BOFF# is active LOW and must meet setup and hold times  
t18 and t19 for proper operation.  
CACHE INVALIDATION  
AHOLD  
I
Address Hold request allows another bus master access to the Embedded Write-  
Back Enhanced IntelDX4 processor’s address bus for a cache invalidation cycle.  
The processor stops driving its address bus in the clock following AHOLD going  
active. Only the address bus is floated during address hold, the remainder of the  
bus remains active. AHOLD is active HIGH and is provided with a small internal  
pull-down resistor. For proper operation, AHOLD must meet setup and hold times  
t18 and t19.  
EADS#  
I
External Address - This signal indicates that a valid external address has been  
driven onto the Embedded Write-Back Enhanced IntelDX4 processor address pins.  
This address is used to perform an internal cache invalidation cycle. EADS# is  
active LOW and is provided with an internal pull-up resistor. EADS# must satisfy  
setup and hold times t12 and t13 for proper operation.  
CACHE CONTROL  
KEN#  
I
Cache Enable pin is used to determine whether the current cycle is cacheable.  
When the Embedded Write-Back Enhanced IntelDX4 processorgenerates a cycle  
that can be cached and KEN# is active one clock before RDY# or BRDY# during  
the first transfer of the cycle, the cycle becomes a cache line fill cycle. Returning  
KEN# active one clock before RDY# during the last read in the cache line fill  
causes the line to be placed in the on-chip cache. KEN# is active LOW and is  
provided with a small internal pull-up resistor. KEN# must satisfy setup and hold  
times t14 and t15 for proper operation.  
FLUSH#  
I
Cache Flush input forces the Embedded Write-Back Enhanced IntelDX4  
processorto flush its entire internal cache. FLUSH# is active LOW and need only  
be asserted for one clock. FLUSH# is asynchronous but setup and hold times t20  
and t21 must be met for recognition in any specific clock.  
PAGE CACHEABILITY  
PWT  
PCD  
O
O
Page Write-Through and Page Cache Disable pins reflect the state of the page  
attribute bits, PWT and PCD, in the page table entry, page directory entry or  
control register 3 (CR3) when paging is enabled. When paging is disabled, the  
Embedded Write-Back Enhanced IntelDX4 processorignores the PCD and PWT  
bits and assumes they are zero for the purpose of caching and driving PCD and  
PWT pins. PWT and PCD have the same timing as the cycle definition pins (M/IO#,  
D/C#, and W/R#). PWT and PCD are active HIGH and are not driven during bus  
hold. PCD is masked by the cache disable bit (CD) in Control Register 0.  
20  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 6 of 8)  
Symbol  
Type  
Name and Function  
BUS SIZE CONTROL  
BS16#  
BS8#  
I
I
Bus Size 16 and Bus Size 8 pins (bus sizing pins) cause the Embedded Write-  
Back Enhanced IntelDX4 processor to run multiple bus cycles to complete a  
request from devices that cannot provide or accept 32 bits of data in a single cycle.  
The bus sizing pins are sampled every clock. The processor uses the state of  
these pins in the clock before Ready to determine bus size. These signals are  
active LOW and are provided with internal pull-up resistors. These inputs must  
satisfy setup and hold times t14 and t15 for proper operation.  
ADDRESS MASK  
A20M#  
I
Address Bit 20 Mask pin, when asserted, causes the Embedded Write-Back  
Enhanced IntelDX4 processorto mask physical address bit 20 (A20) before  
performing a lookup to the internal cache or driving a memory cycle on the bus.  
A20M# emulates the address wraparound at 1 Mbyte, which occurs on the 8086  
processor. A20M# is active LOW and should be asserted only when the  
Embedded Write-Back Enhanced IntelDX4 processoris in real mode. This pin is  
asynchronous but should meet setup and hold times t20 and t21 for recognition in  
any specific clock. For proper operation, A20M# should be sampled HIGH at the  
falling edge of RESET.  
TEST ACCESS PORT  
TCK  
I
Test Clock, an input to the Embedded Write-Back Enhanced IntelDX4 processor,  
provides the clocking function required by the JTAG Boundary scan feature. TCK  
is used to clock state information (via TMS) and data (via TDI) into the component  
on the rising edge of TCK. Data is clocked out of the component (via TDO) on the  
falling edge of TCK. TCK is provided with an internal pull-up resistor.  
TDI  
TDO  
TMS  
I
Test Data Input is the serial input used to shift JTAG instructions and data into the  
processor. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and  
SHIFT-DR Test Access Port (TAP) controller states. During all other TAP controller  
states, TDI is a “don’t care.” TDI is provided with an internal pull-up resistor.  
O
I
Test Data Output is the serial output used to shift JTAG instructions and data out  
of the component. TDO is driven on the falling edge of TCK during the SHIFT-IR  
and SHIFT-DR TAP controller states. At all other times TDO is driven to the high  
impedance state.  
Test Mode Select is decoded by the JTAG TAP to select test logic operation. TMS  
is sampled on the rising edge of TCK. To guarantee deterministic behavior of the  
TAP controller, TMS is provided with an internal pull-up resistor.  
NUMERIC ERROR REPORTING  
FERR#  
O
The Floating Point Error pin is driven active when a floating point error occurs.  
FERR# is similar to the ERROR# pin on the Intel387™ Math CoProcessor. FERR#  
is included for compatibility with systems using DOS type floating point error  
reporting. FERR# will not go active if FP errors are masked in FPU register.  
FERR# is active LOW, and is not floated during bus hold.  
21  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 7 of 8)  
Symbol  
Type  
Name and Function  
IGNNE#  
I
When the Ignore Numeric Error pin is asserted the processor will ignore a  
numeric error and continue executing non-control floating point instructions, but  
FERR# will still be activated by the processor. When IGNNE# is de-asserted the  
processor will freeze on a non-control floating point instruction, if a previous  
floating point instruction caused an error. IGNNE# has no effect when the NE bit in  
control register 0 is set. IGNNE# is active LOW and is provided with a small  
internal pull-up resistor. IGNNE# is asynchronous but setup and hold times t20 and  
t21 must be met to ensure recognition on any specific clock.  
WRITE-BACK ENHANCED MODE  
CACHE#  
FLUSH#  
O
I
The CACHE# output indicates internal cacheability on read cycles and burst write-  
back on write cycles. CACHE# is asserted for cacheable reads, cacheable code  
fetches and write-backs. It is driven inactive for non-cacheable reads, I/O cycles,  
special cycles, and write-through cycles.  
Cache FLUSH# is an existing pin that operates differently if the processor is  
configured as Enhanced Bus mode (write-back). FLUSH# causes the processor to  
write back all modified lines and flush (invalidate) the cache. FLUSH# is  
asynchronous, but must meet setup and hold times t20 and t21 for recognition in any  
specific clock.  
HITM#  
INV  
O
The Hit/Miss to a Modified Line pin is a cache coherency protocol pin that is  
driven only in Enhanced Bus mode. When a snoop cycle is run, HITM# indicates  
that the processor contains the snooped line and that the line has been modified.  
Assertion of HITM# implies that the line will be written back in its entirety, unless  
the processor is already in the process of doing a replacement write-back of the  
same line.  
I
The Invalidation Request pin is a cache coherency protocol pin that is used only  
in the Enhanced Bus mode. It is sampled by the processor on EADS#-driven  
snoop cycles. It is necessary to assert this pin to get the effect of the processor  
invalidate cycle on write-through-only lines. INV also invalidates the write-back  
lines. However, if the snooped line is modified, the line will be written back and  
then invalidated. INV must satisfy setup and hold times t12 and t13 for proper  
operation.  
PLOCK#  
SRESET  
O
In the Enhanced bus mode, Pseudo-Lock Output is always driven inactive. In this  
mode, a 64-bit data read (caused by an FP operand access or a segment  
descriptor read) is treated as a multiple cycle read request, which may be a burst  
or a non-burst access based on whether BRDY# or RDY# is returned by the  
system. Because only write-back cycles (caused by snoop write-back or  
replacement write-back) are write burstable, a 64-bit write will be driven out as two  
non-burst bus cycles. BLAST# is asserted during both writes.  
I
For the Embedded Write-Back Enhanced IntelDX4 processor, Soft RESET  
operates similar to other the Intel486 processors. On SRESET, the internal  
SMRAM base register retains its previous value, does not flush, write-back or  
disable the internal cache. Because SRESET is treated as an interrupt, it is  
possible to have a bus cycle while SRESET is asserted. SRESET is serviced only  
on an instruction boundary. SRESET is asynchronous but must meet setup and  
hold times t20 and t21 for recognition in any specific clock.  
22  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 8 of 8)  
Symbol  
Type  
Name and Function  
WB/WT#  
I
The Write-Back/Write-Through pin enables Enhanced Bus mode (write-back  
cache). It also defines a cached line as write-through or write-back. For cache  
configuration, WB/WT# must be valid during RESET and be active for at least two  
clocks before and two clocks after RESET is de-asserted. To define write-back or  
write-through configuration of a line, WB/WT# is sampled in the same clock as the  
first RDY# or BRDY# is returned during a line fill (allocation) cycle.  
CLKMUL, VCC5, AND VOLDET  
CLKMUL  
I
The Clock Multiplier input, defined during device RESET, defines the ratio of  
internal core frequency to external bus frequency. If sampled low, the core  
frequency operates at twice the external bus frequency (speed doubled mode). If  
driven high, speed triple mode is selected. CLKMUL has an internal pull-up speed  
to VCC. A 10-KΩ pullup resistor is recommended when the pin is tied high.  
VCC5  
I
The 5V reference voltage input is the reference voltage for the 5V-tolerant I/O  
buffers. This signal should be connected to +5V ±5% for use with 5V logic. If all  
inputs are from 3V logic, this pin should be connected to 3.3V.  
VOLDET  
O
A Voltage Detect signal allows external system logic to distinguish between a 5V  
Intel486 processor and the 3.3V IntelDX4 processor. This signal is active LOW for  
a 3.3V IntelDX4 processor. This pin is available only on the PGA version of the  
Embedded Write-Back Enhanced IntelDX4 processor.  
RESERVED PINS  
RESERVED#  
I
Reserved is reserved for future use. This pin MUST be connected to an external  
pull-up resistor circuit. The recommended resistor value is 10 kOhms. The pull-up  
resistor must be connected only to the RESERVED# pin. Do not share this  
resistor with other pins requiring pull-ups.  
23  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 9. Output Pins  
Output Signal  
Floated During Floated During  
Name  
Active Level  
During Stop Grant and  
Stop Clock States  
Address Hold  
Bus Hold  
1
BREQ  
HLDA  
HIGH  
HIGH  
LOW  
Previous State  
As per HOLD  
Previous State  
Previous State  
Previous State  
HIGH (inactive)  
HIGH (inactive)  
HIGH (inactive)  
Previous State  
Previous State  
Previous State  
Previous State  
Previous State  
BE3#-BE0#  
PWT, PCD  
W/R#, M/IO#, D/C#  
LOCK#  
•
•
•
•
•
•
•
HIGH  
HIGH/LOW  
LOW  
PLOCK#  
ADS#  
LOW  
LOW  
BLAST#  
PCHK#  
LOW  
LOW  
FERR#  
LOW  
A3-A2  
HIGH  
LOW  
•
•
SMIACT#  
CACHE#  
HITM#  
2
LOW  
•
•
•
•
HIGH  
2
LOW  
HIGH  
VOLDET  
NOTES:  
LOW  
LOW  
1. The term “Previous State” means that the processor maintains the logic level applied to the signal pin just before the pro-  
cessor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.  
2. For the case of snoop cycles (via EADS#) during Stop Grant state, CACHE# and HITM# can go active depending on the  
snoop hit in the internal cache.  
Table 10. Input/Output Pins  
Output Signal  
Floated During  
Address Hold  
Floated During  
Bus Hold  
During Stop Grant and  
Stop Clock States  
Name  
Active Level  
D31-D0  
DP3–DP0  
A31-A4  
HIGH  
HIGH  
HIGH  
•
•
•
Floated  
Floated  
•
Previous State  
NOTE:  
The term “Previous State” means that the processor maintains the logic level applied to the signal pin just before the  
processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.  
24  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 11. Test Pins  
Name  
TCK  
TDI  
Input or Output  
Input  
Sampled/ Driven On  
N/A  
Input  
Rising Edge of TCK  
Failing Edge of TCK  
Rising Edge of TCK  
TDO  
TMS  
Output  
Input  
Table 12. Input Pins (Sheet 1 of 2)  
Synchronous/  
Asynchronous  
Internal Pull-Up/  
Name  
Active Level  
Pull-Down  
CLK  
RESET  
SRESET  
HOLD  
HIGH  
HIGH  
HIGH  
HIGH  
LOW  
LOW  
LOW  
LOW  
LOW  
LOW  
LOW  
LOW  
HIGH  
HIGH  
LOW  
LOW  
LOW  
LOW  
HIGH  
Asynchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Asynchronous  
Asynchronous  
Asynchronous  
Asynchronous  
Asynchronous  
Synchronous  
Pull-Down  
AHOLD  
EADS#  
BOFF#  
FLUSH#  
A20M#  
BS16#, BS8#  
KEN#  
Pull-Down  
Pull-Up  
Pull-Up  
Pull-Up  
Pull-Up  
Pull-Up  
Pull-Up  
RDY#  
BRDY#  
INTR  
Pull-Up  
NMI  
IGNNE#  
RESERVED#  
SMI#  
Pull-Up  
Pull-Up  
Pull-Up  
Pull-Up1  
Pull-Up  
STPCLK#  
INV  
NOTE:  
1. Even though STPCLK# and CLKMUL have internal pull-up resistors, they cannot be left floating. An external 10-KΩ pull-  
up resistor is needed if the STPCLK# pin is unused. CLKMUL must be driven to a valid logic level. If tied HIGH, an external  
10-KΩ pull-up resistor is recommended.  
25  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 12. Input Pins (Sheet 2 of 2)  
Synchronous/  
Asynchronous  
Internal Pull-Up/  
Pull-Down  
Name  
Active Level  
WB/WT#  
CLKMUL  
TCK  
HIGH/LOW  
HIGH  
Synchronous  
Pull-Down  
Pull-Up1  
Pull-Up  
HIGH  
TDI  
HIGH  
Pull-Up  
TMS  
HIGH  
Pull-Up  
NOTE:  
1. Even though STPCLK# and CLKMUL have internal pull-up resistors, they cannot be left floating. An external 10-KΩ pull-  
up resistor is needed if the STPCLK# pin is unused. CLKMUL must be driven to a valid logic level. If tied HIGH, an external  
10-KΩ pull-up resistor is recommended.  
processor’s ID Flag, which is bit 21 of the EFLAGS  
register. If software can change the value of this flag,  
the CPUID instruction is available. The actual state  
4.0 ARCHITECTURAL AND  
FUNCTIONAL OVERVIEW  
of the ID Flag bit is irrelevant and provides no signifi-  
The Embedded Write-Back Enhanced IntelDX4  
cance to the hardware. This bit is cleared (reset to  
processor architecture is essentially the same as the  
zero) upon device reset (RESET or SRESET) for  
IntelDX4 processor. Refer to the Embedded  
compatibility with Intel486 processor designs that do  
Intel486™ Processor Family Developer’s Manual  
not support the CPUID instruction.  
(273021)  
CPUID-instruction details are provided here for the  
The Embedded Write-Back Enhanced IntelDX4  
Embedded  
Write-Back  
Enhanced  
IntelDX4  
processor has one pin reserved for possible future  
use. This pin, an input signal, is called RESERVED#  
and must be connected to a 10-KΩ pull-up resistor.  
The pull-up resistor must be connected only to the  
RESERVED# pin. Do not share this resistor with  
other pins requiring pull-ups.  
processor. Refer to Intel Application Note AP-485  
Intel Processor Identification with the CPUID  
Instruction (Order No. 241618) for a description that  
covers all aspects of the CPUID instruction and how  
it pertains to other Intel processors.  
4.1.1 Operation of the CPUID Instruction  
4.1 CPUID Instruction  
The CPUID instruction requires the software  
developer to pass an input parameter to the  
processor in the EAX register. The processor  
response is returned in registers EAX, EBX, EDX,  
and ECX.  
The Embedded Write-Back Enhanced IntelDX4  
processor supports the CPUID instruction (see Table  
13). Because not all Intel processors support the  
CPUID instruction, a simple test can determine if the  
instruction is supported. The test involves the  
Table 13. CPUID Instruction Description  
Parameter passed in  
EAX  
Processor  
Core Clocks  
OP CODE  
Instruction  
Description  
(Input Value)  
0F A2  
CPUID  
9
14  
9
0
1
Vendor (Intel) ID String  
Processor Identification  
Undefined (Do Not Use)  
> 1  
26  
 
Embedded Write-Back Enhanced IntelDX4™ Processor  
Vendor ID String - When the parameter passed in EAX is 0 (zero), the register values returned upon  
instruction execution are shown in the following table.  
31-------------24  
23-----------16  
15--------------8  
7--------------0  
High Value (= 1)  
EAX  
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 1  
Vendor ID String  
(ASCII  
EBX  
EDX  
ECX  
u (75)  
I (49)  
l (6C)  
n (6E)  
e (65)  
e (65)  
e (65)  
n (6E)  
t (74)  
G (47)  
i (69)  
n (6E)  
Characters)  
The values in EBX, EDX and ECX indicate an Intel processor. When taken in the proper order, they decode to  
the string “GenuineIntel.”  
The state of the WB/WT# input pin is sampled by the processor on the falling edge of the RESET signal. If  
WB/WT# is LOW, the processor is configured to operate in Write-Through/Standard Bus mode. If HIGH, it is  
configured to operate in Write-Back/Enhanced Bus mode. The value of the “Model” field of the processor  
signature register depends on the bus mode for which the processor is configured.  
Processor Identification - When the parameter passed to EAX is 1 (one), the register values returned upon  
instruction execution are:  
31---------------------------14  
(Do Not Use)  
13,12  
0 0  
11----8  
0 1 0 0  
Family  
7----4  
1 0 0 0  
Model  
3----0  
XXXX  
Processor  
Signature for  
Write-Through/Stan-  
dard Bus mode  
EAX  
Intel Reserved  
Processor  
Type  
Stepping  
Processor  
Signature for  
Write-  
(Do Not Use)  
0 0  
0 1 0 0  
Family  
1 0 0 1  
Model  
XXXX  
Intel Reserved  
Processor  
Type  
Stepping  
Back/Enhanced Bus  
mode  
(Intel releases information about stepping numbers as needed)  
31--------------------------------------------------------------------------------------------------0  
Intel Reserved  
(Do Not Use)  
EBX  
ECX  
Intel Reserved  
Intel Reserved  
31----------------------------------------------------------------------------2  
0------------------------------------------------------------------------------0  
1
0
Feature Flags  
EDX  
1
0
VME  
FPU  
27  
Embedded Write-Back Enhanced IntelDX4™ Processor  
4.2 Identification After Reset  
Processor Identification - Upon reset, the EDX register contains the processor signature:  
31---------------------------14  
13,12  
11----8  
7----4  
3----0  
Processor  
Signature for  
Write-Through/Stan-  
dard Bus mode  
EDX  
(Do Not Use)  
0 0  
0 1 0 0  
Family  
1 0 0 0  
Model  
XXXX  
Intel Reserved  
Processor  
Type  
Stepping  
Processor  
Signature for  
Write-  
(Do Not Use)  
0 0  
0 1 0 0  
Family  
1 0 0 1  
Model  
XXXX  
Intel Reserved  
Processor  
Type  
Stepping  
Back/Enhanced Bus  
mode  
(Intel releases information about stepping numbers as needed)  
4.3 Boundary Scan (JTAG)  
4.3.1 Device Identification  
Tables 14 and 15 show the 32-bit code for the Embedded Write-Back Enhanced IntelDX4 processor. This code  
is loaded into the Device Identification Register.  
Table 14. Boundary Scan Component Identification Code (Write-Through/Standard Bus Mode)  
Version  
Part Number  
Mfg ID  
1
009H = Intel  
VCC  
1=3.3 V  
Family  
0100 = Intel486  
CPU Family  
Model  
01000 =  
Embedded Write-  
Back Enhanced  
IntelDX4 processor  
Intel  
Architecture  
Type  
31----28  
XXXX  
27  
1
26-----------21  
000001  
20----17  
0100  
16--------12  
01000  
11------------1  
00000001001  
0
1
(Intel releases information about version numbers as needed)  
Boundary Scan Component Identification Code = x828 8013 (Hex)  
28  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 15. Boundary Scan Component Identification Code (Write-Back/Enhanced Bus Mode)  
Version  
Part Number  
Mfg ID  
1
009H = Intel  
VCC  
1=3.3 V  
Intel  
Architecture  
Type  
Family  
0100 = Intel486  
CPU Family  
Model  
01001 =  
Embedded Write-  
Back Enhanced  
IntelDX4 processor  
31----28  
XXXX  
27  
1
26-----------21  
000001  
20----17  
0100  
16--------12  
01001  
11------------1  
00000001001  
0
1
(Intel releases information about version numbers as needed)  
Boundary Scan Component Identification Code = x828 9013 (Hex)  
4.3.2 Boundary Scan Register Bits and Bit  
Order  
TDO ← A2, A3, A4, A5, RESERVED#, A6,  
A7, A8, A9, A10, A11, A12, A13,  
A14, A15, A16, A17, A18, A19,  
A20, A21, A22, A23, A24, A25,  
A26, A27, A28, A29, A30, A31,  
DP0, D0, D1, D2, D3, D4, D5, D6,  
D7, DP1, D8, D9, D10, D11, D12,  
D13, D14, D15, DP2, D16, D17,  
D18, D19, D20, D21, D22, D23,  
DP3, D24, D25, D26, D27, D28,  
D29, D30, D31, STPCLK#,  
IGNNE#, INV, CACHE#, FERR#,  
The boundary scan register contains a cell for each  
pin as well as cells for control of bidirectional and  
three-state pins. There are “Reserved” bits which  
correspond to no-connect (N/C) signals of the  
Embedded  
Write-Back  
Enhanced  
IntelDX4  
processor. Control registers WRCTL, ABUSCTL,  
BUSCTL, and MISCCTL are used to select the  
direction of bidirectional or three-state output signal  
pins. A “1” in these cells designates that the  
associated bus or bits are floated if the pins are  
three-state, or selected as input if they are bidirec-  
tional.  
SMI#,  
SMIACT#, SRESET, NMI, INTR,  
FLUSH#, RESET, A20M#,  
WB/WT#,  
HITM#,  
• WRCTL controls D31-D0 and DP3–DP0  
• ABUSCTL controls A31-A2  
EADS#, PCD, PWT, D/C#, M/IO#,  
BE3#, BE2#, BE1#, BE0#, BREQ,  
W/R#, HLDA, CLK, AHOLD,  
HOLD, KEN#, RDY#, CLKMUL,  
BS8#, BS16#, BOFF#, BRDY#,  
• BUSCTL controls ADS#, BLAST#, PLOCK#,  
LOCK#, W/R#, BE0#, BE1#, BE2#, BE3#, M/IO#,  
D/C#, PWT, PCD, and CACHE#  
• MISCCTL controls PCHK#, HLDA, BREQ, and  
HITM#  
PCHK#,  
LOCK#,  
PLOCK#,  
BLAST#,  
BUSCTL, ABUSCTL, WRCTL  
ADS#,  
MISCCTL,  
The following is the bit order of the Embedded Write-  
Back Enhanced IntelDX4 processor boundary scan  
register:  
← TDI  
29  
Embedded Write-Back Enhanced IntelDX4™ Processor  
5.0 ELECTRICAL SPECIFICATIONS  
5.1 Maximum Ratings  
5.2 DC Specifications  
The following tables show the operating supply  
voltages, DC I/O specifications, and component  
power consumption for the Embedded Write-Back  
Enhanced IntelDX4 processor.  
Table 16 is a stress rating only. Extended exposure  
to the Maximum Ratings may affect device reliability.  
Table 17. Operating Supply Voltages  
Furthermore, although the Embedded Write-Back  
Enhanced IntelDX4 processorcontains protective  
circuitry to resist damage from electrostatic  
discharge, always take precautions to avoid high  
static voltages or electric fields.  
Product  
VCC  
x80486DX4WB75  
x80486DX4WB100  
x0486DX4WB100  
3.3 V ± 0.3 V  
3.3 V ± 0.3 V  
3.3 V ± 0.3 V  
Functional operating conditions are given in Section  
5.2, DC Specifications and Section 5.3, AC Speci-  
fications.  
NOTE: To address the fact that many of the package prefix  
variables have changed, all package prefix variables  
in this document are now indicated with an "x".  
Table 16. Absolute Maximum Ratings  
Case Temperature under  
Bias  
-65 °C to +110 °C  
Storage Temperature  
-65 °C to +150 °C  
DC Voltage on Any Pin with  
Respect to Ground  
-0.5 V to VCC5 + 0.5 V  
Supply Voltage V  
Respect to VSS  
with  
-0.5 V to +4.6 V  
-0.5 V to +6.5 V  
The lesser of:  
CC  
Reference Voltage VCC5 with  
Respect to VSS  
Transient Voltage on any  
Input  
VCC5 + 1.6 V  
or  
6.5 V  
Current Sink on VCC5  
55 mA  
30  
 
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 18. DC Specifications  
Functional Operating Range: VCC = 3.3 V ± 0.3 V; VCC5 = 5 V ± 0.25 V (Note 1); TCASE=0 °C to +85 °C  
Symbol  
VIL  
Parameter  
Input LOW Voltage  
Min.  
-0.3  
Typ.  
Max.  
+0.8  
Unit  
V
Notes  
VIH  
Input HIGH Voltage  
2.0  
VCC5 +0.3  
VCC5 +0.3  
V
Note 2  
VIHC  
VOL  
Input HIGH Voltage of CLK  
Output LOW Voltage  
VCC5 -0.6  
V
I
I
I
I
OL = 4.0 mA (Address, Data, BEn)  
OL = 5.0 mA (Definition, Control)  
OL = 2.0 mA  
0.45  
0.45  
0.40  
0.20  
V
V
V
V
OL = 100 µA  
VOH  
Output HIGH Voltage  
OH = -2.0 mA  
I
2.4  
V
ICC5  
ILI  
VCC5 Leakage Current  
Input Leakage Current  
15  
300  
15  
µA  
µA  
Note 3  
Note 4  
IIH  
Input Leakage Current  
SRESET  
200  
300  
µA  
µA  
Note 5  
Note 5  
IIL  
ILO  
Input Leakage Current  
Output Leakage Current  
Input Capacitance  
400  
15  
10  
14  
12  
µA  
µA  
pF  
pF  
pF  
Note 6  
CIN  
Note 7  
Note 7  
Note 7  
COUT  
CCLK  
NOTES:  
I/O or Output Capacitance  
CLK Capacitance  
1.  
VCC5 should be connected to 3.3 V ± 0.3 V in 3.3 V-only systems.  
2. All inputs except CLK.  
3. This parameter is for inputs without pull-up or pull-down resistors and 0V ≤ VIN ≤ VCC  
4. This parameter is for VCC5 – VCC ≤ 2.25 V. Typical value is not 100% tested.  
5. This parameter is for inputs with pull-down resistors and VIH = 2.4V.  
6. This parameter is for inputs with pull-up resistors and VIL = 0.4V.  
.
7. F =1 MHz. Not 100% tested.  
C
31  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 19. ICC Values  
Functional Operating Range: VCC = 3.3 V ±0.3 V; VCC5 = 5 V ± 0.25 V (Note 1); TCASE = 0°C to +85°C  
Operating  
Parameter  
CC Active  
Frequency  
Typ.  
Maximum  
Notes  
I
75 MHz  
100 MHz  
1100 mA  
1450 mA  
Note 2  
(Power Supply)  
I
CC Active  
75 MHz  
100 MHz  
825 mA  
1075 mA  
975 mA  
1300 mA  
Notes 3, 4, 5  
Note 6  
(Thermal Design)  
ICC Stop Grant  
75 MHz  
100 MHz  
20 mA  
50 mA  
75 mA  
100 mA  
ICC Stop Clock  
0 MHz  
600 µA  
2 mA  
Note 7  
NOTES:  
1. VCC5 should be connected to 3.3 V ± 0.3 V in 3.3 V-only systems.  
2. This parameter is for proper power supply selection. It is measured using the worst case instruction mix at VCC = 3.6V.  
3. The maximum current column is for thermal design power dissipation. It is measured using the worst case instruction mix  
at VCC = 3.3V.  
4. The typical current column is the typical operating current in a system. This value is measured in a system using a typical  
device at VCC = 3.3V, running Microsoft Windows 3.1 at an idle condition. This typical value is dependent upon the specific  
system configuration.  
5. Typical values are not 100% tested.  
6. The ICC Stop Grant specification refers to the ICC value once the Embedded Write-Back Enhanced IntelDX4 processor  
enters the Stop Grant or Auto HALT Power Down state.  
7. The ICC Stop Clock specification refers to the ICC value once the Embedded Write-Back Enhanced IntelDX4 processor  
enters the Stop Clock state. The VIH and VIL levels must be equal to VCC and 0 V, respectively, in order to meet the ICC  
Stop Clock specifications.  
32  
Embedded Write-Back Enhanced IntelDX4™ Processor  
5.3 AC Specifications  
The AC specifications for the Embedded Write-Back Enhanced IntelDX4 processor are given in this section.  
Table 20. AC Characteristics  
VCC = 3.3 V ± 0.3 V; VCC5 = 5 V ± 0.25 V (Note 1)  
CASE = 0°C to +85°C; CL = 50pF, unless otherwise specified. (Sheet 1 of 2)  
T
Product  
WB75  
WB100  
Symbol  
Parameter  
Min Max Min Max  
Unit  
MHz  
ns  
Figure  
Notes  
CLK Frequency  
CLK Period  
8
25  
8
33  
Note 2  
t1  
40  
125  
30  
125  
4
4
t1a  
CLK Period Stability  
±250  
±250  
ps  
Adjacent  
clocks  
Note 3  
at 2V  
t2  
t3  
t4  
t5  
t6  
CLK High Time  
CLK Low Time  
CLK Fall Time  
CLK Rise Time  
14  
14  
11  
11  
ns  
ns  
ns  
ns  
ns  
4
4
4
4
8
at 0.8V  
4
4
3
3
2V to 0.8V  
0.8V to 2V  
A31–A2, PWT, PCD, BE3–BE0#,  
M/IO#, D/C#, W/R#, ADS#, LOCK#,  
FERR#, CACHE#, HITM#, BREQ,  
HLDA Valid Delay  
3
19  
3
14  
t7  
A31–A2, PWT, PCD, BE3–BE0#,  
M/IO#, D/C#, W/R#, ADS#, LOCK#,  
CACHE# Float Delay  
28  
20  
ns  
9
Note 3  
t8  
PCHK# Valid Delay  
3
3
24  
24  
3
3
14  
14  
ns  
ns  
7
8
t8a  
BLAST#, PLOCK#, SMIACT# Valid  
Delay  
t9  
BLAST#, PLOCK# Float Delay  
28  
20  
20  
14  
ns  
ns  
9
8
Note 3  
Note 3  
t10  
D31–D0, DP3–DP0 Write Data Valid  
Delay  
3
3
t11  
D31–D0, DP3–DP0 Write Data Float  
Delay  
28  
20  
ns  
9
t12  
t13  
t14  
EADS#, INV Setup Time  
EADS#, INV Hold Time  
8
3
8
5
3
5
ns  
ns  
ns  
5
5
5
KEN#, BS16#, BS8#, WB/WT# Setup  
Time  
t15  
KEN#, BS16#, BS8#, WB/WT# Hold  
Time  
3
3
ns  
5
t16  
t17  
RDY#, BRDY# Setup Time  
RDY#, BRDY# Hold Time  
8
3
5
3
ns  
ns  
6
6
33  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 20. AC Characteristics  
VCC = 3.3 V ± 0.3 V; VCC5 = 5 V ± 0.25 V (Note 1)  
CASE = 0°C to +85°C; CL = 50pF, unless otherwise specified. (Sheet 2 of 2)  
T
Product  
WB75  
WB100  
Symbol  
Parameter  
Min Max Min Max  
Unit  
ns  
Figure  
Notes  
t18  
t18a  
t19  
HOLD, AHOLD Setup Time  
BOFF# Setup Time  
8
8
3
8
6
7
3
5
5
5
5
5
ns  
HOLD, AHOLD, BOFF# Hold Time  
ns  
t20  
FLUSH#, A20M#, NMI, INTR, SMI#,  
STPCLK#, SRESET, RESET,  
IGNNE# Setup Time  
ns  
Note 4  
Note 4  
t21  
FLUSH#, A20M#, NMI, INTR, SMI#,  
STPCLK#, SRESET, RESET,  
IGNNE# Hold Time  
3
3
ns  
5
t22  
t23  
D31–D0, DP3–DP0,  
A31–A4 Read Setup Time  
5
3
5
3
ns  
ns  
6
5
D31–D0, DP3–DP0,  
A31–A4 Read Hold Time  
6
5
NOTES:  
1. VCC5 should be connected to 3.3 V ± 0.3 V in 3.3 V-only systems.  
2. 0-MHz operation is guaranteed when the STPCLK# and Stop Grant bus cycle protocol is used.  
3. Not 100% tested, guaranteed by design characterization.  
4. A reset pulse width of 15 CLK cycles is required for warm resets (RESET or SRESET). Power-up resets (cold resets)  
require RESET to be asserted for at least 1 ms after VCC and CLK are stable.  
34  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 21. AC Specifications for the Test Access Port  
CC = 3.3 V ±0.3 V; VCC5 = 5 V ±0.25 V (Note 1)  
TCASE = 0°C to +85°C; CL = 50 pF  
V
Symbol  
Parameter  
Min  
Max  
Unit  
MHz  
ns  
Figure  
Notes  
t24  
t25  
TCK Frequency  
TCK Period  
25  
Note 2  
40  
10  
10  
10  
10  
10  
10  
10  
11  
11  
11  
11  
11  
11  
11  
11  
t26  
TCK High Time  
TCK Low Time  
TCK Rise Time  
TCK Fall Time  
ns  
@ 2.0V  
@ 0.8V  
Note 3  
Note 3  
Note 4  
Note 4  
Note 4  
Note 4  
Note 4  
Note 4  
Note 4  
Note 4  
t27  
ns  
t28  
4
4
ns  
t29  
ns  
t30  
TDI, TMS Setup Time  
8
7
3
ns  
t31  
TDI, TMS Hold Time  
ns  
t32  
TDO Valid Delay  
25  
30  
25  
36  
ns  
t33  
TDO Float Delay  
ns  
t34  
All Outputs (except TDO) Valid Delay  
All Outputs (except TDO) Float Delay  
All Inputs (except TDI, TMS, TCK) Setup Time  
All Inputs (except TDI, TMS, TCK) Hold Time  
3
ns  
t35  
ns  
t36  
8
7
ns  
t37  
ns  
NOTES:  
1.  
VCC5 should be connected to 3.3 V ±0.3 V in 3.3 V-only systems. All inputs and outputs are TTL level.  
2. TCK period ≤ CLK period.  
3. Rise/Fall times are measured between 0.8V and 2.0V. Rise/Fall times can be relaxed by 1 ns per 10-ns increase in TCK  
period.  
4. Parameters t30 – t37 are measured from TCK.  
35  
Embedded Write-Back Enhanced IntelDX4™ Processor  
2.0 V  
2.0 V  
1.5 V  
1.5 V  
0.8 V  
CLK  
0.8 V  
t2  
t3  
t4  
t5  
t1  
tx  
ty  
1.5 V  
tx = input setup times  
ty = input hold times, output float, valid and hold times  
Figure 4. CLK Waveform  
Tx  
Tx  
Tx  
CLK  
t13  
t12  
INV, EADS#  
t14  
t15  
t19  
t21  
t23  
BS8#, BS16#,  
KEN#, WB/WT#  
t18  
t20  
t22  
BOFF#, AHOLD, HOLD  
RESET, FLUSH#,  
A20M#, INTR, NMI, SMI#,  
STPCLK#, SRESET, IGNNE#  
A31-A4  
(READ)  
Figure 5. Input Setup and Hold Timing  
36  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Tx  
T2  
Tx  
CLK  
t16  
t17  
RDY#, BRDY#  
1.5 V  
1.5 V  
t23  
t22  
D31-D0, DP3–DP0  
Figure 6. Input Setup and Hold Timing  
T2  
Tx  
Tx  
Tx  
CLK  
RDY#, BRDY#  
D31-D0  
DP3-DP0  
VALID  
MIN  
t8  
MAX  
VALID  
PCHK#  
Figure 7. PCHK# Valid Delay Timing  
37  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Tx  
Tx  
Tx  
CLK  
MIN  
MAX  
MAX  
MAX  
t6  
A2-A31, PWT, PCD,  
BE0-3#, M/IO#,  
D/C#, W/R#, ADS#,  
VALID n  
VALID n+1  
VALID n+1  
VALID n+1  
LOCK#, BREQ, HLDA,  
FERR#, CACHE#, HITM#  
MIN  
t10  
D31-D0, DP3–DP0  
VALID n  
MIN  
t8a  
SMIACT#, BLAST#,  
PLOCK#  
VALID n  
Figure 8. Output Valid Delay Timing  
Tx  
Tx  
Tx  
CLK  
MIN  
t7  
t6  
A2-A31, PWT, PCD,  
BE0-3#, M/IO#,  
D/C#, W/R#, ADS#,  
LOCK#, CACHE#  
VALID  
MIN  
MIN  
t10  
t11  
D31-D0, DP3–DP0  
VALID  
t9  
t8a  
BLAST#,  
PLOCK#  
VALID  
Figure 9. Maximum Float Delay Timing  
38  
Embedded Write-Back Enhanced IntelDX4™ Processor  
2.0 V  
2.0 V  
t27  
TCK  
0.8 V  
0.8 V  
t26  
t28  
t29  
t25  
Figure 10. TCK Waveform  
1.5 V  
TCK  
t31  
t30  
TMS  
TDI  
VALID  
t33  
t32  
VALID  
TDO  
OUTPUT  
INPUT  
t35  
t34  
VALID  
t37  
VALID  
t36  
VALID  
Figure 11. Test Signal Timing Diagram  
39  
Embedded Write-Back Enhanced IntelDX4™ Processor  
5.4 Capacitive Derating Curves  
These graphs are the capacitive derating curves for the Embedded Write-Back Enhanced IntelDX4 processor.  
nom+7  
nom+6  
nom+5  
nom+4  
nom+3  
nom+2  
nom+1  
nom  
nom-1  
nom-2  
25  
50  
75  
100  
125  
150  
Capacitive Load (pF)  
Note: This graph will not be linear outside of the capacitive range shown.  
nom = nominal value from the AC Characteristics table.  
A3238-01  
Figure 12. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions  
for a Low-to-High Transition  
nom+5  
nom+4  
nom+3  
nom+2  
nom+1  
nom  
nom-1  
nom-2  
25  
50  
75  
100  
125  
150  
Capacitive Load (pF)  
Note: This graph will not be linear outside of the capacitive range shown.  
nom = nominal value from the AC Characteristics table.  
A3237-01  
Figure 13. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions  
for a High-to-Low Transition  
40  
Embedded Write-Back Enhanced IntelDX4™ Processor  
In a mixed voltage system (processors at 3 volts,  
peripherals at 5 volts), the bus is driven to 5 volts by  
the peripheral logic. Therefore, the processor must  
discharge the capacitance on the bus from 5 volts to  
0 volts, which takes more time than the 3 volts to 0  
volts transition. Inaccurate capacitive derating  
impacts timing margins and may result in system  
failures under certain load conditions.  
When designing for higher loads in mixed voltage  
systems, timing margins should be evaluated based  
on the derating curves shown in Figure 14. For more  
accurate delay prediction, use I/O buffer models.  
Figure 14. Typical Loading Delay versus Load Capacitance in Mixed Voltage System  
41  
Embedded Write-Back Enhanced IntelDX4™ Processor  
6.0 MECHANICAL DATA  
This section describes the packaging dimensions and thermal specifications for the Embedded Write-Back  
Enhanced IntelDX4 processor.  
6.1 Package Dimensions  
30.6 ± 0.25  
28.0 ± 0.10  
25.50 (ref)  
1.14  
(ref)  
.40 Min  
157  
208  
21.20 ± 0.10  
0.13 + 0.12-0.08  
1
156  
0˚ Min  
7˚ Max  
0.60 ± 0.10  
1.30 Ref  
0.50  
Top View  
Metal Heat Spreader  
3.37 ± 0.08  
3.70 Max  
0.13 Min  
0.25 Max  
52  
105  
53  
104  
NOTE: Length measurements same as width measurements  
Tolerance Window for  
Lead Skew from Theoretical  
True Position  
1.76 Max  
0.10 Max  
Units: mm  
A3260-01  
Figure 15. 208-Lead SQFP Package Dimensions  
42  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Figure 16. Principal Dimensions and Data for 168-Pin Grid Array Package  
Table 22. 168-Pin Ceramic PGA Package Dimensions  
Millimeters  
Max  
Inches  
Symbol  
Min  
3.56  
0.64  
2.8  
Notes  
Min  
Max  
Notes  
A
A1  
A2  
A3  
B
4.57  
0.140  
0.025  
0.110  
0.045  
0.017  
1.735  
1.595  
0.090  
0.100  
0.180  
0.045  
0.140  
0.055  
0.020  
1.765  
1.605  
0.110  
0.130  
1.14  
SOLID LID  
SOLID LID  
SOLID LID  
SOLID LID  
3.5  
1.14  
0.43  
44.07  
40.51  
2.29  
2.54  
1.40  
0.51  
D
44.83  
40.77  
2.79  
D1  
e1  
L
3.30  
N
168  
168  
S1  
1.52  
2.54  
0.060  
0.100  
43  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 23. Ceramic PGA Package Dimension Symbols  
Letter or Symbol  
Description of Dimensions  
Distance from seating plane to highest point of body  
Distance between seating plane and base plane (lid)  
Distance from base plane to highest point of body  
Distance from seating plane to bottom of body  
Diameter of terminal lead pin  
A
A1  
A2  
A3  
B
D
Largest overall package dimension of length  
D1  
e1  
L
A body length dimension, outer lead center to outer lead center  
Linear spacing between true lead position centerlines  
Distance from seating plane to end of lead  
S1  
Other body dimension, outer lead center to edge of body  
NOTES:  
1. Controlling dimension: millimeter.  
2. Dimension “e1” (“e”) is non-cumulative.  
3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415–0.0430 inch.  
4. Dimensions “B”, “B1” and “C” are nominal.  
5. Details of Pin 1 identifier are optional.  
Values for θJA and θJC are given in the following  
6.2 Package Thermal Specifications  
tables for each product at its maximum operating  
frequencies. Maximum TA is shown for each product  
operating at its maximum processor frequency (three  
times the CLK frequency). Refer to the Embedded  
Intel486™ Processor Family Developer’s Manual  
(273021) for a description of the methods used to  
measure these characteristics.  
The Embedded Write-Back Enhanced IntelDX4  
processoris specified for operation when the case  
temperature (TC) is within the range of 0°C to 85°C.  
TC may be measured in any environment to  
determine whether the processor is within the  
specified operating range.  
The ambient temperature (TA) can be calculated  
from θJC and θJA from the following equations:  
TJ = TC + P * θJC  
TA = TJ - P * θJA  
TC = TA + P * [θJA - θJC  
]
TA = TC - P * [θJA - θJC  
]
Where TJ, TA, TC equals Junction, Ambient and  
Case Temperature respectively. θJC, θJA equals  
Junction-to-Case and Junction-to-Ambient thermal  
Resistance, respectively. P is defined as Maximum  
Power Consumption.  
44  
Embedded Write-Back Enhanced IntelDX4™ Processor  
Table 24. Thermal Resistance, θJA (°C/W)  
θJA vs. Airflow — ft/min. (m/sec)  
Heat  
Sink  
0
(0)  
200  
(1.01)  
400  
(2.03)  
600  
(3.04)  
800  
(4.06)  
1000  
(5.07)  
Package  
168-Pin PGA  
168-Pin PGA  
No  
Yes  
No  
17.5  
13.5  
12.5  
10.5  
15.0  
8.5  
13.0  
6.5  
11.5  
5.5  
8.5  
4.0  
10.0  
4.5  
9.5  
4.25  
208-Lead SQFP  
208-Lead SQFP  
10.0  
6.5  
9.0  
Yes  
5.0  
Table 25. Thermal Resistance, θJC (°C/W)  
Package  
Heat Sink  
No  
θJC  
2.0  
2.0  
1.2  
0.8  
168-Pin PGA  
168-Pin PGA  
Yes  
208-Lead SQFP  
208-Lead SQFP  
No  
Yes  
Table 26. Maximum Tambient, TA max (°C)  
Airflow — ft/min. (m/sec)  
Freq.  
(MHz)  
0
(0)  
200  
(1.01)  
400  
(2.03)  
600  
(3.04)  
Package  
Heat Sink  
168-Pin PGA  
No  
Yes  
No  
100  
100  
100  
100  
75  
18.5  
35.5  
36.5  
43.5  
29.0  
57.0  
46.0  
60.5  
37.5  
65.5  
50.0  
67.0  
44.0  
70.0  
52.5  
71.0  
168-Pin PGA  
208-Lead SQFP  
208-Lead SQFP  
208-Lead SQFP  
208-Lead SQFP  
Yes  
No  
Yes  
75  
45  
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