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YW80486DX2SC50

型号：

YW80486DX2SC50

品牌：

INTEL[ INTEL ]

页数：

48 页

PDF大小：

1589 K

下载PDF手册
EMBEDDED IntelDX2™ PROCESSOR  
■
■
■
■
■
■
■
Integrated Floating-Point Unit  
Speed-Multiplying Technology  
32-Bit RISC Technology Core  
8-Kbyte Write-Through Cache  
Four Internal Write Buffers  
Burst Bus Cycles  
■
■
■
■
SL Technology  
Data Bus Parity Generation and Checking  
Boundary Scan (JTAG)  
3.3-Volt Processor, 50 MHz, 25 MHz CLK  
— 208-Lead Shrink Quad Flat Pack (SQFP)  
5-Volt Processor, 66 MHz, 33 MHz CLK  
— 168-Pin Pin Grid Array (PGA)  
■
■
Dynamic Bus Sizing for 8- and 16-bit  
Data Bus Devices  
Binary Compatible with Large Software  
Base  
64-Bit Interunit Transfer Bus  
32-Bit Data Bus  
Core  
CLK  
Clock  
Clock  
Multiplier  
32-Bit Data Bus  
Linear Address  
32  
PCD  
PWT  
Bus Interface  
A31-A2  
Base/  
Index  
Bus  
Barrel  
Shifter  
Segmentation  
Unit  
2
Cache Unit  
BE3#- BE0#  
Paging  
Unit  
32  
Address  
Drivers  
20  
Descriptor  
Registers  
Register  
File  
32  
Physical  
Address  
Write Buffers  
4 x 32  
8 Kbyte  
Cache  
32  
32  
Translation  
Lookaside  
Buffer  
Limit and  
Attribute PLA  
D31-D0  
ALU  
Data Bus  
Transceivers  
ADS# W/R# D/C# M/IO#  
PCD PWT RDY# LOCK#  
PLOCK# BOFF# A20M#  
BREQ HOLD HLDA  
RESET SRESET INTR  
NMI SMI# SMIACT#  
FERR# IGNNE#  
Bus Control  
Displacement Bus  
32  
Prefetcher  
Micro-  
Instruction  
STPCLK#  
Request  
Sequencer  
32-Byte Code  
Queue  
BRDY# BLAST#  
BS16# BS8#  
Burst Bus  
Control  
Code  
Stream  
2x16 Bytes  
Control &  
Protection  
Test Unit  
Instruction  
Decode  
Floating  
Point Unit  
Bus Size  
Control  
24  
KEN# FLUSH#  
AHOLD EADS#  
Cache  
Control  
Decoded  
Instruction  
Path  
Floating  
Point  
Register File  
Control  
ROM  
DP3-DP0 PCHK#  
Parity  
Generation  
and Control  
TCK TMS  
TDI TD0  
Boundary  
Scan  
Control  
A3223-01  
Figure 1. Embedded IntelDX2™ Processor Block Diagram  
August 2004  
Order Number: 272770-003  
© INTEL CORPORATION, 2004  
Information in this document is provided in connection with Intel products. No license, express or implied, by  
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in  
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel  
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or  
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright  
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life  
sustaining applications.  
Intel may make changes to specifications and product descriptions at any time, without notice.  
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or  
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or  
incompatibilities arising from future changes to them.  
The Embedded IntelDX2™ processor may contain design defects or errors known as errata which may cause  
the product to deviate from published specifications. Current characterized errata are available on request.  
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your  
product order.  
Copies of documents which have an ordering number and are referenced in this document, or other Intel  
literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.  
Copyright © Intel Corporation, 1997, 2004  
*Third-party brands and names are the property of their respective owners.  
Contents  
EMBEDDED IntelDX2™ PROCESSOR  
1.0 INTRODUCTION ........................................................................................................................................ 1  
1.1 Features ............................................................................................................................................. 1  
1.2 Family Members ................................................................................................................................. 2  
2.0 HOW TO USE THIS DOCUMENT ............................................................................................................. 3  
3.0 PIN DESCRIPTIONS ................................................................................................................................. 3  
3.1 Pin Assignments ................................................................................................................................. 3  
3.2 Pin Quick Reference ......................................................................................................................... 16  
4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW ............................................................................. 25  
4.1 CPUID Instruction ............................................................................................................................. 25  
4.1.1 Operation of the CPUID Instruction ....................................................................................... 25  
4.2 Identification After Reset .................................................................................................................. 26  
4.3 Boundary Scan (JTAG) .................................................................................................................... 26  
4.3.1 Device Identification ............................................................................................................... 26  
4.3.2 Boundary Scan Register Bits and Bit Order ........................................................................... 27  
5.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 28  
5.1 Maximum Ratings ............................................................................................................................. 28  
5.2 DC Specifications ............................................................................................................................. 28  
5.3 AC Specifications ............................................................................................................................. 33  
5.4 Capacitive Derating Curves .............................................................................................................. 39  
6.0 MECHANICAL DATA .............................................................................................................................. 41  
6.1 Package Dimensions ........................................................................................................................ 41  
6.2 Package Thermal Specifications ...................................................................................................... 44  
FIGURES  
Figure 1.  
Figure 2.  
Figure 3.  
Figure 4.  
Figure 5.  
Figure 6.  
Figure 7.  
Figure 8.  
Figure 9.  
Figure 10.  
Figure 11.  
Embedded IntelDX2™ Processor Block Diagram ...................................................................... i  
Package Diagram for 208-Lead SQFP Embedded IntelDX2™ Processor ................................ 4  
Package Diagram for 168-Pin PGA Embedded IntelDX2™ Processor ................................... 10  
CLK Waveform ........................................................................................................................ 35  
Input Setup and Hold Timing ................................................................................................... 35  
Input Setup and Hold Timing ................................................................................................... 36  
PCHK# Valid Delay Timing ...................................................................................................... 36  
Output Valid Delay Timing ....................................................................................................... 37  
Maximum Float Delay Timing .................................................................................................. 37  
TCK Waveform ........................................................................................................................ 38  
Test Signal Timing Diagram .................................................................................................... 38  
iii  
Contents  
Figure 12.  
Figure 13.  
Figure 14.  
Figure 15.  
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions  
for a Low-to-High Transition, 3.3 V Processor .........................................................................39  
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions  
for a High-to-Low Transition, 3.3 V Processor .........................................................................39  
Typical Loading Delay versus Load Capacitance under  
Worst-Case Conditions for a Low-to-High Transition, 5 V Processor ......................................40  
Typical Loading Delay versus Load Capacitance under  
Worst-Case Conditions for a High-to-Low Transition, 5 V Processor ......................................40  
Figure 16.  
Figure 17.  
208-Lead SQFP Package Dimensions .................................................................................... 41  
Principal Dimensions and Data for 168-Pin Pin Grid Array Package .......................................42  
TABLES  
Table 1.  
The Embedded IntelDX2™ Processor Family ............................................................................2  
Pinout Differences for 208-Lead SQFP Package ......................................................................5  
Pin Assignment for 208-Lead SQFP Package ...........................................................................6  
Pin Cross Reference for 208-Lead SQFP Package ...................................................................8  
Pinout Differences for 168-Pin PGA Package .........................................................................11  
Pin Assignment for 168-Pin PGA Package ..............................................................................12  
Pin Cross Reference for 168-Pin PGA Package ......................................................................14  
Embedded IntelDX2™ Processor Pin Descriptions .................................................................16  
Output Pins ..............................................................................................................................23  
Input/Output Pins .....................................................................................................................23  
Test Pins ..................................................................................................................................23  
Input Pins .................................................................................................................................24  
CPUID Instruction Description .................................................................................................25  
Boundary Scan Component Identification Code (3.3 Volt Processor) .....................................26  
Boundary Scan Component Identification Code (5 Volt Processor) ........................................27  
Absolute Maximum Ratings .....................................................................................................28  
Operating Supply Voltages ......................................................................................................28  
3.3 V DC Specifications ...........................................................................................................29  
3.3 V ICC Values ......................................................................................................................30  
5 V DC Specifications ..............................................................................................................31  
5 V ICC Values .........................................................................................................................32  
AC Characteristics ...................................................................................................................33  
AC Specifications for the Test Access Port .............................................................................34  
168-Pin Ceramic PGA Package Dimensions ...........................................................................42  
Ceramic PGA Package Dimension Symbols ...........................................................................43  
Thermal Resistance, θJA (°C/W) .............................................................................................44  
Thermal Resistance, θJC (°C/W) .............................................................................................44  
Maximum Tambient, TA max (°C) ...............................................................................................44  
Table 2.  
Table 3.  
Table 4.  
Table 5.  
Table 6.  
Table 7.  
Table 8.  
Table 9.  
Table 10.  
Table 11.  
Table 12.  
Table 13.  
Table 14.  
Table 15.  
Table 16.  
Table 17.  
Table 18.  
Table 19.  
Table 20.  
Table 21.  
Table 22.  
Table 23.  
Table 24.  
Table 25.  
Table 26.  
Table 27.  
Table 28.  
iv  
Embedded IntelDX2™ Processor  
• Instruction Pipelining — Overlapped instruction  
fetching, decoding, address translation and  
execution.  
1.0 INTRODUCTION  
The embedded IntelDX2™ processor provides high  
performance to 32-bit, embedded applications.  
Designed for applications that need a floating-point  
unit, the processor is ideal for embedded designs  
running DOS*, Microsoft Windows*, OS/2*, or UNIX*  
applications written for the Intel architecture.  
Projects can be completed quickly by utilizing the  
wide range of software tools, utilities, assemblers  
and compilers that are available for desktop  
computer systems. Also, developers can find  
advantages in using existing chipsets and peripheral  
components in their embedded designs.  
• On-Chip Floating-Point Unit — Intel486™  
processors support the 32-, 64-, and 80-bit formats  
specified in IEEE standard 754. The unit is binary  
compatible with the 8087, Intel287™, Intel387™  
coprocessors, and Intel OverDrive® processor.  
• On-Chip Cache with Cache Consistency  
Support — An 8-Kbyte, write-through, internal  
cache is used for both data and instructions.  
Cache hits provide zero wait-state access times  
for data within the cache. Bus activity is tracked to  
detect alterations in the memory represented by  
the internal cache. The internal cache can be  
invalidated or flushed so that an external cache  
controller can maintain cache consistency.  
The embedded IntelDX2 processor is binary  
compatible with the Intel386™ and earlier Intel  
processors. Compared with the Intel386 processor, it  
provides faster execution of many commonly-used  
instructions. It also provides the benefits of an  
integrated, 8-Kbyte, write-through cache for code  
and data. Its data bus can operate in burst mode  
which provides up to 106-Mbyte-per-second  
transfers for cache-line fills and instruction  
prefetches.  
• External Cache Control — Write-back and flush  
controls for an external cache are provided so the  
processor can maintain cache consistency.  
• On-Chip Memory Management Unit — Address  
management and memory space protection  
mechanisms maintain the integrity of memory in a  
multitasking and virtual memory environment. Both  
memory segmentation and paging are supported.  
Intel’s SL technology is incorporated in the  
embedded IntelDX2 processor. Utilizing Intel’s  
System Management Mode (SMM), it enables  
designers to develop energy-efficient systems.  
• Burst Cycles — Burst transfers allow a new  
double-word to be read from memory on each bus  
clock cycle. This capability is especially useful for  
instruction prefetch and for filling the internal  
cache.  
Two component packages are available. A 168-pin  
Pin Grid Array (PGA) is available for 5-Volt designs  
and a 208-lead Shrink Quad Flat Pack (SQFP) is  
available for 3.3-Volt designs.  
• Write Buffers — The processor contains four  
write buffers to enhance the performance of  
consecutive writes to memory. The processor can  
continue internal operations after a write to these  
buffers, without waiting for the write to be  
completed on the external bus.  
The processor operates at twice the external-bus  
frequency. The 5 V processor operates up to 66  
MHz (33-MHz CLK). The 3.3 V processor operates  
up to 50 MHz (25-MHz CLK).  
• Bus Backoff — When another bus master needs  
control of the bus during a processor initiated bus  
cycle, the embedded IntelDX2 processor floats its  
bus signals, then restarts the cycle when the bus  
becomes available again.  
1.1 Features  
• Instruction Restart — Programs can continue  
execution following an exception generated by an  
unsuccessful attempt to access memory. This  
feature is important for supporting demand-paged  
virtual memory applications.  
The embedded IntelDX2 processor offers these  
features:  
• 32-bit RISC-Technology Core — The embedded  
IntelDX2 processor performs a complete set of  
arithmetic and logical operations on 8-, 16-, and  
32-bit data types using a full-width ALU and eight  
general purpose registers.  
• Dynamic Bus Sizing — External controllers can  
dynamically alter the effective width of the data  
bus. Bus widths of 8, 16, or 32 bits can be used.  
• Single Cycle Execution — Many instructions  
execute in a single clock cycle.  
*
Other brands and names are the property of their  
respective owners.  
1
Embedded IntelDX2™ Processor  
• Boundary Scan (JTAG) — Boundary Scan  
provides in-circuit testing of components on  
printed circuit boards. The Intel Boundary Scan  
implementation conforms with the IEEE Standard  
Test Access Port and Boundary Scan Architecture.  
• Auto HALT Power Down — After the execution of  
a HALT instruction, the embedded IntelDX2  
processor issues a normal Halt bus cycle and the  
clock input to the processor core is automatically  
stopped, causing the processor to enter the Auto  
HALT Power Down state (20–45 mA typical,  
depending on input clock frequency).  
Intel’s SL technology provides these features:  
• Intel System Management Mode (SMM) — A  
unique Intel architecture operating mode provides  
a dedicated special purpose interrupt and address  
space that can be used to implement intelligent  
power management and other enhanced functions  
in a manner that is completely transparent to the  
operating system and applications software.  
• Auto Idle Power Down — This function allows the  
processor to reduce the core frequency to the bus  
frequency when both the core and bus are idle.  
Auto Idle Power Down is software transparent and  
does not affect processor performance. Auto Idle  
Power Down provides an average power savings  
of 10% and is only applicable to clock multiplied  
processors.  
• I/O Restart — An I/O instruction interrupted by a  
System Management Interrupt (SMI#) can  
automatically be restarted following the execution  
of the RSM instruction.  
1.2 Family Members  
• Stop Clock — The embedded IntelDX2 processor  
has a stop clock control mechanism that provides  
two low-power states: a Stop Grant state (20–45  
mA typical, depending on input clock frequency)  
and a Stop Clock state (~100-200 µA typical, with  
input clock frequency of 0 MHz).  
Table 1 shows the embedded IntelDX2 processors  
and briefly describes their characteristics.  
Table 1. The Embedded IntelDX2™ Processor Family  
Maximum  
Processor  
Frequency  
Maximum  
External Bus  
Frequency  
Supply Voltage  
Product  
Package  
V
CC  
x80486DX2SC50  
x80486DX2SA66  
3.3 V  
5.0 V  
50 MHz  
66 MHz  
25 MHz  
33 MHz  
208-Lead SQFP  
168-Pin PGA  
NOTE: To address the fact that many of the package prefix variables have changed, all package prefix  
variables in this document are now indicated with an "x".  
2
 
Embedded IntelDX2™ Processor  
2.0 HOW TO USE THIS DOCUMENT  
3.0 PIN DESCRIPTIONS  
For a complete set of documentation related to the  
embedded IntelDX2 processor, use this document in  
conjunction with the following reference documents:  
3.1 Pin Assignments  
The following figures and tables show the pin assign-  
ments of each package type for the embedded  
IntelDX2 processor. Tables are provided showing  
the pin differences between the embedded IntelDX2  
processor and other embedded Intel486 processor  
products.  
• Embedded Intel486™ Processor Family  
Developer’s Manual — Order No. 273021  
• Embedded Intel486™ Processor Hardware  
Reference Manual — Order No. 273025  
• Intel486 Microprocessor Family Programmer’s  
Reference Manual — Order No. 240486  
208-Lead SQFP - Quad Flat Pack  
• Intel Application Note AP-485 — Intel Processor  
Identification with the CPUID Instruction —  
Order No. 241618  
• Figure 2, Package Diagram for 208-Lead SQFP  
Embedded IntelDX2™ Processor (pg. 4)  
• Table 2, Pinout Differences for 208-Lead SQFP  
Package (pg. 5)  
The information in the reference documents for the  
IntelDX2 processor applies to the embedded  
IntelDX2 processor. Some of the IntelDX2 processor  
information is duplicated in this document to  
minimize the dependence on the reference  
documents.  
• Table 3, Pin Assignment for 208-Lead SQFP  
Package (pg. 6)  
• Table 4, Pin Cross Reference for 208-Lead SQFP  
Package (pg. 8)  
168-Pin PGA - Pin Grid Array  
• Figure 3, Package Diagram for 168-Pin PGA  
Embedded IntelDX2™ Processor (pg. 10)  
• Table 5, Pinout Differences for 168-Pin PGA  
Package (pg. 11)  
• Table 6, Pin Assignment for 168-Pin PGA  
Package (pg. 12)  
• Table 7, Pin Cross Reference for 168-Pin PGA  
Package (pg. 14)  
3
Embedded IntelDX2™ Processor  
V
V
V
1
156  
155  
154  
153  
152  
151  
150  
149  
148  
147  
146  
145  
144  
143  
142  
141  
140  
139  
138  
137  
136  
135  
134  
133  
132  
131  
130  
129  
128  
127  
126  
125  
124  
123  
122  
121  
120  
119  
118  
117  
116  
115  
114  
113  
112  
111  
110  
109  
108  
107  
106  
105  
SS  
CC  
SS  
V
2
CC  
CC  
V
3
A25  
A26  
A27  
A28  
PCHK#  
BRDY#  
BOFF#  
BS16#  
BS8#  
4
5
6
V
CC  
7
8
A29  
A30  
A31  
V
9
CC  
SS  
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
V
SS  
INC  
RDY#  
KEN#  
DP0  
D0  
D1  
D2  
D3  
D4  
V
CC  
SS  
V
HOLD  
AHOLD  
TCK  
V
SS  
CC  
V
V
CC  
208-Lead SQFP  
Embedded IntelDX2™ Processor  
V
V
CC  
CC  
V
CC  
V
SS  
V
CC  
V
CC  
SS  
V
CC  
V
V
SS  
CLK  
CC  
V
V
CC  
V
CC  
HLDA  
W/R#  
D5  
V
CC  
D6  
SS  
V
V
CC  
BREQ  
BE0#  
BE1#  
BE2#  
BE3#  
NC  
D7  
Top View  
DP1  
D8  
D9  
V
V
CC  
SS  
V
CC  
SS  
V
V
SS  
M/IO#  
V
CC  
D10  
D11  
D12  
D13  
D/C#  
PWT  
PCD  
V
V
CC  
SS  
V
CC  
SS  
V
V
D14  
CC  
V
D15  
CC  
V
SS  
EADS#  
A20M#  
RESET  
FLUSH#  
INTR  
CC  
V
DP2  
D16  
V
CC  
SS  
V
NMI  
V
SS  
V
SS  
A3227-01  
Figure 2. Package Diagram for 208-Lead SQFP Embedded IntelDX2™ Processor  
4
Embedded IntelDX2™ Processor  
Table 2. Pinout Differences for 208-Lead SQFP Package  
Embedded  
Intel486™ SX  
Processor  
1
Embedded  
IntelDX2™  
Processor  
Embedded Write-Back  
Enhanced IntelDX4™  
Processor  
Pin #  
3
VCC  
VCC5  
V
CC  
2
11  
INC  
INC  
CLKMUL  
HITM#  
INC  
63  
64  
INC  
INC  
INC  
INC  
INC  
INC  
INC  
WB/WT#  
FERR#  
CACHE#  
INV  
66  
FERR#  
INC  
70  
71  
INC  
72  
IGNNE#  
IGNNE#  
NOTES:  
1. This pin location is for the VCC5 pin on the embedded IntelDX4 processor. For compatibility with 3.3V processors that  
have 5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this pin should be connected to a VCC trace, not to  
the VCC plane.  
2. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded IntelDX2 processor. How-  
ever, new signals are defined for the location of the INC pins in the embedded IntelDX4 processor. One system design  
can accommodate any one of these processors provided the purpose of each INC pin is understood before it is used.  
5
Embedded IntelDX2™ Processor  
Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 1 of 2)  
Pin#  
1
Description  
Pin#  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
Description  
Pin#  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
Description  
Pin#  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
191  
Description  
VSS  
VSS  
VSS  
VSS  
A24  
A23  
A22  
A21  
2
V
V
V
CC  
CC  
CC  
1
V
3
VSS  
VSS  
D16  
DP2  
VSS  
CC  
4
PCHK#  
BRDY#  
BOFF#  
BS16#  
BS8#  
V
CC  
5
VSS  
6
SRESET  
SMIACT#  
V
CC  
CC  
7
V
V
CC  
8
D15  
D14  
A20  
A19  
A18  
TMS  
TDI  
V
CC  
9
V
VSS  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
VSS  
V
V
CC  
CC  
INC2  
INC2  
INC2  
VSS  
D13  
D12  
D11  
D10  
VSS  
RDY#  
KEN#  
SMI#  
FERR#  
NC3  
V
CC  
V
VSS  
A17  
CC  
VSS  
HOLD  
AHOLD  
TCK  
TDO  
V
CC  
V
A16  
A15  
VSS  
V
CC  
CC  
INC2  
INC2  
VSS  
D9  
V
CC  
V
IGNNE#  
STPCLK#  
D31  
D8  
V
CC  
CC  
VSS  
DP1  
A14  
A13  
V
D7  
CC  
V
D30  
NC3  
V
CC  
CC  
CLK  
VSS  
V
A12  
VSS  
A11  
CC  
V
D6  
D5  
V
CC  
CC  
HLDA  
W/R#  
VSS  
D29  
D28  
V
V
CC  
CC  
V
VSS  
VSS  
CC  
V
VSS  
V
V
CC  
CC  
CC  
CC  
BREQ  
BE0#  
BE1#  
BE2#  
BE3#  
V
A10  
A9  
V
CC  
D27  
D26  
D25  
VSS  
V
V
CC  
CC  
V
VSS  
A8  
CC  
VSS  
V
CC  
V
D24  
V
V
CC  
CC  
CC  
6
Embedded IntelDX2™ Processor  
Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 2 of 2)  
Pin#  
36  
Description  
VSS  
Pin#  
88  
Description  
Pin#  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
Description  
Pin#  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
202  
203  
204  
205  
206  
207  
208  
Description  
VSS  
D4  
D3  
A7  
37  
M/IO#  
89  
A6  
V
CC  
38  
V
90  
DP3  
D23  
D22  
D21  
VSS  
D2  
RESERVED#  
CC  
39  
D/C#  
PWT  
PCD  
91  
D1  
A5  
A4  
A3  
40  
92  
D0  
41  
93  
DP0  
VSS  
A31  
A30  
A29  
42  
V
94  
V
CC  
CC  
43  
VSS  
95  
VSS  
V
CC  
44  
V
96  
NC3  
V
CC  
CC  
45  
V
97  
VSS  
VSS  
A2  
CC  
46  
EADS#  
A20M#  
RESET  
FLUSH#  
INTR  
98  
V
V
CC  
CC  
47  
99  
D20  
D19  
D18  
A28  
A27  
A26  
A25  
ADS#  
BLAST#  
48  
100  
101  
102  
103  
104  
49  
V
CC  
50  
V
PLOCK#  
LOCK#  
VSS  
CC  
51  
NMI  
D17  
VSS  
V
CC  
52  
VSS  
VSS  
NOTES:  
1. This pin location is for the VCC5 pin on the embedded IntelDX4 processor. For compatibility with 3.3V processors that have  
5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this pin should be connected to a VCC trace, not to the VCC  
plane.  
2. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded IntelDX2 processors. How-  
ever, signals are defined for the location of the INC pins in the IntelDX4 processor. One system design can accommodate  
any one of these processors provided the purpose of each INC pin is understood before it is used.  
3. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to VCC, or VSS or to any other  
signal can result in component malfunction or incompatibility with future steppings of the Intel486 processors.  
7
Embedded IntelDX2™ Processor  
Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 1 of 2)  
Address  
A2  
Pin #  
202  
197  
196  
195  
193  
192  
190  
187  
186  
182  
180  
178  
177  
174  
173  
171  
166  
165  
164  
161  
160  
159  
158  
154  
153  
152  
151  
149  
148  
147  
Data  
D0  
Pin #  
144  
143  
142  
141  
140  
130  
129  
126  
124  
123  
119  
118  
117  
116  
113  
112  
108  
103  
101  
100  
99  
Control  
A20M#  
ADS#  
Pin #  
47  
203  
17  
31  
32  
33  
34  
204  
6
NC  
67  
INC  
11  
63  
64  
70  
71  
VCC  
2
VSS  
1
A3  
D1  
96  
3
10  
A4  
D2  
AHOLD  
BE0#  
127  
9
15  
A5  
D3  
14  
19  
20  
22  
23  
25  
29  
35  
38  
42  
44  
45  
54  
56  
60  
62  
69  
77  
80  
82  
86  
89  
95  
98  
102  
106  
111  
114  
121  
128  
131  
133  
21  
A6  
D4  
BE1#  
28  
A7  
D5  
BE2#  
36  
A8  
D6  
BE3#  
43  
A9  
D7  
BLAST#  
BOFF#  
BRDY#  
BREQ  
BS16#  
BS8#  
52  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
D8  
53  
D9  
5
55  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
D19  
D20  
D21  
D22  
D23  
D24  
D25  
D26  
D27  
D28  
D29  
D30  
D31  
30  
7
57  
61  
8
76  
CLK  
24  
39  
145  
125  
109  
90  
46  
66  
49  
26  
16  
72  
50  
13  
207  
37  
51  
41  
4
81  
D/C#  
88  
DP0  
94  
DP1  
97  
DP2  
104  
105  
107  
110  
115  
120  
122  
132  
135  
138  
146  
156  
157  
170  
175  
181  
184  
189  
DP3  
EADS#  
FERR#  
FLUSH#  
HLDA  
93  
92  
91  
HOLD  
IGNNE#  
INTR  
87  
85  
84  
KEN#  
83  
LOCK#  
M/IO#  
NMI  
79  
78  
75  
PCD  
74  
PCHK#  
PLOCK#  
PWT  
206  
40  
12  
194  
48  
65  
59  
RDY#  
RESERVED#  
RESET  
SMI#  
134  
136  
199  
201  
SMIACT#  
8
Embedded IntelDX2™ Processor  
Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 2 of 2)  
Address  
Pin #  
Data  
Pin #  
Control  
SRESET  
STPCLK#  
TCK  
Pin #  
58  
NC  
INC  
VCC  
137  
139  
150  
155  
162  
163  
169  
172  
176  
179  
183  
185  
188  
191  
198  
200  
205  
VSS  
208  
73  
18  
TDI  
168  
68  
TDO  
TMS  
167  
27  
W/R#  
9
Embedded IntelDX2™ Processor  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
V
V
V
V
V
V
D9  
DP1  
V
D20  
D19  
D11  
A28  
A27  
D2  
D0  
A31  
SS  
SS  
SS  
CC  
SS  
SS  
D6  
D7  
SS  
1
2
3
4
5
6
7
1
2
3
4
V
V
D8  
V
V
D22  
D21  
D18  
CLK  
D13  
D17  
D3  
V
A25  
VCC  
VSS  
A26  
D1  
A29  
A30  
D5  
CC  
CC  
CC  
SS  
CC  
V
D15  
D12  
D4  
DP0  
A17  
A19  
TCK  
D23  
DP3  
D24  
D10  
DP2  
D16  
D14  
A23  
NC  
SS  
V
V
SS  
CC  
V
V
A18  
A14  
A21  
A24  
SS  
CC  
5
6
7
V
V
D25  
D27  
CC  
SS  
V
V
A22  
A20  
A15  
A12  
D26  
D28  
D30  
SS  
CC  
168-Pin PGA  
Embedded IntelDX2™ Processor  
D29  
VSS  
INC  
D31  
VCC  
V
V
CC  
SS  
8
9
8
V
V
A16  
A13  
CC  
SS  
9
SMI# SRESET  
V
V
CC  
SS  
10  
11  
12  
13  
14  
15  
10  
Pin Side View  
VCC  
VSS  
INC  
INC  
TDI  
RESERVED#  
V
V
A9  
A5  
A7  
A2  
CC  
SS  
11  
12  
13  
SMIACT#  
NC  
V
INC  
INC  
A11  
A8  
SS  
A10  
VSS  
A6  
VCC  
A3  
TMS FERR#  
14  
15  
IGNNE# NMI FLUSH# A20M# HOLD KEN# STPCLK# BRDY# BE2#  
D/C# LOCK# HLDA BREQ  
BE0#  
PWT  
V
RDY#  
BE3#  
V
V
V
V
V
V
V
CC  
A4  
INTR  
TDO RESET BS8#  
M/IO#  
W/R#  
PLOCK# BLAST#  
BE1#  
PCD  
CC  
CC  
CC  
CC  
CC  
CC  
16  
17  
16  
17  
V
V
V
V
V
V
SS  
BOFF#  
D
AHOLD EADS# BS16#  
INC  
R
ADS#  
PCHK#  
Q
SS  
SS  
SS  
H
SS  
SS  
SS  
A
B
C
E
F
G
J
K
L
M
N
P
S
A3226-01  
Figure 3. Package Diagram for 168-Pin PGA Embedded IntelDX2™ Processor  
10  
Embedded IntelDX2™ Processor  
Table 5. Pinout Differences for 168-Pin PGA Package  
Embedded Write-Back Enhanced  
IntelDX4™ Processor  
Pin #  
Embedded IntelDX2™ Processor  
A10  
A12  
B12  
B13  
J1  
INC  
INC  
INC  
INC  
VCC  
INC  
NC  
INV  
HITM#  
CACHE#  
WB/WT#  
VCC5  
R17  
S4  
CLKMUL  
VOLDET  
11  
Embedded IntelDX2™ Processor  
Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 1 of 2)  
Pin #  
A1  
Description  
D20  
Pin #  
D17  
E1  
Description  
BOFF#  
VSS  
Pin #  
P2  
Description  
A29  
A2  
D22  
P3  
A30  
A3  
TCK  
E2  
V
P15  
P16  
P17  
Q1  
HLDA  
CC  
A4  
D23  
E3  
D10  
V
CC  
VSS  
A5  
DP3  
E15  
E16  
E17  
F1  
HOLD  
A6  
D24  
V
A31  
VSS  
CC  
VSS  
VSS  
A7  
Q2  
A8  
D29  
VSS  
DP1  
D8  
Q3  
A17  
A19  
A9  
F2  
Q4  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
B1  
INC1  
VSS  
F3  
D15  
Q5  
A21  
F15  
F16  
F17  
G1  
KEN#  
RDY#  
BE3#  
VSS  
Q6  
A24  
INC1  
INC1  
TDI  
Q7  
A22  
Q8  
A20  
Q9  
A16  
IGNNE#  
INTR  
AHOLD  
D19  
G2  
V
Q10  
Q11  
Q12  
Q13  
Q14  
Q15  
Q16  
Q17  
R1  
A13  
CC  
G3  
D12  
A9  
G15  
G16  
G17  
H1  
STPCLK#  
A5  
V
A7  
CC  
VSS  
VSS  
B2  
D21  
A2  
VSS  
B3  
BREQ  
PLOCK#  
PCHK#  
A28  
VSS  
B4  
H2  
D3  
VSS  
B5  
H3  
DP2  
BRDY#  
B6  
D25  
H15  
H16  
H17  
J1  
B7  
V
V
R2  
A25  
CC  
CC  
VSS  
B8  
D31  
R3  
V
CC  
VSS  
B9  
V
V
R4  
CC  
CC  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
SMI#  
J2  
D5  
D16  
R5  
A18  
V
J3  
R6  
V
CC  
CC  
INC1  
INC1  
TMS  
NMI  
J15  
J16  
J17  
K1  
BE2#  
BE1#  
PCD  
VSS  
R7  
A15  
R8  
V
CC  
R9  
V
V
V
CC  
CC  
CC  
R10  
R11  
TDO  
K2  
V
CC  
12  
Embedded IntelDX2™ Processor  
Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 2 of 2)  
Pin #  
B17  
C1  
Description  
EADS#  
D11  
Pin #  
K3  
Description  
D14  
Pin #  
R12  
R13  
R14  
R15  
R16  
R17  
S1  
Description  
A11  
A8  
K15  
K16  
K17  
L1  
BE0#  
C2  
D18  
V
V
CC  
CC  
VSS  
VSS  
D6  
C3  
CLK  
A3  
BLAST#  
INC1  
A27  
C4  
V
V
CC  
CC  
C5  
L2  
C6  
D27  
D26  
L3  
D7  
C7  
L15  
L16  
L17  
M1  
PWT  
S2  
A26  
C8  
D28  
V
S3  
A23  
NC2  
CC  
VSS  
VSS  
C9  
D30  
S4  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
D1  
SRESET  
RESERVED#  
SMIACT#  
NC2  
S5  
A14  
VSS  
M2  
V
S6  
CC  
M3  
D4  
S7  
A12  
VSS  
VSS  
VSS  
VSS  
VSS  
M15  
M16  
M17  
N1  
D/C#  
S8  
FERR#  
FLUSH#  
RESET  
BS16#  
D9  
V
S9  
CC  
VSS  
D2  
S10  
S11  
S12  
S13  
S14  
S15  
S16  
S17  
N2  
D1  
N3  
DP0  
LOCK#  
M/IO#  
W/R#  
D0  
A10  
VSS  
D2  
D13  
N15  
N16  
N17  
P1  
D3  
D17  
A6  
A4  
D15  
D16  
NOTES:  
A20M#  
BS8#  
ADS#  
1. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded  
IntelDX2 processors. However, signals are defined for the location of the INC pins in the IntelDX4  
processor. One system design can accommodate any one of these processors provided the pur-  
pose of each INC pin is understood before it is used.  
2. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to  
VCC, or VSS or to any other signal can result in component malfunction or incompatibility with  
future steppings of the Intel486 processors.  
13  
Embedded IntelDX2™ Processor  
Table 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 1 of 2)  
Address Pin #  
Data  
D0  
Pin #  
P1  
N2  
N1  
H2  
M3  
J2  
Control  
A20M#  
ADS#  
Pin #  
D15  
S17  
A17  
K15  
J16  
J15  
F17  
R16  
D17  
H15  
Q15  
C17  
D16  
C3  
NC  
C13  
S4  
INC  
A10  
A12  
A13  
B12  
B13  
R17  
Vcc  
B7  
Vss  
A7  
A2  
A3  
Q14  
R15  
S16  
Q12  
S15  
Q13  
R13  
Q11  
S13  
R12  
S7  
D1  
B9  
A9  
A4  
D2  
AHOLD  
BE0#  
B11  
C4  
A11  
B3  
A5  
D3  
A6  
D4  
BE1#  
C5  
B4  
A7  
D5  
BE2#  
E2  
B5  
A8  
D6  
L2  
BE3#  
E16  
G2  
E1  
A9  
D7  
L3  
BLAST#  
BOFF#  
BRDY#  
BREQ  
BS16#  
BS8#  
E17  
G1  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
D8  
F2  
D1  
E3  
C1  
G3  
D2  
K3  
F3  
J3  
G16  
H16  
J1  
D9  
G17  
H1  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
D19  
D20  
D21  
D22  
D23  
D24  
D25  
D26  
D27  
D28  
D29  
D30  
D31  
Q10  
S5  
K2  
H17  
K1  
K16  
L16  
M2  
R7  
CLK  
K17  
L1  
Q9  
D/C#  
M15  
N3  
Q3  
DP0  
M16  
P16  
R3  
L17  
M1  
R5  
DP1  
F1  
Q4  
D3  
C2  
B1  
A1  
B2  
A2  
A4  
A6  
B6  
C7  
C6  
C8  
A8  
C9  
B8  
DP2  
H3  
M17  
P17  
Q2  
Q8  
DP3  
A5  
R6  
Q5  
EADS#  
FERR#  
FLUSH#  
HLDA  
B17  
C14  
C15  
P15  
E15  
A15  
A16  
F15  
N15  
N16  
B15  
J17  
Q17  
Q16  
L15  
F16  
C11  
C16  
B10  
C12  
R8  
Q7  
R9  
R4  
S3  
R10  
R11  
R14  
S6  
Q6  
S8  
R2  
HOLD  
IGNNE#  
INTR  
S9  
S2  
S10  
S11  
S12  
S14  
S1  
R1  
KEN#  
P2  
LOCK#  
M/IO#  
NMI  
P3  
Q1  
PCD  
PCHK#  
PLOCK#  
PWT  
RDY#  
RESERVED#  
RESET  
SMI#  
SMIACT#  
14  
Embedded IntelDX2™ Processor  
Table 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 2 of 2)  
Address Pin #  
Data  
Pin #  
Control  
SRESET  
STPCLK#  
TCK  
Pin #  
C10  
G15  
A3  
NC  
INC  
Vcc  
Vss  
TDI  
A14  
B16  
B14  
N17  
TDO  
TMS  
W/R#  
15  
Embedded IntelDX2™ Processor  
3.2 Pin Quick Reference  
The following is a brief pin description. For detailed signal descriptions refer to Appendix A, “Signal Descrip-  
tions,” in the Embedded Intel486™ Processor Family Developer’s Manual, order No. 273021.  
Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 1 of 7)  
Symbol  
CLK  
Type  
Name and Function  
I
Clock provides the fundamental timing and internal operating frequency for the  
embedded IntelDX2 processor. All external timing parameters are specified with  
respect to the rising edge of CLK.  
ADDRESS BUS  
A31-A4  
I/O  
O
Address Lines A31–A2, together with the byte enable signals, BE3#–BE0#,  
define the physical area of memory or input/output space accessed. Address  
lines A31–A4 are used to drive addresses into the embedded IntelDX2 processor  
to perform cache line invalidation. Input signals must meet setup and hold times  
t22 and t23. A31–A2 are not driven during bus or address hold.  
A3–A2  
BE3#  
BE2#  
BE1#  
BE0#  
O
O
O
O
Byte Enable signals indicate active bytes during read and write cycles. During  
the first cycle of a cache fill, the external system should assume that all byte  
enables are active. BE3#–BE0# are active LOW and are not driven during bus  
hold.  
BE3# applies to D31–D24  
BE2# applies to D23–D16  
BE1# applies to D15–D8  
BE0# applies to D7–D0  
DATA BUS  
D31–D0  
I/O  
I/O  
Data Lines. D7–D0 define the least significant byte of the data bus; D31–D24  
define the most significant byte of the data bus. These signals must meet setup  
and hold times t22 and t23 for proper operation on reads. These pins are driven  
during the second and subsequent clocks of write cycles.  
DATA PARITY  
DP3–DP0  
There is one Data Parity pin for each byte of the data bus. Data parity is  
generated on all write data cycles with the same timing as the data driven by the  
embedded IntelDX2 processor. Even parity information must be driven back into  
the processor on the data parity pins with the same timing as read information to  
ensure that the correct parity check status is indicated by the embedded IntelDX2  
processor. The signals read on these pins do not affect program execution.  
Input signals must meet setup and hold times t22 and t23. DP3–DP0 must be  
connected to VCC through a pull-up resistor in systems that do not use parity.  
DP3–DP0 are active HIGH and are driven during the second and subsequent  
clocks of write cycles.  
PCHK#  
O
Parity Status is driven on the PCHK# pin the clock after ready for read  
operations. The parity status is for data sampled at the end of the previous clock.  
A parity error is indicated by PCHK# being LOW. Parity status is only checked for  
enabled bytes as indicated by the byte enable and bus size signals. PCHK# is  
valid only in the clock immediately after read data is returned to the processor. At  
all other times PCHK# is inactive (HIGH). PCHK# is never floated.  
16  
Embedded IntelDX2™ Processor  
Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 2 of 7)  
Symbol  
Type  
Name and Function  
BUS CYCLE DEFINITION  
M/IO#  
D/C#  
O
O
O
Memory/Input-Output, Data/Control and Write/Read lines are the primary bus  
definition signals. These signals are driven valid as the ADS# signal is asserted.  
M/IO#  
D/C#  
W/R#  
Bus Cycle Initiated  
Interrupt Acknowledge  
HALT/Special Cycle (see details below)  
I/O Read  
W/R#  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
I/O Write  
Code Read  
Reserved  
Memory Read  
Memory Write  
HALT/Special Cycle  
Cycle Name  
Shutdown  
BE3# - BE0#  
A4-A2  
000  
1110  
1011  
1011  
HALT  
000  
Stop Grant bus cycle  
100  
LOCK#  
O
O
Bus Lock indicates that the current bus cycle is locked. The embedded IntelDX2  
processor does not allow a bus hold when LOCK# is asserted (address holds are  
allowed). LOCK# goes active in the first clock of the first locked bus cycle and  
goes inactive after the last clock of the last locked bus cycle. The last locked cycle  
ends when Ready is returned. LOCK# is active LOW and not driven during bus  
hold. Locked read cycles are not transformed into cache fill cycles when KEN# is  
returned active.  
PLOCK#  
Pseudo-Lock indicates that the current bus transaction requires more than one  
bus cycle to complete. For the embedded IntelDX2 processor, examples of such  
operations are segment table descriptor reads (64 bits) and cache line fills (128  
bits). For Intel486 processors with on-chip Floating-Point Unit, floating-point long  
reads and writes (64 bits) also require more than one bus cycle to complete.  
The embedded IntelDX2 processor drives PLOCK# active until the addresses for  
the last bus cycle of the transaction are driven, regardless of whether RDY# or  
BRDY# have been returned.  
Normally PLOCK# and BLAST# are inverse of each other. However, during the  
first bus cycle of a 64-bit floating-point write (for Intel486 processors with on-chip  
Floating-Point Unit) both PLOCK# and BLAST# are asserted.  
PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be  
sampled only in the clock in which Ready is returned. PLOCK# is active LOW and  
is not driven during bus hold.  
BUS CONTROL  
ADS#  
O
Address Status output indicates that a valid bus cycle definition and address are  
available on the cycle definition lines and address bus. ADS# is driven active in  
the same clock in which the addresses are driven. ADS# is active LOW and not  
driven during bus hold.  
17  
Embedded IntelDX2™ Processor  
Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 3 of 7)  
Symbol  
Type  
Name and Function  
RDY#  
I
Non-burst Ready input indicates that the current bus cycle is complete. RDY#  
indicates that the external system has presented valid data on the data pins in  
response to a read or that the external system has accepted data from the  
embedded IntelDX2 processor in response to a write. RDY# is ignored when the  
bus is idle and at the end of the first clock of the bus cycle.  
RDY# is active during address hold. Data can be returned to the embedded  
IntelDX2 processor while AHOLD is active.  
RDY# is active LOW and is not provided with an internal pull-up resistor. RDY#  
must satisfy setup and hold times t16 and t17 for proper chip operation.  
BURST CONTROL  
BRDY#  
I
Burst Ready input performs the same function during a burst cycle that RDY#  
performs during a non-burst cycle. BRDY# indicates that the external system has  
presented valid data in response to a read or that the external system has  
accepted data in response to a write. BRDY# is ignored when the bus is idle and  
at the end of the first clock in a bus cycle.  
BRDY# is sampled in the second and subsequent clocks of a burst cycle. Data  
presented on the data bus is strobed into the embedded IntelDX2 processor  
when BRDY# is sampled active. If RDY# is returned simultaneously with BRDY#,  
BRDY# is ignored and the burst cycle is prematurely aborted.  
BRDY# is active LOW and is provided with a small pull-up resistor. BRDY# must  
satisfy the setup and hold times t16 and t17  
.
BLAST#  
O
I
Burst Last signal indicates that the next time BRDY# is returned, the burst bus  
cycle is complete. BLAST# is active for both burst and non-burst bus cycles.  
BLAST# is active LOW and is not driven during bus hold.  
INTERRUPTS  
RESET  
Reset input forces the embedded IntelDX2 processor to begin execution at a  
known state. The processor cannot begin executing instructions until at least  
1 ms after VCC, and CLK have reached their proper DC and AC specifications.  
The RESET pin must remain active during this time to ensure proper processor  
operation. However, for warm resets, RESET should remain active for at least 15  
CLK periods. RESET is active HIGH. RESET is asynchronous but must meet  
setup and hold times t20 and t21 for recognition in any specific clock.  
INTR  
I
Maskable Interrupt indicates that an external interrupt has been generated.  
When the internal interrupt flag is set in EFLAGS, active interrupt processing is  
initiated. The embedded IntelDX2 processor generates two locked interrupt  
acknowledge bus cycles in response to the INTR pin going active. INTR must  
remain active until the interrupt acknowledges have been performed to ensure  
processor recognition of the interrupt.  
INTR is active HIGH and is not provided with an internal pull-down resistor. INTR  
is asynchronous, but must meet setup and hold times t20 and t21 for recognition in  
any specific clock.  
NMI  
I
Non-Maskable Interrupt request signal indicates that an external non-maskable  
interrupt has been generated. NMI is rising-edge sensitive and must be held LOW  
for at least four CLK periods before this rising edge. NMI is not provided with an  
internal pull-down resistor. NMI is asynchronous, but must meet setup and hold  
times t20 and t21 for recognition in any specific clock.  
18  
Embedded IntelDX2™ Processor  
Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 4 of 7)  
Symbol  
Type  
Name and Function  
SRESET  
I
Soft Reset pin duplicates all functionality of the RESET pin except that the  
SMBASE register retains its previous value. For soft resets, SRESET must  
remain active for at least 15 CLK periods. SRESET is active HIGH. SRESET is  
asynchronous but must meet setup and hold times t20 and t21 for recognition in  
any specific clock.  
SMI#  
I
System Management Interrupt input invokes System Management Mode  
(SMM). SMI# is a falling-edge triggered signal which forces the embedded  
IntelDX2 processor into SMM at the completion of the current instruction. SMI# is  
recognized on an instruction boundary and at each iteration for repeat string  
instructions. SMI# does not break LOCKed bus cycles and cannot interrupt a  
currently executing SMM. The embedded IntelDX2 processor latches the falling  
edge of one pending SMI# signal while it is executing an existing SMI#. The  
nested SMI# is not recognized until after the execution of a Resume (RSM)  
instruction.  
SMIACT#  
STPCLK#  
O
I
System Management Interrupt Active, an active LOW output, indicates that the  
embedded IntelDX2 processor is operating in SMM. It is asserted when the  
processor begins to execute the SMI# state save sequence and remains active  
LOW until the processor executes the last state restore cycle out of SMRAM.  
Stop Clock Request input signal indicates a request was made to turn off or  
change the CLK input frequency. When the embedded IntelDX2 processor  
recognizes a STPCLK#, it stops execution on the next instruction boundary  
(unless superseded by a higher priority interrupt), empties all internal pipelines  
and write buffers, and generates a Stop Grant bus cycle. STPCLK# is active  
LOW. Though STPCLK# has an internal pull-up resistor, an external 10-KΩ pull-  
up resistor is needed if the STPCLK# pin is unused. STPCLK# is an  
asynchronous signal, but must remain active until the embedded IntelDX2  
processor issues the Stop Grant bus cycle. STPCLK# may be de-asserted at  
any time after the processor has issued the Stop Grant bus cycle.  
BUS ARBITRATION  
BREQ  
O
Bus Request signal indicates that the embedded IntelDX2 processor has  
internally generated a bus request. BREQ is generated whether or not the  
processor is driving the bus. BREQ is active HIGH and is never floated.  
HOLD  
I
Bus Hold Request allows another bus master complete control of the embedded  
IntelDX2 processor bus. In response to HOLD going active, the processor floats  
most of its output and input/output pins. HLDA is asserted after completing the  
current bus cycle, burst cycle or sequence of locked cycles. The embedded  
IntelDX2 processor remains in this state until HOLD is de-asserted. HOLD is  
active HIGH and is not provided with an internal pull-down resistor. HOLD must  
satisfy setup and hold times t18 and t19 for proper operation.  
HLDA  
O
Hold Acknowledge goes active in response to a hold request presented on the  
HOLD pin. HLDA indicates that the embedded IntelDX2 processor has given the  
bus to another local bus master. HLDA is driven active in the same clock that the  
processor floats its bus. HLDA is driven inactive when leaving bus hold. HLDA is  
active HIGH and remains driven during bus hold.  
19  
Embedded IntelDX2™ Processor  
Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 5 of 7)  
Symbol  
Type  
Name and Function  
BOFF#  
I
Backoff input forces the embedded IntelDX2 processor to float its bus in the next  
clock. The processor floats all pins normally floated during bus hold but HLDA is  
not asserted in response to BOFF#. BOFF# has higher priority than RDY# or  
BRDY#; if both are returned in the same clock, BOFF# takes effect. The  
embedded IntelDX2 processor remains in bus hold until BOFF# is negated. If a  
bus cycle is in progress when BOFF# is asserted the cycle is restarted. BOFF# is  
active LOW and must meet setup and hold times t18 and t19 for proper operation.  
CACHE INVALIDATION  
AHOLD  
I
Address Hold request allows another bus master access to the embedded  
IntelDX2 processor’s address bus for a cache invalidation cycle. The processor  
stops driving its address bus in the clock following AHOLD going active. Only the  
address bus is floated during address hold, the remainder of the bus remains  
active. AHOLD is active HIGH and is provided with a small internal pull-down  
resistor. For proper operation, AHOLD must meet setup and hold times t18 and  
t19.  
EADS#  
I
I
External Address - This signal indicates that a valid external address has been  
driven onto the embedded IntelDX2 processor address pins. This address is used  
to perform an internal cache invalidation cycle. EADS# is active LOW and is  
provided with an internal pull-up resistor. EADS# must satisfy setup and hold  
times t12 and t13 for proper operation.  
CACHE CONTROL  
KEN#  
Cache Enable pin is used to determine whether the current cycle is cacheable.  
When the embedded IntelDX2 processor generates a cycle that can be cached  
and KEN# is active one clock before RDY# or BRDY# during the first transfer of  
the cycle, the cycle becomes a cache line fill cycle. Returning KEN# active one  
clock before RDY# during the last read in the cache line fill causes the line to be  
placed in the on-chip cache. KEN# is active LOW and is provided with a small  
internal pull-up resistor. KEN# must satisfy setup and hold times t14 and t15 for  
proper operation.  
FLUSH#  
I
Cache Flush input forces the embedded IntelDX2 processor to flush its entire  
internal cache. FLUSH# is active LOW and need only be asserted for one clock.  
FLUSH# is asynchronous but setup and hold times t20 and t21 must be met for  
recognition in any specific clock.  
PAGE CACHEABILITY  
PWT  
PCD  
O
O
Page Write-Through and Page Cache Disable pins reflect the state of the page  
attribute bits, PWT and PCD, in the page table entry, page directory entry or  
control register 3 (CR3) when paging is enabled. When paging is disabled, the  
embedded IntelDX2 processor ignores the PCD and PWT bits and assumes they  
are zero for the purpose of caching and driving PCD and PWT pins. PWT and  
PCD have the same timing as the cycle definition pins (M/IO#, D/C#, and W/R#).  
PWT and PCD are active HIGH and are not driven during bus hold. PCD is  
masked by the cache disable bit (CD) in Control Register 0.  
20  
Embedded IntelDX2™ Processor  
Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 6 of 7)  
Symbol  
Type  
Name and Function  
BUS SIZE CONTROL  
BS16#  
BS8#  
I
I
Bus Size 16 and Bus Size 8 pins (bus sizing pins) cause the embedded IntelDX2  
processor to run multiple bus cycles to complete a request from devices that  
cannot provide or accept 32 bits of data in a single cycle. The bus sizing pins are  
sampled every clock. The processor uses the state of these pins in the clock  
before Ready to determine bus size. These signals are active LOW and are  
provided with internal pull-up resistors. These inputs must satisfy setup and hold  
times t14 and t15 for proper operation.  
ADDRESS MASK  
A20M#  
I
Address Bit 20 Mask pin, when asserted, causes the embedded IntelDX2  
processor to mask physical address bit 20 (A20) before performing a lookup to  
the internal cache or driving a memory cycle on the bus. A20M# emulates the  
address wraparound at 1 Mbyte, which occurs on the 8086 processor. A20M# is  
active LOW and should be asserted only when the embedded IntelDX2 processor  
is in real mode. This pin is asynchronous but should meet setup and hold times  
t20 and t21 for recognition in any specific clock. For proper operation, A20M#  
should be sampled HIGH at the falling edge of RESET.  
TEST ACCESS PORT  
TCK  
I
Test Clock, an input to the embedded IntelDX2 processor, provides the clocking  
function required by the JTAG Boundary scan feature. TCK is used to clock state  
information (via TMS) and data (via TDI) into the component on the rising edge of  
TCK. Data is clocked out of the component (via TDO) on the falling edge of TCK.  
TCK is provided with an internal pull-up resistor.  
TDI  
I
Test Data Input is the serial input used to shift JTAG instructions and data into  
the processor. TDI is sampled on the rising edge of TCK, during the SHIFT-IR  
and SHIFT-DR Test Access Port (TAP) controller states. During all other TAP  
controller states, TDI is a “don’t care.” TDI is provided with an internal pull-up  
resistor.  
TDO  
TMS  
O
I
Test Data Output is the serial output used to shift JTAG instructions and data out  
of the component. TDO is driven on the falling edge of TCK during the SHIFT-IR  
and SHIFT-DR TAP controller states. At all other times TDO is driven to the high  
impedance state.  
Test Mode Select is decoded by the JTAG TAP to select test logic operation.  
TMS is sampled on the rising edge of TCK. To guarantee deterministic behavior  
of the TAP controller, TMS is provided with an internal pull-up resistor.  
21  
Embedded IntelDX2™ Processor  
Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 7 of 7)  
Symbol  
Type  
Name and Function  
NUMERIC ERROR REPORTING  
FERR#  
O
The Floating Point Error pin is driven active when a floating point error occurs.  
FERR# is similar to the ERROR# pin on the Intel387™ Math CoProcessor.  
FERR# is included for compatibility with systems using DOS type floating point  
error reporting. FERR# will not go active if FP errors are masked in FPU register.  
FERR# is active LOW, and is not floated during bus hold.  
IGNNE#  
I
When the Ignore Numeric Error pin is asserted the processor will ignore a  
numeric error and continue executing non-control floating point instructions, but  
FERR# will still be activated by the processor. When IGNNE# is de-asserted the  
processor will freeze on a non-control floating point instruction, if a previous  
floating point instruction caused an error. IGNNE# has no effect when the NE bit  
in control register 0 is set. IGNNE# is active LOW and is provided with a small  
internal pull-up resistor. IGNNE# is asynchronous but setup and hold times t20  
and t21 must be met to ensure recognition on any specific clock.  
RESERVED PINS  
RESERVED#  
I
Reserved is reserved for future use. This pin MUST be connected to an external  
pull-up resistor circuit. The recommended resistor value is 10 kOhms. The pull-up  
resistor must be connected only to the RESERVED# pin. Do not share this  
resistor with other pins requiring pull-ups.  
22  
Embedded IntelDX2™ Processor  
Table 9. Output Pins  
Output Signal  
Name  
Active Level  
Floated During Floated During  
During Stop Grant and  
Stop Clock States  
Address Hold  
Bus Hold  
BREQ  
HLDA  
HIGH  
HIGH  
LOW  
Previous State  
As per HOLD  
BE3#-BE0#  
PWT, PCD  
W/R#, M/IO#, D/C#  
LOCK#  
•
•
•
•
•
•
•
Previous State  
Previous State  
Previous State  
HIGH (inactive)  
HIGH (inactive)  
HIGH (inactive)  
Previous State  
Previous State  
Previous State  
Previous State  
Previous State  
HIGH  
HIGH/LOW  
LOW  
PLOCK#  
ADS#  
LOW  
LOW  
BLAST#  
PCHK#  
LOW  
LOW  
FERR#  
LOW  
A3-A2  
HIGH  
LOW  
•
•
SMIACT#  
NOTES: The term “Previous State” means that the processor maintains the logic level applied to the signal pin just before  
the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.  
Table 10. Input/Output Pins  
Output Signal  
Floated During  
Address Hold  
Floated During  
Bus Hold  
During Stop Grant and  
Stop Clock States  
Name  
Active Level  
D31-D0  
DP3–DP0  
A31-A4  
HIGH  
HIGH  
HIGH  
•
•
•
Floated  
Floated  
•
Previous State  
NOTES: The term “Previous State” means that the processor maintains the logic level applied to the signal pin just before the  
processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.  
Table 11. Test Pins  
Name  
TCK  
TDI  
Input or Output  
Input  
Sampled/ Driven On  
N/A  
Input  
Rising Edge of TCK  
Failing Edge of TCK  
Rising Edge of TCK  
TDO  
TMS  
Output  
Input  
23  
Embedded IntelDX2™ Processor  
Table 12. Input Pins  
Synchronous/  
Asynchronous  
Internal Pull-Up/  
Pull-Down  
Name  
Active Level  
CLK  
RESET  
SRESET  
HOLD  
HIGH  
HIGH  
HIGH  
HIGH  
LOW  
LOW  
LOW  
LOW  
LOW  
LOW  
LOW  
LOW  
HIGH  
HIGH  
LOW  
Asynchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Asynchronous  
Asynchronous  
Pull-Down  
AHOLD  
EADS#  
BOFF#  
FLUSH#  
A20M#  
Pull-Down  
Pull-Up  
Pull-Up  
Pull-Up  
Pull-Up  
Pull-Up  
Pull-Up  
BS16#, BS8#  
KEN#  
RDY#  
BRDY#  
INTR  
Pull-Up  
Pull-Up  
NMI  
IGNNE#  
RESERVED#  
SMI#  
LOW  
LOW  
HIGH  
HIGH  
HIGH  
Asynchronous  
Asynchronous  
Pull-Up  
Pull-Up1  
Pull-Up  
Pull-Up  
Pull-Up  
STPCLK#  
TCK  
TDI  
TMS  
NOTES:  
1. Though STPCLK# has an internal pull-up resistor, an external 10-KΩ pull-up resistor is needed if the STPCLK# pin is  
unused.  
24  
Embedded IntelDX2™ Processor  
can change the value of this flag, the CPUID  
instruction is available. The actual state of the ID  
Flag bit is irrelevant and provides no significance to  
the hardware. This bit is cleared (reset to zero) upon  
device reset (RESET or SRESET) for compatibility  
with Intel486 processor designs that do not support  
the CPUID instruction.  
4.0 ARCHITECTURAL AND  
FUNCTIONAL OVERVIEW  
The embedded IntelDX2 processor architecture is  
essentially the same as the IntelDX2 processor.  
Refer to the Embedded Intel486™ Processor Family  
Developer’s Manual for a description of the IntelDX2  
processor.  
CPUID-instruction details are provided here for the  
embedded IntelDX2 processor. Refer to Intel Appli-  
cation Note AP-485 Intel Processor Identification  
with the CPUID Instruction (Order No. 241618) for a  
description that covers all aspects of the CPUID  
instruction and how it pertains to other Intel  
processors.  
Note that the embedded IntelDX2 processor has one  
pin reserved for possible future use. This pin, an  
input signal, is called RESERVED# and must be  
connected to a 10-KΩ pull-up resistor. The pull-up  
resistor must be connected only to the RESERVED#  
pin. Do not share this resistor with other pins  
requiring pull-ups.  
4.1.1 Operation of the CPUID Instruction  
4.1 CPUID Instruction  
The CPUID instruction requires the software  
developer to pass an input parameter to the  
processor in the EAX register. The processor  
response is returned in registers EAX, EBX, EDX,  
and ECX.  
The embedded IntelDX2 processor supports the  
CPUID instruction (see Table 13). Because not all  
Intel processors support the CPUID instruction, a  
simple test can determine if the instruction is  
supported. The test involves the processor’s ID Flag,  
which is bit 21 of the EFLAGS register. If software  
Table 13. CPUID Instruction Description  
Parameter passed in  
EAX  
Processor  
Core Clocks  
OP CODE  
Instruction  
Description  
(Input Value)  
0F A2  
CPUID  
9
14  
9
0
1
Vendor (Intel) ID String  
Processor Identification  
Undefined (Do Not Use)  
> 1  
Vendor ID String - When the parameter passed in EAX is 0 (zero), the register values returned upon  
instruction execution are shown in the following table.  
31-------------24  
23-----------16  
15--------------8  
7--------------0  
High Value (= 1)  
EAX  
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 1  
Vendor ID String  
(ASCII  
EBX  
EDX  
ECX  
u (75)  
I (49)  
l (6C)  
n (6E)  
e (65)  
e (65)  
e (65)  
n (6E)  
t (74)  
G (47)  
i (69)  
n (6E)  
Characters)  
The values in EBX, EDX and ECX indicate an Intel processor. When taken in the proper order, they decode to  
the string “GenuineIntel.”  
25  
 
Embedded IntelDX2™ Processor  
Processor Identification - When the parameter passed to EAX is 1 (one), the register values returned upon  
instruction execution are:  
31---------------------------14  
13,12  
0 0  
11----8  
7----4  
3----0  
Processor  
Signature  
EAX  
(Do Not Use)  
0 1 0 0  
Family  
0 0 1 1  
Model  
XXXX  
Intel Reserved  
Processor  
Type  
Stepping  
(Intel releases information about stepping numbers as needed)  
31--------------------------------------------------------------------------------------------------0  
Intel Reserved  
(Do Not Use)  
EBX  
ECX  
Intel Reserved  
Intel Reserved  
31----------------------------------------------------------------------------2  
0------------------------------------------------------------------------------0  
1
0
Feature Flags  
EDX  
1
0
VME  
FPU  
4.2 Identification After Reset  
Processor Identification - Upon reset, the EDX register contains the processor signature:  
31---------------------------14  
13,12  
11----8  
7----4  
3----0  
XXXX  
Stepping  
Processor  
Signature  
EDX  
(Do Not Use)  
0 0  
0 1 0 0  
Family  
0 0 1 1  
Model  
Intel Reserved  
Processor  
Type  
(Intel releases information about stepping numbers as needed)  
4.3 Boundary Scan (JTAG)  
4.3.1 Device Identification  
Tables 14 and 15 show the 32-bit code for the embedded IntelDX2 processor. This code is loaded into the  
Device Identification Register.  
Table 14. Boundary Scan Component Identification Code (3.3 Volt Processor)  
Version  
Part Number  
Mfg ID  
1
009H = Intel  
VCC  
0=5 V  
1=3.3 V  
Family  
0100 = Intel486  
CPU Family  
Model  
00101 =  
embedded IntelDX2  
processor  
Intel  
Architecture  
Type  
31----28  
XXXX  
27  
1
26-----------21  
000001  
20----17  
0100  
16--------12  
00101  
11------------1  
00000001001  
0
1
(Intel releases information about version numbers as needed)  
Boundary Scan Component Identification Code = x828 5013 (Hex)  
26  
Embedded IntelDX2™ Processor  
Table 15. Boundary Scan Component Identification Code (5 Volt Processor)  
Version  
Part Number  
Mfg ID  
1
009H = Intel  
VCC  
0=5 V  
1=3.3 V  
Intel  
Architecture  
Type  
Family  
0100 = Intel486  
CPU Family  
Model  
00101 =  
embedded IntelDX2  
processor  
31----28  
XXXX  
27  
0
26-----------21  
000001  
20----17  
0100  
16--------12  
00101  
11------------1  
00000001001  
0
1
(Intel releases information about version numbers as needed)  
Boundary Scan Component Identification Code = x028 5013 (Hex)  
4.3.2 Boundary Scan Register Bits and Bit  
Order  
The following is the bit order of the embedded  
IntelDX2 processor boundary scan register:  
The boundary scan register contains a cell for each  
pin as well as cells for control of bidirectional and  
three-state pins. There are “Reserved” bits which  
correspond to no-connect (N/C) signals of the  
embedded IntelDX2 processor. Control registers  
WRCTL, ABUSCTL, BUSCTL, and MISCCTL are  
used to select the direction of bidirectional or three-  
TDO ← A2, A3, A4, A5, RESERVED#, A6,  
A7, A8, A9, A10, A11, A12, A13,  
A14, A15, A16, A17, A18, A19,  
A20, A21, A22, A23, A24, A25,  
A26, A27, A28, A29, A30, A31,  
DP0, D0, D1, D2, D3, D4, D5, D6,  
D7, DP1, D8, D9, D10, D11, D12,  
D13, D14, D15, DP2, D16, D17,  
D18, D19, D20, D21, D22, D23,  
DP3, D24, D25, D26, D27, D28,  
D29, D30, D31, STPCLK#,  
state output signal pins.  
A “1” in these cells  
designates that the associated bus or bits are floated  
if the pins are three-state, or selected as input if they  
are bidirectional.  
• WRCTL controls D31-D0 and DP3–DP0  
• ABUSCTL controls A31-A2  
IGNNE#,  
SMIACT#, SRESET, NMI, INTR,  
FLUSH#, RESET, A20M#,  
FERR#,  
SMI#,  
• BUSCTL controls ADS#, BLAST#, PLOCK#,  
LOCK#, W/R#, BE0#, BE1#, BE2#, BE3#, M/IO#,  
D/C#, PWT, and PCD  
EADS#, PCD, PWT, D/C#, M/IO#,  
BE3#, BE2#, BE1#, BE0#, BREQ,  
W/R#, HLDA, CLK, RESERVED#,  
AHOLD, HOLD, KEN#, RDY#,  
BS8#, BS16#, BOFF#, BRDY#,  
• MISCCTL controls PCHK#, HLDA, and BREQ  
PCHK#,  
BLAST#,  
LOCK#,  
ADS#,  
PLOCK#,  
MISCCTL,  
BUSCTL, ABUSCTL, WRCTL  
← TDI  
27  
Embedded IntelDX2™ Processor  
5.0 ELECTRICAL SPECIFICATIONS  
5.1 Maximum Ratings  
5.2 DC Specifications  
The following tables show the operating supply  
voltages, DC I/O specifications, and component  
power consumption for the embedded IntelDX2  
processor.  
Table 16 is a stress rating only. Extended exposure  
to the Maximum Ratings may affect device reliability.  
Table 17. Operating Supply Voltages  
Furthermore, although the embedded IntelDX2  
processor contains protective circuitry to resist  
damage from electrostatic discharge, always take  
precautions to avoid high static voltages or electric  
fields.  
Product  
VCC  
x80486DX2SC50  
x80486DX2SA66  
3.3 V ± 0.3 V  
5.0 V ± 0.25 V  
Functional operating conditions are given in Section  
5.2, DC Specifications and Section 5.3, AC Speci-  
fications.  
Note: To address the fact that many of the package  
prefix variables have changed, all package prefix  
variables in this document are now indicated with  
an "x".  
Table 16. Absolute Maximum Ratings  
Case Temperature under  
Bias  
-65 °C to +110 °C  
Storage Temperature  
-65 °C to +150 °C  
DC Voltage on Any Pin with  
Respect to Ground  
-0.5 V to VCC + 0.5 V  
Supply Voltage V  
Respect to VSS  
with  
-0.5 V to +6.5 V  
CC  
28  
 
 
Embedded IntelDX2™ Processor  
Table 18. 3.3 V DC Specifications  
Functional Operating Range: VCC = 3.3 V ± 0.3 V, TCASE=0 °C to +85 °C  
Symbol  
VIL  
Parameter  
Input LOW Voltage  
Min.  
-0.3  
Max.  
+0.8  
Unit  
V
Notes  
VIH  
Input HIGH Voltage  
2.0  
VCC +0.3  
VCC +0.3  
V
Note 1  
VIHC  
VOL  
Input HIGH Voltage of CLK  
Output LOW Voltage  
VCC -0.6  
V
I
I
OL = 2.0 mA  
0.4  
0.2  
V
V
OL = 100 µA  
VOH  
Output HIGH Voltage  
OH = -2.0 mA  
I
2.4  
VCC -0.2  
V
V
IOH = -100 µA  
ILI  
Input Leakage Current  
15  
µA  
Note 2  
IIH  
Input Leakage Current  
SRESET  
200  
300  
µA  
µA  
Note 3  
Note 3  
IIL  
Input Leakage Current  
Output Leakage Current  
Input Capacitance  
400  
15  
10  
10  
6
µA  
µA  
pF  
pF  
pF  
Note 4  
ILO  
CIN  
Note 5  
Note 5  
Note 5  
COUT  
CCLK  
I/O or Output Capacitance  
CLK Capacitance  
NOTES:  
1. All inputs except CLK.  
2. This parameter is for inputs without pull-up or pull-down resistors and 0V ≤ VIN ≤ VCC  
3. This parameter is for inputs with pull-down resistors and VIH = 2.4V.  
4. This parameter is for inputs with pull-up resistors and VIL = 0.4V.  
.
5.  
F =1 MHz. Not 100% tested.  
C
29  
Embedded IntelDX2™ Processor  
Table 19. 3.3 V ICC Values  
Functional Operating Range: VCC = 3.3 V ±0.3 V; TCASE = 0°C to +85°C  
Operating  
Parameter  
CC Active  
(Power Supply)  
Frequency  
Typ  
Maximum  
Notes  
I
40 MHz  
50 MHz  
450 mA  
550 mA  
Note 1  
ICC Active  
(Thermal Design)  
40 MHz  
50 MHz  
318 mA  
395 mA  
416 mA  
507 mA  
Notes 2, 3, 4  
Note 5  
ICC Stop Grant  
40 MHz  
50 MHz  
20 mA  
23 mA  
40 mA  
50 mA  
ICC Stop Clock  
0 MHz  
100 µA  
1 mA  
Note 6  
NOTES:  
1. This parameter is for proper power supply selection. It is measured using the worst case instruction mix at VCC = 3.6V.  
2. The maximum current column is for thermal design power dissipation. It is measured using the worst case instruction mix  
at VCC = 3.3V.  
3. The typical current column is the typical operating current in a system. This value is measured in a system using a typical  
device at VCC = 3.3V, running Microsoft Windows 3.1 at an idle condition. This typical value is dependent upon the specific  
system configuration.  
4. Typical values are not 100% tested.  
5. The ICC Stop Grant specification refers to the ICC value once the embedded IntelDX2 processor enters the Stop Grant or  
Auto HALT Power Down state.  
6. The ICC Stop Clock specification refers to the ICC value once the embedded IntelDX2 processor enters the Stop Clock  
state. The VIH and VIL levels must be equal to VCC and 0 V, respectively, to meet the ICC Stop Clock specifications.  
30  
Embedded IntelDX2™ Processor  
Table 20. 5 V DC Specifications  
Functional operating range: VCC = 5V ± 0.25V; TCASE = 0°C to +85°C  
Symbol  
VIL  
Parameter  
Input LOW Voltage  
Min  
-0.3  
2.0  
Max  
+0.8  
Unit  
V
Notes  
VIH  
Input HIGH Voltage  
Output LOW Voltage  
Output HIGH Voltage  
Input Leakage Current  
VCC+0.3  
0.45  
V
VOL  
VOH  
ILI  
V
Note 1  
Note 2  
Note 3  
2.4  
V
15  
µA  
IIH  
Input Leakage Current  
SRESET  
200  
300  
µA  
µA  
Note 4  
Note 4  
IIL  
Input Leakage Current  
Output Leakage Current  
Input Capacitance  
400  
15  
20  
20  
20  
µA  
µA  
pF  
pF  
pF  
Note 5  
ILO  
CIN  
Note 6  
Note 6  
Note 6  
COUT  
CCLK  
Output or I/O Capacitance  
CLK Capacitance  
NOTES:  
1. This parameter is measured at:  
Address, Data, BEn# 4.0 mA  
Definition, Control 5.0 #mA  
2. This parameter is measured at:  
Address, Data, BEn# -1.0 mA  
Definition, Control -0.9 mA  
3. This parameter is for inputs without pull-ups or pull-downs and 0V ≤ VIN ≤ VCC  
4. This parameter is for inputs with pull-downs and VIH = 2.4V.  
5. This parameter is for inputs with pull-ups and VIL = 0.45V.  
6. FC=1 MHz; Not 100% tested.  
.
31  
Embedded IntelDX2™ Processor  
Table 21. 5 V ICC Values  
Functional Operating Range: VCC = 5V ±0.25V; TCASE = 0°C to +85°C  
Operating  
Parameter  
CC Active  
(Power Supply)  
Frequency  
Typ  
Maximum  
Notes  
I
50 MHz  
66 MHz  
950 mA  
1200 mA  
Note 1  
ICC Active  
(Thermal Design)  
50 MHz  
66 MHz  
680 mA  
901 mA  
906 mA  
1145 mA  
Notes 2, 3, 4  
Note 5  
ICC Stop Grant  
50 MHz  
66 MHz  
35 mA  
40 mA  
70 mA  
90 mA  
ICC Stop Clock  
0 MHz  
200 µA  
2 mA  
Note 6  
NOTES:  
1. This parameter is for proper power supply selection. It is measured using the worst case instruction mix at VCC = 5.25V.  
2. The maximum current column is for thermal design power dissipation. It is measured using the worst case instruction mix  
at VCC = 5V.  
3. The typical current column is the typical operating current in a system. This value is measured in a system using a typical  
device at VCC = 5V, running Microsoft Windows 3.1 at an idle condition. This typical value is dependent upon the specific  
system configuration.  
4. Typical values are not 100% tested.  
5. The ICC Stop Grant specification refers to the ICC value once the embedded IntelDX2 processor enters the Stop Grant or  
Auto HALT Power Down state.  
6. The ICC Stop Clock specification refers to the ICC value once the processor enters the Stop Clock state. The VIH and VIL  
levels must be equal to VCC and 0V, respectively, in order to meet the ICC Stop Clock specifications.  
32  
Embedded IntelDX2™ Processor  
5.3 AC Specifications  
The AC specifications for the embedded IntelDX2 processor are given in this section.  
Table 22. AC Characteristics  
TCASE = 0°C to +85°C; CL = 50pF, unless otherwise specified. (Sheet 1 of 2)  
Vcc (Package)  
3.3V  
(208-Lead  
SQFP)  
5V  
(168-Pin  
PGA)  
Symbol  
Parameter  
Min Max Min Max  
Unit  
MHz  
ns  
Figure  
Notes  
CLK Frequency  
8
25  
8
33  
Note 1  
t1  
CLK Period  
40  
125  
30  
125  
4
4
t1a  
CLK Period Stability  
±250  
±250  
ps  
Adjacent  
clocks  
t2  
t3  
t4  
t5  
t6  
CLK High Time  
CLK Low Time  
CLK Fall Time  
CLK Rise Time  
14  
14  
11  
11  
ns  
ns  
ns  
ns  
ns  
4
4
4
4
8
at 2V  
at 0.8V  
4
4
3
3
2V to 0.8V  
0.8V to 2V  
A31–A2, PWT, PCD, BE3–BE0#,  
M/IO#, D/C#, W/R#, ADS#, LOCK#,  
BREQ, HLDA, SMIACT#, FERR#  
Valid Delay  
3
19  
3
16  
t7  
A31–A2, PWT, PCD, BE3–BE0#,  
M/IO#, D/C#, W/R#, ADS#, LOCK#,  
BREQ, HLDA Float Delay  
28  
20  
ns  
9
Note 2  
t8  
t8a  
t9  
PCHK# Valid Delay  
3
3
24  
24  
28  
20  
3
3
22  
20  
20  
18  
ns  
ns  
ns  
ns  
7
8
9
8
BLAST#, PLOCK# Valid Delay  
BLAST#, PLOCK# Float Delay  
Note 2  
Note 2  
t10  
D31–D0, DP3–DP0 Write Data Valid  
Delay  
3
3
t11  
D31–D0, DP3–DP0 Write Data Float  
Delay  
28  
20  
ns  
9
t12  
t13  
t14  
t15  
t16  
t17  
t18  
t18a  
t19  
EADS# Setup Time  
8
3
5
3
5
3
5
3
6
8
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
5
5
5
5
6
6
5
5
5
EADS# Hold Time  
KEN#, BS16#, BS8# Setup Time  
KEN#, BS16#, BS8# Hold Time  
RDY#, BRDY# Setup Time  
RDY#, BRDY# Hold Time  
HOLD, AHOLD Setup Time  
BOFF# Setup Time  
8
3
8
3
10  
10  
3
HOLD, AHOLD, BOFF# Hold Time  
33  
Embedded IntelDX2™ Processor  
Table 22. AC Characteristics  
TCASE = 0°C to +85°C; CL = 50pF, unless otherwise specified. (Sheet 2 of 2)  
Vcc (Package)  
3.3V  
(208-Lead  
SQFP)  
5V  
(168-Pin  
PGA)  
Symbol  
Parameter  
Min Max Min Max  
Unit  
Figure  
Notes  
t20  
FLUSH#, A20M#, NMI, INTR, SMI#,  
STPCLK#, SRESET, RESET,  
IGNNE# Setup Time  
10  
5
ns  
5
Note 3  
t21  
FLUSH#, A20M#, NMI, INTR, SMI#,  
STPCLK#, SRESET, RESET,  
IGNNE# Hold Time  
3
3
ns  
5
Note 3  
t22  
t23  
D31–D0, DP3–DP0,  
A31–A4 Read Setup Time  
6
3
5
3
ns  
ns  
6
5
D31–D0, DP3–DP0,  
A31–A4 Read Hold Time  
6
5
NOTES:  
1. 0-MHz operation is guaranteed when the STPCLK# and Stop Grant bus cycle protocol is used.  
2. Not 100% tested, guaranteed by design characterization.  
3. A reset pulse width of 15 CLK cycles is required for warm resets (RESET or SRESET). Power-up resets (cold resets)  
require RESET to be asserted for at least 1 ms after VCC and CLK are stable.  
Table 23. AC Specifications for the Test Access Port  
(Both 3.3V SQFP and 5V PGA Processors)  
T
CASE = 0°C to +85°C; CL = 50 pF  
Symbol  
Parameter  
Min  
Max  
Unit  
MHz  
ns  
Figure  
Notes  
t24  
t25  
TCK Frequency  
TCK Period  
8
Note 1  
125  
40  
10  
10  
10  
10  
10  
11  
11  
11  
11  
11  
11  
11  
11  
t26  
TCK High Time  
TCK Low Time  
TCK Rise Time  
TCK Fall Time  
ns  
@ 2.0V  
@ 0.8V  
Note 2  
Note 2  
Note 3  
Note 3  
Note 3  
Note 3  
Note 3  
Note 3  
Note 3  
Note 3  
t27  
40  
ns  
t28  
8
8
ns  
t29  
ns  
t30  
TDI, TMS Setup Time  
8
10  
3
ns  
t31  
TDI, TMS Hold Time  
ns  
t32  
TDO Valid Delay  
30  
36  
30  
36  
ns  
t33  
TDO Float Delay  
ns  
t34  
All Outputs (except TDO) Valid Delay  
All Outputs (except TDO) Float Delay  
All Inputs (except TDI, TMS, TCK) Setup Time  
All Inputs (except TDI, TMS, TCK) Hold Time  
3
ns  
t35  
ns  
t36  
8
ns  
t37  
10  
ns  
NOTES:  
1. TCK period ≤ CLK period.  
2. Rise/Fall times are measured between 0.8V and 2.0V. Rise/Fall times can be relaxed by 1 ns per 10-ns increase in TCK  
period.  
3. Parameters t30 – t37 are measured from TCK.  
34  
Embedded IntelDX2™ Processor  
2.0 V  
1.5 V  
2.0 V  
1.5 V  
CLK  
0.8 V  
0.8 V  
t2  
t3  
t4  
t5  
t1  
tx  
ty  
1.5 V  
tx = input setup times  
ty = input hold times, output float, valid and hold times  
Figure 4. CLK Waveform  
Tx  
Tx  
Tx  
CLK  
t13  
t12  
EADS#  
BS8#, BS16#, KEN#  
t14  
t15  
t19  
t21  
t23  
t18  
t20  
t22  
BOFF#, AHOLD, HOLD  
RESET, FLUSH#,  
A20M#, INTR, NMI, SMI#,  
STPCLK#, SRESET, IGNNE#  
A31-A4  
(READ)  
Figure 5. Input Setup and Hold Timing  
35  
Embedded IntelDX2™ Processor  
Tx  
T2  
Tx  
CLK  
t16  
t17  
RDY#, BRDY#  
1.5 V  
1.5 V  
t23  
t22  
D31-D0, DP3–DP0  
Figure 6. Input Setup and Hold Timing  
T2  
Tx  
Tx  
Tx  
CLK  
RDY#, BRDY#  
D31-D0,  
DP3-DP0  
VALID  
MIN  
t8  
MAX  
VALID  
PCHK#  
Figure 7. PCHK# Valid Delay Timing  
36  
Embedded IntelDX2™ Processor  
Tx  
Tx  
Tx  
CLK  
MIN  
MAX  
t6  
A2-A31, PWT, PCD,  
BE0-3#, M/IO#,  
VALID n  
VALID n+1  
VALID n+1  
VALID n+1  
D/C#, W/R#, ADS#,  
LOCK#, BREQ, HLDA,  
SMIACT#  
MIN  
MAX  
t10  
VALID n  
D31-D0, DP3–DP0  
MIN  
MAX  
t8a  
BLAST#,  
PLOCK#  
VALID n  
Figure 8. Output Valid Delay Timing  
Tx  
Tx  
Tx  
CLK  
MIN  
t7  
t6  
A2-A31, PWT, PCD,  
BE0-3#, M/IO#, D/C#,  
W/R#, ADS#, LOCK#,  
BREQ, HLDA, FERR#  
VALID  
MIN  
MIN  
t11  
t10  
D31-D0, DP3–DP0  
VALID  
t9  
t8a  
BLAST#,  
PLOCK#  
VALID  
Figure 9. Maximum Float Delay Timing  
37  
Embedded IntelDX2™ Processor  
2.0 V  
2.0 V  
0.8 V  
t27  
TCK  
0.8 V  
t26  
t28  
t29  
t25  
Figure 10. TCK Waveform  
1.5 V  
TCK  
t31  
t30  
TMS,  
TDI  
VALID  
t33  
t32  
VALID  
TDO  
OUTPUT  
INPUT  
t35  
t34  
VALID  
t37  
VALID  
t36  
VALID  
Figure 11. Test Signal Timing Diagram  
38  
Embedded IntelDX2™ Processor  
5.4 Capacitive Derating Curves  
The following graphs are the capacitive derating curves for the embedded IntelDX2 processor.  
nom+7  
nom+6  
nom+5  
nom+4  
nom+3  
nom+2  
nom+1  
nom  
nom-1  
nom-2  
25  
50  
75  
100  
125  
150  
Capacitive Load (pF)  
NOTE: This graph will not be linear outside of the capacitive range shown.  
nom = nominal value from the AC Characteristics table.  
Figure 12. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions  
for a Low-to-High Transition, 3.3 V Processor  
nom+5  
nom+4  
nom+3  
nom+2  
nom+1  
nom  
nom-1  
nom-2  
25  
50  
75  
100  
125  
150  
Capacitive Load (pF)  
NOTE: This graph will not be linear outside of the capacitive range shown.  
nom = nominal value from the AC Characteristics table.  
Figure 13. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions  
for a High-to-Low Transition, 3.3 V Processor  
39  
Embedded IntelDX2™ Processor  
nom+5  
nom+4  
nom+3  
nom+2  
nom+1  
nom  
nom-1  
nom-2  
25  
50  
75  
Capacitive Load (pF)  
100  
125  
150  
Note: This graph will not be linear outside of the capacitive range shown.  
nom = nominal value from the AC Characteristics table.  
A3234-01  
Figure 14. Typical Loading Delay versus Load Capacitance under  
Worst-Case Conditions for a Low-to-High Transition, 5 V Processor  
nom+7  
nom+6  
nom+5  
nom+4  
nom+3  
nom+2  
nom+1  
nom  
nom-1  
nom-2  
25  
50  
75  
100  
125  
150  
Capacitive Load (pF)  
Note: This graph will not be linear outside of the capacitive range shown.  
nom = nominal value from the AC Characteristics table.  
A3235-01  
Figure 15. Typical Loading Delay versus Load Capacitance under  
Worst-Case Conditions for a High-to-Low Transition, 5 V Processor  
40  
Embedded IntelDX2™ Processor  
6.0 MECHANICAL DATA  
This section describes the packaging dimensions and thermal specifications for the embedded IntelDX2  
processor.  
6.1 Package Dimensions  
30.6 ± 0.25  
28.0 ± 0.10  
25.50 (ref)  
1.14  
(ref)  
.40 Min  
157  
208  
0.13 + 0.12-0.08  
1
156  
0˚ Min  
7˚ Max  
0.60 ± 0.10  
1.30 Ref  
0.50  
Top View  
3.37 ± 0.08  
3.70 Max  
0.13 Min  
0.25 Max  
52  
105  
53  
104  
NOTE: Length measurements same as width measurements  
Tolerance Window for  
Lead Skew from Theoretical  
True Position  
1.76 Max  
0.10 Max  
Units: mm  
A3262-01  
Figure 16. 208-Lead SQFP Package Dimensions  
41  
Embedded IntelDX2™ Processor  
Figure 17. Principal Dimensions and Data for 168-Pin Pin Grid Array Package  
Table 24. 168-Pin Ceramic PGA Package Dimensions  
Millimeters  
Max  
Inches  
Symbol  
Min  
3.56  
0.64  
2.8  
Notes  
Min  
Max  
Notes  
A
A1  
A2  
A3  
B
4.57  
0.140  
0.025  
0.110  
0.045  
0.017  
1.735  
1.595  
0.090  
0.100  
0.180  
0.045  
0.140  
0.055  
0.020  
1.765  
1.605  
0.110  
0.130  
1.14  
SOLID LID  
SOLID LID  
SOLID LID  
SOLID LID  
3.5  
1.14  
0.43  
44.07  
40.51  
2.29  
2.54  
1.40  
0.51  
D
44.83  
40.77  
2.79  
D1  
e1  
L
3.30  
N
168  
168  
S1  
1.52  
2.54  
0.060  
0.100  
42  
Embedded IntelDX2™ Processor  
Table 25. Ceramic PGA Package Dimension Symbols  
Letter or Symbol  
Description of Dimensions  
Distance from seating plane to highest point of body  
Distance between seating plane and base plane (lid)  
Distance from base plane to highest point of body  
Distance from seating plane to bottom of body  
Diameter of terminal lead pin  
A
A1  
A2  
A3  
B
D
Largest overall package dimension of length  
D1  
e1  
L
A body length dimension, outer lead center to outer lead center  
Linear spacing between true lead position centerlines  
Distance from seating plane to end of lead  
S1  
Other body dimension, outer lead center to edge of body  
NOTES:  
1. Controlling dimension: millimeter.  
2. Dimension “e1” (“e”) is non-cumulative.  
3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415–0.0430 inch.  
4. Dimensions “B”, “B1” and “C” are nominal.  
5. Details of Pin 1 identifier are optional.  
43  
Embedded IntelDX2™ Processor  
Where TJ, TA, TC equals Junction, Ambient and  
Case Temperature respectively. θJC, θJA equals  
Junction-to-Case and Junction-to-Ambient thermal  
Resistance, respectively. P is defined as Maximum  
Power Consumption.  
6.2 Package Thermal Specifications  
The embedded IntelDX2 processor is specified for  
operation when the case temperature (TC) is within  
the range of 0°C to 85°C. TC may be measured in  
any environment to determine whether the processor  
is within the specified operating range.  
Values for θJA and θJC are given in the following  
tables for each product at its maximum operating  
frequencies. Maximum TA is shown for each product  
operating at various processor frequencies (twice  
the CLK frequencies).  
The ambient temperature (TA) can be calculated  
from θJC and θJA from the following equations:  
TJ = TC + P * θJC  
T
T
T
A = TJ - P * θJA  
C = TA + P * [θJA - θJC  
]
A = TC - P * [θJA - θJC  
]
Table 26. Thermal Resistance, θJA (°C/W)  
θJA vs. Airflow — ft/min. (m/sec)  
0
200  
400  
600  
800  
1000  
(0)  
(1.01)  
(2.03)  
(3.04)  
(4.06)  
(5.07)  
208-Lead SQFP (3.3V) - Without Heat Sink  
168-Pin PGA (5V) - Without Heat Sink  
168-Pin PGA (5V) - With Heat Sink*  
*0.350" high omnidirectional heat sink.  
24.0  
17.0  
13.0  
17.0  
14.5  
8.0  
15.0  
12.5  
6.0  
13.0  
11.0  
5.0  
–
–
10.0  
4.5  
9.5  
4.25  
Table 27. Thermal Resistance, θJC (°C/W)  
θJC vs. Airflow — ft/min. (m/sec)  
0
200  
400  
600  
(0)  
(1.01)  
(2.03)  
(3.04)  
600  
6.0  
0
200  
6.0  
–
400  
6.0  
–
208-Lead SQFP (3.3V)  
168-Pin PGA (5V)  
3.5  
1.5  
–
Table 28. Maximum Tambient, TA max (°C)  
Airflow — ft/min. (m/sec)  
Freq.  
0
200  
400  
600  
(MHz)  
(0)  
(1.01)  
(2.03)  
(3.04)  
IntelDX2™ Processor  
208-Lead SQFP (3.3V)  
Without Heat Sink  
168-Pin PGA (5V)  
Without Heat Sink  
168-Pin PGA (5V)  
With Heat Sink  
40  
50  
50  
66  
50  
66  
57  
51  
15  
-4  
70  
67  
26  
11  
56  
48  
73  
70  
35  
22  
65  
59  
75  
73  
46  
36  
69  
65  
33  
19  
44  
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