8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
7.0 THERMAL CHARACTERISTICS
All thermal impedance data is approximate for static
air conditions at 1 watt of power dissipation. Values
will change depending on operating conditions and
the application. The Intel Packaging Handbook
(order number 240800) describes Intel’s thermal
impedance test methodology. The Components
Quality and Reliability Handbook (order number
210997) provides quality and reliability information.
1. A heading was added for Section 1.0, “Product
Overview,” and the remaining sections were
renumbered.
2. List of features, the 8XC196NU has four
options (0–3) for programmable wait states for
each chip select, not sixteen (0–15) as previ-
ously stated.
3. The ROM SQFP (SB83C196NU) pinout and
pin assignment tables have been deleted.
4. Figure 5, package designator in diagram
changed to “S” from “SB” to correctly indicate
the QFP package type.
Table 19. Thermal Characteristics
Package Type
θJA
θJC
5. Table 8, EA# signal description added.
6. Table 8, signal descriptions for BREQ#,
HLDA#, HOLD#, PLLEN2:1, and RESET#
have been modified.
7. Table 9, redesigned and footnotes reordered.
8. Table 10, VIH2 specification added with foot-
note.
100-pin QFP 80C196NU
55°C/W
11°C/W
100-pin SQFP 80C196NU 66°C/W 16.5°C/W
100-pin QFP 83C196NU 55°C/W 11°C/W
8.0 8XC196NU ERRATA
9. Figure 6, corrected to state PLLEN2:1=01 (not
PLLEN2:1=10).
The 8XC196NU may contain design defects or
errors known as errata. Characterized errata that
may cause the 8XC196NU’s behavior to deviate
from published specifications are documented in the
8XC196NU Specification Update (272864-001).
Specification updates can be obtained from your
local Intel sales office or from the World Wide Web
(www.intel.com).
10. Tables 12 and 14, B-step timing added for
T
WHBX min and TRHBX min.
11. Table 12, deleted notes 4 and 5, added note 2,
and reordered remaining notes.
12. Table 13, deleted notes 1, 3, and 6 and reor-
dered remaining notes.
13. Table 14, deleted notes 4, 5, and 6, added note
2, and reordered remaining notes.
14. Table 15, deleted notes 1, 3, and 6 and reor-
dered remaining notes.
15. Tables 13 and 15, the minimum timing for TRXDX
improved from 2 ns to 0 ns.
9.0 DATASHEET REVISION HISTORY
This datasheet is valid for devices with a “B” or “C”
designation at the end of the topside tracking
number. Datasheets are changed as new device
information becomes available. Verify with your local
Intel sales office that you have the latest version
before finalizing a design or ordering devices.
16. Figures 7–11, updated to reflect both A- and B-
step timings on the BHE#, INST signal.
17. Section 5.4.3, the second sentence of the first
paragraph, the word “and” replaced by “or”.
18. Table 19, thermal characteristics specifications
have been changed and expanded.
19. The errata list was replaced with a reference to
the specification update document.
This is the -004 version of the datasheet. The
following changes were made in this version:
The following changes were made in the -002
version of the datasheet:
1. All references to “ADVANCE INFORMATION”
have been changed to “PRELIMINARY”.
2. Table note added to Tables 4 and 6.
3. Table 15, removed note (2) attachment from
1. The input frequency on XTAL1, formerly called
F
OSC, is now called FXTAL1. The internal operat-
TRHDZ
4. Table 15, specification change made to the fol-
lowing timings: TAVDV, TSLDV, TCLYX
.
ing frequency and operating period are
denoted by (f) and (t), respectively.
.
2. 25 MHz is the maximum input frequency when
using an external crystal oscillator; however,
50 MHz can be applied with an external clock
source.
This is the -003 version of the datasheet. The
following changes were made in this version:
38
PRELIMINARY
