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CYIL2SM1300-EVAL

型号：

CYIL2SM1300-EVAL

描述：

LUPA 1300-2 ：高速CMOS图像传感器[ LUPA 1300-2: High Speed CMOS Image Sensor ]

品牌：

ONSEMI[ ONSEMI ]

页数：

41 页

PDF大小：

1752 K

下载PDF手册
CYIL2SM1300AA  
LUPA 1300-2: High Speed CMOS  
Image Sensor  
FPN correction enables the sensor to output ready to use image  
data for most applications. To enable simple and reliable system  
integration, the 12 channels, 1 sync channel, 8 Gbps, and LVDS  
serial link protocol supports skew correction and serial link  
integrity monitoring.  
Features  
■
■
■
■
■
■
■
■
■
1280 x 1024 Active Pixels  
14 µm X 14 µm Square Pixels  
1” Optical Format  
The peak responsivity of the 14 µm x 14 µm 6T pixel is 7350  
V.m2/W.s. Dynamic range is measured at 57 dB. In full frame  
video mode, the sensor consumes 1350 mW from the 2.5V  
power supply. The sensors integrate A/D conversion, on-chip  
timing for a wide range of operating modes, and has an LVDS  
interface for easy system integration.  
Monochrome or Color Digital Output  
500 fps Frame Rate  
On-Chip 10-Bit ADCs  
12 LVDS Serial Outputs  
Random Programmable ROI Readout  
Pipelined and Triggered Snapshot Shutter  
By removing the visually disturbing column patterned noise, this  
sensor enables building a camera without any offline correction  
or the need for memory. In addition, the on-chip column FPN  
correction is more reliable than an offline correction, because it  
compensates for supply and temperature variations. The sensor  
requires one master clock for operations up to 500 fps.  
■
■
■
■
On-Chip Column FPN Correction  
Serial to Parallel Interface (SPI)  
Limited Supplies: Nominal 2.5V and 3.3V  
0°C to 70°C Operational Temperature Range  
The LUPA 1300-2 is housed in a 168 pin µPGA package and is  
available in a monochrome version and Bayer (RGB) patterned  
color filter array. The monochrome version is available without  
glass. Contact your local Cypress office.  
■
■
168-Pin µPGA Package  
Power Dissipation: 1350 mW  
Figure 1. LUPA 1300-2 Die Photo  
Applications  
■
■
■
■
■
High Speed Machine Vision  
Motion Analysis  
Intelligent Traffic System  
Medical Imaging  
Industrial Imaging  
Description  
The LUPA 1300-2 is an integrated SXGA high speed, high  
sensi¬tivity CMOS image sensor. This sensor targets high speed  
machine vision and industrial monitoring applications. The LUPA  
1300-2 sensor runs at 500 fps and has triggered and pipelined  
shutter modes. It packs 24 parallel 10-bit A/D converters with an  
aggregate conversion rate of 740 MSPS. On-chip digital column  
Ordering Information  
Marketing Part Number  
CYIL2SM1300AA-GZDC  
Mono/Color  
Package  
168 pin µPGA  
Demo Kit  
Mono with Glass  
Mono without Glass[1]  
Color with Glass  
CYIL2SM1300AA-GWCES  
CYIL2SC1300AA-GZDC  
CYIL2SM1300-EVAL  
Mono Demo Kit  
Note  
1. Contact your local sales office for the windowless option.  
Cypress Semiconductor Corporation  
Document Number: 001-24599 Rev. *C  
•
198 Champion Court  
•
San Jose  
,
CA 95134-1709  
•
408-943-2600  
Revised September 18, 2009  
[+] Feedback  
CYIL2SM1300AA  
Overview  
Specifications  
Table 1. General Specifications  
Parameter  
This data sheet describes the interface of the LUPA1300-2  
image sensor. The SXGA resolution CMOS active pixel sensor  
features synchronous shutter and a maximal frame rate of  
500 fps in full resolution. The readout speed is boosted by sub  
sampling and the windowed region of interest (ROI) readout.  
FPN correction cannot be used in conjunction with sub-sampling  
and windowed region of interest readout. High dynamic range  
scenes can be captured using the double and multiple slope  
functionality. User programmable row and column start and stop  
positions enables windowing. Sub sampling reduces resolution  
while maintaining the constant field of view and an increased  
frame rate.  
Specifications  
Active Pixels  
Pixel Size  
Pixel Type  
Pixel Rate  
1280 (H) x 1024 (V)  
14 µm x 14 µm  
6T pixel architecture  
630 Mbps per channel (12 serial  
LVDS outputs)  
Shutter Type  
Frame Rate  
Pipelined and Triggered Global  
Shutter  
500 fps at 1.3 Mpixel (boosted by  
subsampling and windowing)  
The LUPA1300-2 sensor has 12 LVDS high speed outputs that  
transfer image data over longer distances. This simplifies the  
surrounding system. The LVDS interface can receive high speed  
and wide bandwidth data signals and maintain low noise and  
distortion. A special training mode enables the receiving system  
to synchronize the coming data stream when switching to  
master, slave, or triggered mode. The image sensor also  
integrates a programmable offset and gain amplifier for each  
channel.  
Master Clock  
315 MHz for 500 fps  
Windowing (ROI)  
Randomly programmable ROI read  
out up to four multiple windows  
Read Out  
Windowed, flipped, mirrored, and  
subsampled read out possible  
ADC Resolution  
Sensitivity  
10-bit, on-chip  
A 10-bit ADC converts the analog data to a 10-bit digital word  
stream. The sensor uses a 3-wire Serial-Parallel Interface (SPI).  
It requires only one master clock for operation up to 500 fps.  
10.16 V/lux.s at 550 nm  
Extended Dynamic  
Range  
Multiple slope (up to 90 dB optical  
dynamic range)  
The sensor is available in a monochrome version or Bayer (RGB)  
patterned color filter array. It is placed in a 168-pin ceramic µPGA  
package.  
Table 2. Electro Optical Specifications  
Parameter  
Value  
Conversion gain  
Full well charge  
Responsivity  
34µV/e-  
30000e-  
7350 V.m2/W.s at 680 nm  
40%  
Fill factor  
Parasitic light sensitivity  
Dark noise  
QE x FF  
< 1/10000  
37e-  
35% at 680 nm  
2% rms of the output swing  
<1% rms of the output signal  
170 mV/s at 30°C  
1350 mW  
FPN  
PRNU  
Dark signal  
Power dissipation  
Document Number: 001-24599 Rev. *C  
Page 2 of 41  
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CYIL2SM1300AA  
Photovoltaic Response Curve  
Figure 2. Photo Voltaic Response of LUPA 1300-2  
Spectral Response Curve  
Figure 3. Spectral Response of LUPA 1300-2  
Document Number: 001-24599 Rev. *C  
Page 3 of 41  
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CYIL2SM1300AA  
Figure 4. Spectral Response of LUPA 1300-2 Color Sensor  
Document Number: 001-24599 Rev. *C  
Page 4 of 41  
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CYIL2SM1300AA  
Electrical Specifications  
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.  
Table 3. Absolute Ratings [2]  
Unit  
Symbol  
VDIG  
Parameter  
Min  
Max  
s
Core digital supply voltage  
Analog supply voltage  
DC supply current  
-0.5  
-0.5  
5.5  
5.5  
V
VIN  
V
IIO  
mA  
V
ESD: HBM  
ESD: CDM  
TJ  
Human Body Model  
Charged Device Model  
Temperature range  
2000  
500  
0
V
70  
°C  
Table 4. Power Supply Ratings [3, 4, 5]  
Boldface limits apply for TA=TMIN to TMAX, all other limits TA=+25°C. Clock = 315 MHz  
Symbol  
Power Supply  
Parameter  
Condition  
Min  
Typ  
2.5  
7
Max  
Units  
V
V
ANA, GNDANA Analog Supply Operating voltage  
-5%  
-5%  
-5%  
+5%  
20  
Dynamic Current  
Peak Current  
Clock enabled, lux=0  
Clock enabled, lux=0  
Shutdown mode, lux=0  
mA  
mA  
mA  
V
16  
1
Standby current  
Operating voltage  
Dynamic Current  
Peak Current  
V
V
DIG, GNDDIG Digital Supply  
2.5  
80  
130  
52  
2.5  
6
+5%  
120  
Clock enabled, lux=0  
Clock enabled, lux=0  
Shutdown mode, lux=0  
mA  
Standby current  
Operating voltage  
Dynamic Current  
mA  
V
PIX, GNDPIX Pixel Supply  
+5%  
50  
Clock enabled, lux=0  
mA  
A
Peak Current during FOT Clock enabled, lux=0,  
transient duration=9 µs  
1.4  
Peak Current during ROT Clock enabled, lux=0,  
transient duration=2.5 µs  
35  
mA  
Standby current  
Operating voltage  
Dynamic Current  
Peak current  
Shutdown mode, lux=0  
1
mA  
V
VLVDS  
GNDLVDS  
,
LVDS Supply  
-5%  
-5%  
2.5  
220  
280  
100  
2.5  
210  
260  
3
+5%  
275  
Clock enabled, lux=0  
Clock enabled, lux=0  
Shutdown mode, lux=0  
mA  
mA  
mA  
V
Standby current  
Operating voltage  
Dynamic Current  
Peak Current  
VADC, GNDADC ADC Supply  
+5%  
275  
Clock enabled, lux=0  
Clock enabled, lux=0  
Shutdown mode, lux=0  
mA  
mA  
mA  
Standby current  
Notes  
2. Absolute ratings are those values beyond which damage to the device may occur.  
3. All parameters are characterized for DC conditions after thermal equilibrium is established.  
4. Peak currents were measured without the load capacitor from the LDO (Low Dropout Regulator). The 100 nF capacitor bank was connected to the pin in question.  
5. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is recommended that normal precautions  
be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit.  
Document Number: 001-24599 Rev. *C  
Page 5 of 41  
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CYIL2SM1300AA  
Table 4. Power Supply Ratings [3, 4, 5] (continued)  
Boldface limits apply for TA=TMIN to TMAX, all other limits TA=+25°C. Clock = 315 MHz  
Symbol  
Power Supply  
Parameter  
Operating voltage  
Dynamic Current  
Peak Current  
Condition  
Min  
Typ  
2.5  
30  
85  
0.1  
2.5  
2
Max  
+5%  
50  
Units  
V
VBUF, GNDBUF Buffer Supply  
-5%  
Clock enabled, lux=0  
Clock enabled, lux=0  
shutdown mode, lux=0  
mA  
mA  
mA  
V
Standby current  
Operating voltage  
Dynamic Current  
Peak Current  
VSAMPLE  
,
Sampling  
Circuitry Supply  
-5%  
-5%  
+5%  
GNDSAMPLE  
Clock enabled, lux=0  
Clock enabled, lux=0  
Shutdown mode, lux=0  
mA  
mA  
mA  
V
42  
1
Standby current  
Operating voltage  
Dynamic Current  
Peak Current  
VRES  
Reset Supply  
3.5  
2
+5%  
15  
Clock enabled, lux=0  
Clock enabled, lux=0  
Shutdown mode, lux=0  
mA  
mA  
mA  
V
65  
2
Standby current  
Operating voltage  
Dynamic Current  
VRES_AB  
Antiblooming  
Supply  
-10%  
0.7  
1
+10%  
Clock enabled, lux=0  
Clock enabled, lux=0  
mA  
mA  
Peak Current following  
edge reset  
50  
Standby current  
Operating voltage  
Dynamic Current  
Peak Current  
Shutdown mode, lux=0  
1
mA  
V
VRES_DS  
VRES_TS  
VMEM_L  
Reset Dual  
Slope Supply  
-5%  
-5%  
-5%  
2.5  
0.4  
36  
1.8  
0.3  
14  
2.5  
0.2  
62  
30  
3.3  
1
+5%  
3
Clock enabled, lux=0  
Clock enabled, lux=0  
mA  
mA  
V
Reset Triple  
Slope Supply  
Operating voltage  
Dynamic Current  
Peak Current  
+5%  
2
Clock enabled, lux=0  
Clock enabled, lux=0  
mA  
mA  
V
Memory  
Element low  
level supply  
Operating voltage  
Dynamic Current  
+5%  
1
Clock enabled, lux=0  
mA  
mA  
mA  
V
Peak Current during FOT Clock enabled, lux=0  
Peak Current during FOT Clock enabled, bright  
Operating voltage  
VMEM_H  
Memory  
Element high  
level supply  
-5%  
+5%  
Dynamic Current  
Clock enabled, lux=0  
mA  
mA  
V
Peak Current during FOT Clock enabled, lux=0  
Operating voltage  
45  
0.7  
0.3  
32  
25  
VPRECH  
Pre_charge  
Driver Supply  
-10%  
+10%  
3
Dynamic Current  
Clock enabled, lux=0  
mA  
mA  
mA  
Peak Current during FOT Clock enabled, lux=0  
Peak Current during FOT Clock enabled, lux=bright  
Every module in the image sensor has its own power supply and  
ground. The grounds can be combined externally, but not all  
power supply inputs may be combined. Some power supplies  
must be isolated to reduce electrical crosstalk and improve  
shielding, dynamic range, and output swing. Internal to the  
image sensor, the ground lines of each module are kept separate  
to improve shielding and electrical crosstalk between them.  
maximum rated voltages in this high impedance circuit. Unused  
inputs must always be tied to an appropriate logic level, for  
example, VDD or GND. All cap_xxx pins must be connected to  
ground through a 100 nF capacitor.  
The recommended combinations of supplies are:  
■
■
Analog group of +2.5V supply: VSAMPLE, VRES_DS, VMEM_L  
VADC, Vpix, VANA, VBUF  
,
The LUPA 1300-2 contains circuitry to protect the inputs against  
damage due to high static voltages or electric fields. However,  
take normal precautions to avoid voltages higher than the  
Digital Group of +2.5V supply: VDIG, VLVDS  
Document Number: 001-24599 Rev. *C  
Page 6 of 41  
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CYIL2SM1300AA  
Table 5. Power Dissipation [3]  
These specifications apply for VDD = 2.5V, Clock = 315 MHz, 500 fps  
Parameter  
Condition  
no clock running  
lux = 0  
Typ  
Units  
mW  
Symbol  
Power down  
Average Power Dissipation  
400  
P
DOWN  
1350  
mW  
Power  
Table 6. AC Electrical Characteristics [3]  
The following specifications apply for VDD = 2.5V, Clock = 315 MHz, 500 fps.  
Parameter Condition  
Input Clock Frequency  
Typ  
Max  
Units  
Symbol  
FCLK  
fps = 500  
315  
MHz  
Clock Duty Cycle  
Frame rate  
At maximum clock  
50  
%
DCCLK  
fps  
Maximum clock speed  
500  
fps  
Sensor Architecture  
The floor plan of the architecture is shown in Figure 5. The sensor consists of a pixel array, analog front end, data block, and LVDS  
transmitters and receivers. Separate modules for the SPI, clock division, and sequencer are also integrated. The image sensor of  
1280 x 1024 pixels is read out in progressive scan.  
This architecture enables programmable addressing in the x-direction in steps of 24 pixels, and in the y-direction in steps of one pixel.  
The starting point of the address can be uploaded by the serial parallel interface (SPI).  
The AFE prepares the signal for the digital data block when the data is multiplexed and prepared for the LVDS interface.  
Figure 5. Floor Plan of the Sensor  
Image core  
1280 x 1024  
SPI  
24 analog channels  
24x 10-bit digital channels  
12x 10-bit digital channels  
31.5 Msps  
31.5 Msps  
63 Msps  
Sequencer  
&
Logic  
Clk X & Clk Y  
Analog front end  
31.5 MHz  
Clk in  
Clock  
Divider  
Local register  
Data block  
Clk out  
63 MHz  
LVDS TX and RX  
315 MHz  
12x LVDS outputs at 630 Msps  
Document Number: 001-24599 Rev. *C  
Page 7 of 41  
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CYIL2SM1300AA  
Windowing  
The 6T Pixel  
Windowing is easily achieved by SPI. The starting point of the x  
and y address and the window size can be uploaded. The  
minimum step size in the x-direction is 24 pixels (choose only  
multiples of 24 as start or stop addresses). The minimum step  
size in the y-direction is one line (every line can be addressed)  
in normal mode, and two lines in sub sampling mode.  
To obtain the global shutter feature combined with a high  
sensitivity and good parasitic light sensitivity (PLS), implement  
the pixel architecture shown in Figure 6. This pixel architecture  
is designed in a 14 µm x 14 µm pixel pitch. The pixel is designed  
to meet the specifications listed in Table 1 and Table 2 on page  
2. This architecture also enables pipelined or triggered mode, as  
shown in Figure 6.  
The section Sequencer on page 10 discusses the use of  
registers to achieve the desired ROI.  
Figure 6. 6T Pixel Architecture  
Table 8. Typical Frame Rates for 630 MHz Clock  
Vpix  
Vmem  
Image  
Resolution (X*Y)  
Frame Rate Frame Read  
(fps)  
Out Time (µs)  
Sample  
Select  
1296x1025  
640 x 512  
256 x 256  
507  
1970  
550  
1842  
6933  
Reset  
146  
Analog to Digital Converter  
The sensor has 24 10-bit pipelined ADCs on board. The ADCs  
nominally operate at 31.5 Msamples/s.  
Table 9. ADC Parameters  
Parameter  
Data rate  
Specification  
31.5 Msamples/s  
Frame Rate and Windowing  
Frame Rate  
Quantization  
DNL  
10 bit  
The frame rate depends on the input clock, the frame overhead  
time (FOT), and the row overhead time (ROT). The frame period  
is calculated by:  
Typ. < 1 DN  
Typ. < 1 DN  
INL  
Frame period = FOT+Nr. Lines * (ROT + Nr. Pixels * clock period)  
Programmable Gain Amplifiers  
Table 7. Frame Rate Parameters  
The PGAs amplify the signal before sending it to the ADCs.  
Parameter  
Comment  
Clarification  
The amplification inside the PGA is controlled by one SPI setting:  
afemode [5:3].  
FOT  
Frame Overhead Programmable: Default  
Time  
315 MHz granularity clock  
cycles (5 µs at 630 MHz)  
Six gain steps can be selected by the afemode<5:3> register.  
Table 10 lists the six gain settings. The unity gain selection of the  
PGA is done by the default afemode<5:3> setting.  
ROT  
Row Overhead  
Time  
Programmable: Default 13  
granularity clock cycles  
(206 ns at 630 MHz)  
Table 10. Gain Settings  
Nr. Lines  
Nr. Pixels  
Number of lines  
read out each  
frame  
afemode<5:3>  
Gain  
1
000  
001  
010  
011  
100  
101  
1.5  
2
Number of pixels  
read out each line  
Clock Period 1/63 MHz = 15.9 ns Every channel works at  
63 MHz Æ12 channels  
2.25  
3
result in 756 MHz data rate  
4
Example  
Readout of the full resolution at nominal speed (756 MHz pixel  
rate = 1.32 ns)  
Frame period = 5 µs + (1025 * (206 ns+1.32 ns*1296) = 1.97 ms  
=> 507 fps  
The real speed of the LUPA1300-2 is reduced to 500 fps,  
because overhead pixels are read out for black level calibration  
and other on board features.  
Document Number: 001-24599 Rev. *C  
Page 8 of 41  
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Operation and Signaling  
Digital Signals  
Depending on the operation mode (Master or Slave), the pixel array of the image sensor requires different digital control signals. The  
function of each signal is listed in this table.  
Table 11. Overview of Digital Signals  
Signal Name  
MONITOR_1  
I/O  
Comments  
Output pin for integration timing, high during integration  
Output pin for dual slope integration timing, high during integration  
Output pin for triple slope integration timing, high during integration  
Integration pin triple slope  
Output  
Output  
Output  
Input  
MONITOR_2  
MONITOR_3  
INT_TIME_3  
INT_TIME_2  
INT_TIME_1  
RESET_N  
CLK  
Input  
Integration pin dual slope  
Input  
Integration pin first slope  
Input  
Sequencer reset, active LOW  
Input  
System clock (630 MHz)  
SPI_CS  
Input  
SPI chip select  
SPI_CLK  
Input  
Clock of the SPI  
SPI_IN  
Input  
Data line of the SPI, serial input  
SPI_OUT  
Output  
Data line of the SPI, serial output  
Synchronous Shutter  
In a synchronous (snapshot or global) shutter, light integration occurs on all pixels in parallel, although subsequent readout is  
sequential. Figure 7 shows the integration and readout sequence for the synchronous shutter. All pixels are light sensitive at the same  
period of time. The whole pixel core is reset simultaneously, and after the integration time, all pixel values are sampled together on  
the storage node inside each pixel. The pixel core is read out line by line after integration. Note that the integration and readout cycle  
can occur in parallel or in sequential mode (pipelined or triggered). Refer to the section Image Sensor Timing and Readout on page 18.  
Figure 7. Synchronous Shutter Operation  
Line number  
Time axis  
Integration Time  
Burst Readout  
Document Number: 001-24599 Rev. *C  
Page 9 of 41  
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Non Destructive Readout (NDR)  
Figure 8. Principle of Non Destructive Readout  
time  
The sensor can also be read out in a nondestructive method. After a pixel is initially reset, it can be read multiple times, without being  
reset. You can record the initial reset level and all intermediate signals. High light levels saturate the pixels quickly, but a useful signal  
is obtained from the early samples. For low light levels, the later or latest samples must be used. Essentially, an active pixel array is  
read multiple times, and reset only once. The external system intelligence interprets the data. Table 12 on page 10 summarizes the  
advantages and disadvantages of nondestructive readout.  
Table 12. Advantages and Disadvantages of Non Destructive Readout  
Advantages  
Disadvantages  
Low noise, because it is true CDS  
System memory required to record the reset level and the  
intermediate samples  
High sensitivity. The conversion capacitance is kept low.  
Requires multiples readings of each pixel, so there is higher data  
throughput  
High dynamic range. The results include signals for short and Requires system level digital calculations  
long integration times.  
Note that the amount of samples taken with one initial reset is programmable in the nr_of_ndr_steps register. If nr_of_ndr_steps is  
one, the sensor operates in the default method, that is one reset and one sample. This is called the disable nondestructive read out  
mode.  
When nr_of_ndr_steps is two, there is one reset and two samples, and so on. In the slave mode, nothing changes on the protocol of  
the signals int_time_*. The sequencer suppresses the internal reset signal to the pixel array.  
Sequencer  
The sequencer generates the complete internal timing of the pixel array and the readout. The timing can be controlled by the user  
through the SPI register settings. The sequencer operates on the same clock as the data block. This is a division by 10 of the input  
clock (internally divided).  
Table 13 lists the internal registers. These registers are discussed in detail in the section Detailed Description of Internal Registers on  
page 15.  
Table 13. Internal Registers  
Block  
Register Name  
Address [6..0]  
Field Reset Value  
[7:0] 0x00  
Description  
Reserved, fixed value  
MBS (reserved) Fix1  
0
1
2
3
4
Fix2  
Fix3  
Fix4  
Fix5  
[7:0] 0xFF  
Reserved, fixed value  
Reserved, fixed value  
Reserved, fixed value  
Reserved, fixed value  
[7:0] 0x00  
[7:0] 0x00  
[7:0] ‘0x08’  
Document Number: 001-24599 Rev. *C  
Page 10 of 41  
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Table 13. Internal Registers (continued)  
Block  
LVDS clk  
divider  
Register Name  
Address [6..0]  
Field Reset Value  
Description  
lvdsmain  
5
[3:0] ‘0110’  
lvds trim  
[7:4]  
0
clkadc phase  
lvdspwd1  
lvdspwd2  
6
7
[7:0] 0x00  
Power down channel 7:0  
Power down channel 13:8  
Power down all channels  
lvds test mode  
[5:0]  
[6]  
0
0
0
[7]  
Fix6  
8
9
[7:0] 0x00  
[3:0] ‘1000’  
[2:0] ‘111’  
[5:3] ‘000’  
Reserved, fixed value  
afe current biasing  
AFE  
afebias  
afemode  
10  
vrefp, vrefm settings  
Pga settings  
[6]  
0
Power down AFE  
afepwd1  
afepwd2  
bandgap  
11  
12  
13  
[7:0] 0x00  
[3:0] 0x00  
Power down adc_channel_2x 7 to 0  
Power down adc_channel_2x 11 to 8  
Power down bandgap and currents  
External resistor  
Bias block  
[0]  
[1]  
[2]  
‘0’  
‘1’  
‘0’  
External voltage reference  
Bandgap trimming  
[5:3] ‘000’  
Image Core  
imcmodes  
14  
[0]  
[1]  
[2]  
[3]  
[4]  
[5]  
0
Power down  
‘1’  
‘1’  
0
Enable vrefcol regulator  
Enable precharge regulator  
Disable internal bias for vprech  
Disable column load  
‘1’  
‘0’  
clkmain invert  
Fix7  
15  
16  
17  
[7:0] 0x00  
[7:0] 0x00  
[3:0] ‘1000’  
[7:4] ‘1000’  
[3:0] ‘1000’  
[7:4] ‘1000’  
[3:0] ‘1000’  
[7:4] ‘1000’  
[3:0] ‘1000’  
[7:4] ‘1000’  
Reserved, fixed value  
Reserved, fixed value  
Bias colfpn DAC buffer  
Bias precharge regulator  
Bias pixel precharge level  
Bias column ota  
Fix8  
imcbias1  
imcbias2  
imcbias3  
Imcbias4  
18  
19  
20  
Bias column unip fast  
Bias column unip slow  
Bias column load  
Bias column precharge  
Document Number: 001-24599 Rev. *C  
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Table 13. Internal Registers (continued)  
Block  
Register Name  
Fix9  
Address [6..0]  
Field Reset Value  
[7:0] 0x20  
Description  
Reserved, fixed value  
Data Block  
21  
22  
23  
Fix10  
[7:0] 0xC0  
Reserved, fixed value  
Reserved, fixed value  
dataconfig1  
[1:0] 0x00  
[2]  
0
‘1’: Enables user upload of dacvrefadc register value  
‘0’: Keeps default value  
[3]  
[4]  
[5]  
0
0
0
Enable PRBS generation  
Reserved, fixed value  
Reserved, fixed value  
[7:6] 0x03  
[7:0] 0x2A  
Training pattern inserted to sync LVDS receivers  
Training pattern inserted to sync LVDS receivers  
Reserved, fixed value  
dataconfig2  
Fix11  
24  
25  
26  
27  
28  
29  
30  
[7:0]  
0
dacvrefadc  
Fix12  
[7:0] 0x80  
[7:0] 0x80  
[7:0]  
Input to DAC to set the offset at the input of the ADC  
Reserved, fixed value  
Fix13  
Reserved, fixed value  
Fix14  
[7:0]  
Reserved, fixed value  
datachannel0_1  
[0]  
[1]  
[2]  
0
0
0
Bypass the data block  
Enables the FPN correction  
Overwrite incoming ADC data by the data in the  
testpat register  
[3]  
0
Reserved, fixed value  
[5:4] 0x00  
[7:0] 0x00  
Pattern inserted to generate a test image  
Pattern inserted to generate a test image  
Bypass the data block  
datachannel0_2  
datachannel1_1  
31  
32  
[0]  
[1]  
[2]  
0
0
0
Enables the FPN correction  
Overwrite incoming ADC data by the data in the  
testpat register  
[3]  
0
Reserved, fixed value  
Data Block  
(continued)  
[5:4] 0x00  
[7:0] 0x00  
Pattern inserted to generate a test image  
Pattern inserted to generate a test image  
datachannel1_2  
datachannel12_1  
33  
54  
[0]  
[1]  
[2]  
0
0
0
Bypass the data block  
Enables the FPN correction  
Overwrite incoming ADC data by the data in the  
testpat register  
[3]  
0
Reserved, fixed value  
[5:4] 0x00  
[7:0] 0x00  
Pattern inserted to generate a test image  
Pattern inserted to generate a test image  
datachannel12_2  
55  
Document Number: 001-24599 Rev. *C  
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Table 13. Internal Registers (continued)  
Block  
Register Name  
Address [6..0]  
56  
Field Reset Value  
Description  
Enables image capture  
Sequencer  
seqmode1  
[0]  
[1]  
0
1
‘1’: Master mode, integration timing is generated  
on-chip  
‘0’: Slave mode, integration timing is controlled  
off-chip through INT_TIME1, INT_TIME2 and  
INT_TIME3 pins  
[2]  
0
‘0’: Pipelined mode  
‘1’: Triggered mode  
[3]  
[4]  
0
0
Enables(‘1’)/disables(‘0’) subsampling  
‘1’: Color subsampling scheme: 1:1:0:0:1:1:0:0  
‘0’: B&W subsampling scheme: 1:0:1:0:1  
[5]  
[6]  
[7]  
0
0
0
Enable dual slope  
Enable triple slope  
Enables continued row select (that is, assert row  
select during pixel read out)  
seqmode2  
seqmode3  
57  
58  
[4:0] ‘10000’  
[6:5] ‘00’  
Must be overwritten with‘10001’ to this register after  
startup, before readout.  
Number of active windows:  
“00”: 1 window  
“01”: 2 windows  
“10”: 3 windows  
“11”: 4 windows  
[0]  
‘1’  
Enables the generation of the CRC10 on the data  
and sync channels  
[1]  
[2]  
‘0’  
‘0’  
Not applicable  
Enable column fpn calibration  
[5:3] “001”  
Number of frames in nondestructive read out:  
“000”: invalid  
“001”: one reset, one sample (default mode)  
“010”: one reset, two samples  
…
[6]  
[7]  
0
0
Controls the granularity of the timer settings (only for  
those that have ‘granularity selectable’ in the  
description):  
‘0’: Expressed in number of lines  
‘1’: Expressed in clock cycles (multiplied by  
2**seqmode4[3:0])  
Allows delaying the syncing of events that happen  
outside of ROT to the next ROT. This avoids image  
artefacts.  
Document Number: 001-24599 Rev. *C  
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Table 13. Internal Registers (continued)  
Block  
Register Name  
Address [6..0]  
59  
Field Reset Value  
Description  
seqmode4  
[3:0] 0x00  
Multiplier factor (=2**seqmode4[3:0]) for the timers  
when working in clock cycle mode  
[5:4] 0x0  
Selects the source signals to put on the digital test  
pins (monitor pins):  
“00”: integration time settings  
“01”: EOS signals  
“10”: frame sync signals  
“11”: functional test mode  
[6]  
[7]  
‘0’  
‘0’  
Reverse read out in X direction  
Reverse read out in Y direction  
Y start address for window 1  
Y start address for window 1  
X start address for window 1  
Y end address for window 1  
Y end address for window 1  
X width for window 1  
window1_1  
window1_2  
60  
61  
[7:0] 0x00  
[1:0] 0x00  
[7:2] 0x00  
[7:0] 0xFF  
[1:0] 0x3  
window1_3  
window1_4  
62  
63  
[7:2] 0x36  
[7:0] 0x00  
[1:0] 0x00  
[7:2] 0x00  
[7:0] 0xFF  
[1:0] 0x3  
window2_1  
window2_2  
64  
65  
Y start address for window 2  
Y start address for window 2  
X start address for window 2  
Y end address for window 2  
Y end address for window 2  
X width for window 2  
window2_3  
window2_4  
66  
67  
[7:2] 0x36  
[7:0] 0x00  
[1:0] 0x00  
[7:2] 0x00  
[7:0] 0xFF  
[1:0] 0x3  
window3_1  
window3_2  
68  
69  
Y start address for window 3  
Y start address for window 3  
X start address for window 3  
Y end address for window 3  
Y end address for window 3  
X width for window 3  
window3_3  
window3_4  
70  
71  
[7:2] 0x36  
[7:0] 0x00  
[1:0] 0x00  
[7:2] 0x00  
[7:0] 0xFF  
[1:0] 0x3  
window4_1  
window4_2  
72  
73  
Y start address for window 4  
Y start address for window 4  
X start address for window 4  
Y end address for window 4  
Y end address for window 4  
X width for window 4  
window4_3  
window4_4  
74  
75  
[7:2] 0x36  
[7:0] 0x02  
[7:0] 0x00  
[7:0] 0x01  
res_length1  
res_length2  
76  
77  
Length of pix_rst (granularity selectable)  
Length of pix_rst (granularity selectable)  
res_dsts_length 78  
Length of resetds and resetts (granularity  
selectable)  
tint_timer1  
79  
80  
81  
[7:0] 0xFF  
[7:0] 0x03  
[7:0] 0x40  
Length of integration time (granularity selectable)  
Length of integration time (granularity selectable)  
tint_timer2  
tint_ds_timer1  
Length of DS integration time (granularity  
selectable)  
tint_ds_timer2  
tint_ts_timer1  
tint_ts_timer2  
82  
83  
84  
[1:0] 0x00  
[7:0] 0x0C  
[1:0] 0x00  
Length of DS integration time (granularity  
selectable)  
Length of TS integration time (granularity  
selectable)  
Length of TS integration time (granularity  
selectable)  
Document Number: 001-24599 Rev. *C  
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Table 13. Internal Registers (continued)  
Block Register Name Address [6..0]  
tint_black_timer 85  
Field Reset Value  
[7:0] 0x06  
Description  
Reserved, fixed value  
rot_timer  
86  
87  
88  
89  
90  
91  
[7:0] 0x0D  
[7:0] 0x36  
Length of ROT (granularity clock cycles)  
fot_timer  
Length of FOT (granularity clock cycles)  
fot_timer  
[1:0] 0x01  
Length of FOT (granularity clock cycles)  
prechpix_timer  
prechpix_timer  
prechcol_timer  
[7:0] 0x7C  
[1:0] 0x00  
Length of pixel precharge (granularity clock cycles)  
Length of pixel precharge (granularity clock cycles)  
[7:0] 0x03  
Length of column precharge (granularity clock  
cycles)  
rowselect_timer 92  
[7:0] 0x09  
[7:0] 0xF8  
[1:0] 0x00  
[7:0] 0x10  
[1:0] 0x01  
Length of rowselect (granularity clock cycles)  
Length of pixel_sample (granularity clock cycles)  
Length of pixel_sample (granularity clock cycles)  
Length of pixel_vmem (granularity clock cycles)  
Length of pixel_vmem (granularity clock cycles)  
sample_timer  
sample_timer  
vmem_timer  
vmem_timer  
93  
94  
95  
96  
delayed_rdt_timer 97  
[7:0]  
0
Readout delay for testing purposes (granularity  
selectable)  
delayed_rdt_timer 98  
[7:0]  
0
Readout delay for testing purposes (granularity  
selectable  
Fix29  
Fix30  
Fix31  
Fix32  
Fix33  
Fix34  
99  
[0]  
[0]  
[0]  
[0]  
[0]  
[0]  
0
0
0
0
0
0
Reserved, fixed value  
100  
101  
102  
103  
104  
Reserved, fixed value  
Reserved, fixed value  
Reserved, fixed value  
Reserved, fixed value  
Reserved, fixed value, write 0x4 to it  
Detailed Description of Internal Registers  
Biasing Block  
The registers must be changed only during idle mode, that is,  
when seqmode1[0] is ‘0’. Uploaded registers have an immediate  
effect on how the frame is read out. Parameters uploaded during  
readout may have an undesired effect on the data coming out of  
the images.  
This block contains several registers for setting biasing currents  
for the sensor. Default values after startup must remain  
unchanged for normal operation of the sensor.  
Image Core Block  
The registers in this block have an impact on the pixel array itself.  
Default settings after startup must remain unchanged for normal  
operation of the image sensor.  
MBS Block  
The register block contains registers for sensor testing and  
debugging. All registers in this block must remain unchanged  
after startup.  
Data Block  
The data block is positioned in between the analog front end  
(output stage + ADCs) and the LVDS interface. It muxes the  
outputs of 2 ADCs to one LVDS block and performs some minor  
data handling:  
LVDS Clock Divider Block  
This block controls division of the input clock for the LVDS  
transmitters or receivers. This block also enables shutting down  
one or all LVDS channels. For normal operation, this register  
block must remain untouched after startup.  
■
■
CRC calculation and insertion  
Training and test pattern generation  
AFE Block  
The most important registers in this block are:  
This register block contains registers to shut down ADC  
channels or the complete AFE block. This block also contains the  
register for setting the PGA gain: AFE_mode[5:3]. Refer to  
Electrical Specifications on page 5 for more details on the PGA  
settings.  
Dataconfig. The dataconfig1[7:6] and dataconfig2[7:0] registers  
insert a training pattern in the LVDS channels to sync the LVDS  
receivers.  
Document Number: 001-24599 Rev. *C  
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Datachannels. DatachannelX_1 and DatachannelX_2 (with  
X=0 to 12) are registers that allow you to enable or disable the  
FPN correction (DatachannelX_1[1]), and generate a test  
Seqmode3[6]: Controls the granularity of the timer settings (only  
for those that have 'granularity selectable' in the description). As  
a result, all timer settings are set either in number of applied clock  
cycles, or in the number of 'readout lines'.  
pattern  
if  
necessary  
(datachannelX_1[5:4]  
and  
datachannelX_2[7:0]).  
'0': expressed in number of lines  
Sequencer Block  
'1': expressed in clock cycles (multiplied by 2**seqmode4 [3:0])  
The sequencer block group registers allow enabling or disabling  
image sensor features that are driven by the onboard sequencer.  
This block consists of the following registers:  
Seqmode3[7]: Allows syncing of events that happen outside of  
ROT to be delayed to the next ROT to avoid image artifacts.  
Seqmode4. This register consists of four subregisters:  
Seqmode1. The seqmode1 registers have the following  
subregisters:  
Seqmode4[3:0]: Multiplier factor (2**seqmode4[3:0]) for the  
timers when working in clock cycle mode.  
Seqmode1[0]: Enables image capture, must be '1' during image  
acquisition.  
Seqmode4[5:4]: Selects the source signals to be put on the  
digital test pins (monitor1, monitor2, and monitor3 pins)  
Seqmode1[1]: This subregister has two modes:  
"00": integration time settings  
'1': In this default mode the integration timing is generated  
on-chip.  
"01": EOS signals  
"10": frame sync signals  
'0': In this slave mode, the integration timing must be generated  
through the int_time1, int_time2, and int_time3 pins.  
"11": functional test mode  
Seqmode1[2]: This bit enables pipelined (0) or triggered (1)  
mode.  
Seqmode4[6]: Enables (1) and disables (0) reverse X read out.  
Seqmode4[7]: Enables (1) and disables (0) reverse Y read out.  
Seqmode1[3]: Enable (1) or disable (0) subsampling.  
Y1_start (60 and 61, 10 bit). These registers set the Y start  
address for window 1 (default window).  
Seqmode1[4]: This bit sets the type of subsampling scheme  
used when subsampling is enabled.  
X1_start (61, 6bit). This register sets the X start address for  
window 1 (default window).  
'1': Color (1:1:0:0:1:1:0:0:1…)  
'0': Black and White (1:0:1:0:1)  
Y1_end (62 and 63, 10 bit). These registers set the Y end  
Seqmode1[5]: This bit enables or disables the dual slope  
integration.  
address for window 1 (default window).  
X1_kernels (63, 6 bit). This register sets the number of kernels  
or X width to be read out for window 1 (default window).  
Seqmode1[6]: This bit enables or disables the triple slope  
integration.  
Y2_start (64 and 65, 10 bit). These registers set the Y start  
address for window 2 (if enabled).  
Seqmode2. The seqmode2 register consists of only two  
subregisters:  
X2_start (65, 6bit). This register sets the X start address for  
window 2 (if enabled).  
Seqmode2[4:0]: Default value after startup is '10000', but this  
must be overwritten with the new value '10001' immediately after  
startup.  
Y2_end (66 and 67, 10 bit). These registers set the Y end  
address for window 2 (if enabled).  
Seqmode3[6:5]: These two bits set the number of active  
windows:  
X2_kernels (67, 6 bit). This register sets the number of kernels  
or X width to be read out for window 2 (if enabled).  
'00': 1 window  
Y3_start (68 and 69, 10 bit). These registers set the Y start  
address for window 3 (if enabled).  
'01': 2 windows  
'10': 3 windows  
'11': 4 windows (max)  
X3_start (69, 6bit). This register sets the X start address for  
window 3 (if enabled).  
Seqmode3. The seqmode3 register consists of the following  
subregisters:  
Y3_end (70 and 71, 10 bit). These registers set the Y end  
address for window 3 (if enabled).  
Seqmode3[0]: This bit enables or disables the CRC10  
generation on the data and sync channels  
X3_kernels (71, 6 bit). This register sets the number of kernels  
or X width to be read out for window 3 (if enabled).  
Seqmode3[1]: Enables or disables black level calibration  
Seqmode3[2]: Enables or disables column FPN correction  
Y4_start (72 and 73, 10 bit). These registers set the Y start  
address for window 4 (if enabled).  
Seqmode3[5:3]: Enables or disables, and sets the number of  
frames grabbed in nondestructive readout mode.  
X4_start (73, 6bit). This register sets the X start address for  
window 4 (if enabled).  
'000': Invalid  
Y4_end (74 and 75, 10 bit). These registers set the Y end  
'001': Default, 1 reset, 1 sample  
'010': 1reset, 2 samples  
'011': 1 reset, 3 samples  
address for window 4 (if enabled).  
X4_kernels (75, 6 bit). This register sets the number of kernels  
or X width to be read out for window 4 (if enabled).  
Document Number: 001-24599 Rev. *C  
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Res_length (76 and 77). This register sets the length of the  
internal pixel array reset (how long are all pixel reset  
simultaneously). This value is expressed in 'number of lines' or  
in clock cycles (depends on seqmode3[6]).  
The interface consists of:  
■
■
■
■
cs_n: chip select, when LOW the chip is selected  
clk: the spi clock  
Res_dsts_length. This register sets the length of the internal  
dual and triple slope reset pulses when enabled. This value is  
expressed in 'number of lines' or in clock cycles (depends on  
seqmode3[6]).  
in: Master out, Slave in, the serial input of the register  
out: Master in, Slave out, the serial output of the register  
SPI Protocol  
Tint_timer (79 and 80). This register sets the length of the  
integration time. This value is expressed in 'number of lines' or  
in clock cycles (depends on seqmode3[6]).  
The information on the data 'in' line is:  
■
■
■
A command bit C, indicating a write ('1') or a read ('0') access  
7-bit address  
Tint_ds_timer (81 and 82). This register sets the length of the  
dual slope integration time. This value is expressed in 'number  
of lines' or in clock cycles (depends on seqmode3[6]).  
8-bit data word (in case of a write access)  
The data 'out' line is generally in High Z mode, except when a  
read request is performed.  
Tint_ts_timer (83 and 84). This register sets the length of the  
triple slope integration time. This value is expressed in 'number  
of lines' or in clock cycles (depends on seqmode3[6]).  
Data is always written on the bus on the falling edge of the clock,  
and sampled on the rising edge, as seen in Figure 9 and  
Figure 10. This is valid for both the 'in' and 'out' bus. The system  
clock must be active to keep the SPI uploads stored on the chip.  
The SPI clock speed must be slower by a factor of 30 when  
compared to the system clock (315 MHz nominal speed).  
Data Interface (SPI)  
The serial 4-wire interface (or Serial to Parallel Interface) uses a  
serial input or output to shift the data in or out the register buffer.  
The chip's configuration registers are accessed from the outside  
world through the SPI protocol. A 4-wire bus runs over the chip  
and connects the SPI I/Os with the internal register blocks.  
Figure 9. Write Access (C='1')  
The 'out' line is held to High Z. The data for the address A is transferred from the shift register to the active register bank (that is,  
sampled) on a rising edge of cs_n. Only the register block with address A can write its data on the 'out' bus. The data on 'in' is ignored.  
Figure 10. Read Access (C='0')  
Document Number: 001-24599 Rev. *C  
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Image Sensor Timing and Readout  
The timing of the sensor consists of two parts. The first part is  
related to the exposure time and the control of the pixel. The  
second part is related to the read out of the image sensor.  
Integration and readout are in parallel or triggered. In the first  
case, the integration time of frame I is ongoing during the readout  
of frame I-1. Figure 11 shows this parallel timing structure.  
groups of 24 (12 on rising edge, and 12 on the falling edge of the  
internal clock). So in total, 54 kernels of 24 pixels are read out  
every line. The internal timing is generated by the sequencer.  
The sequencer can operate in two modes: master mode and  
slave mode. In master mode, all internal timing is controlled by  
the sequencer, based on the SPI settings. In slave mode, the  
integration timing is directly controlled by over three pins, and the  
readout timing is still controlled by the sequencer. The  
seqmode1[1] register of the SPI selects between the master and  
slave modes.  
The readout of every frame starts with a FOT, during which the  
analog value on the pixel diode is transferred to the pixel memory  
element. After this FOT, the sensor is read out line by line. The  
read out of every line starts with a ROT, during which the pixel  
value is put on the column lines. Then the pixels are selected in  
Figure 11. Global Readout Timing (Parallel)  
Integration frame I+1  
Integration frame I+2  
Readout frame I  
Readout Lines  
Readout frame I+1  
L2  
L1024  
K54  
FOT  
ROT  
L1  
...  
K2  
K1  
...  
Readout Pixels  
Pipelined Shutter  
Integration and readout occur in parallel and are continuous. You only need to start and stop the batch of image captures.  
Integration of frame N is always ongoing during readout of frame N-1. The readout of every frame starts with a FOT, during which the  
analog value on the pixel diode is transferred to the pixel memory element. After this FOT, the sensor is read out line by line. The  
readout of every line starts with a ROT, during which the pixel value is put on the column lines. Then the pixels are muxed in the correct  
ADCs, processed, and then sent to the LVDS output block.  
Figure 12. Integration and Readout for Pipelined Shutter  
Int. Time  
Handling  
Reset  
N+1  
Exposure Time N  
Exposure Time  
Readout N  
Reset N  
Readout  
Handling  
Readout N-1  
FOT  
FOT  
ROT  
Line Readout  
You have two options in the pipelined shutter mode. The first option is to program the reset and integration through the configuration  
interface and let the sequencer handle integration time automatically. This mode is called master mode. The second option is to drive  
the integration time through an external pin. This mode is called slave mode.  
Document Number: 001-24599 Rev. *C  
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Programming the Exposure Time  
In master mode, the exposure time is configured in two distinct methods (controlled by register seqmode3[6]):  
■
■
#lines: Obvious, changing signals that control integration time. They are always changed during ROT to avoid any image artefacts.  
#clockcycles:Mustbemultipliedby(2**seqmode4[3:0]).Whenthecounterexpires,changesareputintoeffectimmediately.Asserting  
the configuration signal (seqmode3[7]) forces delaying signal updates until the next ROT.  
Table 14 lists the user programmable timer settings and how they are interpreted by the hardware.  
Table 14. User Programmable Timer Settings  
Setting  
reg_res_length  
Granularity  
Lines/cycles  
reg_tint_timer  
Lines/cycles  
Lines/cycles  
Lines/cycles  
clock cycles  
clock cycles  
clock cycles  
clock cycles  
clock cycles  
clock cycles  
Lines/cycles  
reg_tint_ds_timer  
reg_tint_ts_timer  
reg_rot_timer  
reg_fot_timer  
reg_sel_pre_timer  
reg_precharge_timer  
reg_sample_timer  
reg_vmem_timer  
reg_delayed_rdt_timer  
Note that the seqmode3[7] can also be used to sync the user signals in slave mode. The behavior is exactly the same.  
Master Mode  
In master mode the reset and exposure time is written in registers.  
Figure 13. Integration and Image Readout in Master Mode  
Ensure that the added value of the registers res_length and tint_timer always exceeds the number of lines that are read out. This is  
because the sequencer samples a new image after integration is complete, without checking if image readout is finished. Enlarging  
res_length to accommodate for this has no impact on image capture.  
Document Number: 001-24599 Rev. *C  
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Slave Mode  
In slave mode, the register values of res_length and tint_timer are ignored. The integration time is controlled by the int_time pin. The  
relationship between the input pin and the integration time is shown in Figure 14. When the input pin int_time is asserted, the pixel  
array goes out of reset and exposure can begin. When int_time goes low again and the desired exposure time is reached, the image  
is sampled and read out can begin.  
Figure 14. Integration and Image Readout in Slave Mode  
Changing a pixel's reset level during line readout might result in image artefacts during a small transient period. As a result, it is advised  
to only change the value of int_time during ROT.  
Triggered Shutter  
The two main differences in the pipelined shutter mode are:  
■
■
One single image is read upon every user action.  
Integration (and read out) is under control of the user through pin int_time.  
This means that for every frame, you need to manually intervene. The pixel array is kept in reset state until you assert the int_time  
input. Similar to the pipelined shutter mode, there is a master mode in which the sequencer can control the integration time, or a slave  
mode in which you can define the integration time.  
Figure 15. Integration and Readout for Triggered Shutter  
int_time1  
Int. Time  
Reset  
Exposure Time N Reset  
Exposure Time N  
FOT  
Reset  
Handling  
Readout  
Handling  
Read  
FOT  
Readout N  
outN+1  
ROT  
Line  
Readout  
The possible applications for this triggered shutter mode are:  
■
■
Synchronize external flash with exposure  
Apply extremely long integration times (only in slave mode)  
Document Number: 001-24599 Rev. *C  
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Master Mode  
Slave Mode  
In this mode, a rising edge on int_time1 pin is used to trigger the  
start of integration and read out. The tint_timer defines the  
integration time independent of the assertion of the input pin  
int_time1. After the integration time counter runs out, the FOT  
automatically starts and the image readout is done. During  
readout, the image array is kept in reset. A request for a new  
frame is started again when a new rising edge on int_time is  
detected. The time of the falling edge is not important in this  
mode.  
Integration time control is identical to the pipelined shutter slave  
mode. The int_time1 pin controls the start of integration. When  
int_time is deasserted, the FOT starts (analog value on the pixel  
diode is transferred to the pixel memory element). Only at that  
time, image read out can start (similar to the pipelined read out).  
During read out, the image array is kept in reset. A request for a  
new frame is started when int_time goes high again.  
Windowing  
A fully configurable window can be selected for readout.  
Figure 16. Window Selected for Readout  
y start  
1024 pixels  
y_end  
x kernel  
x start  
1280 pixels  
The parameters to configure this window are:  
y_end. The end line of the readout window, granularity of 1. In  
all cases (even in reverse scan), y_end are larger than y_start.  
Note that in subsample mode, the correct y_end position must  
be uploaded (exact value depends on color or B/W subsampling  
mode). This value must be written to the windowX_3 and  
windowX_4 register.  
x_start. The sensor reads out 24 pixels in one single clock cycle.  
The granularity of configuring the X start position is also 24.  
Every value written to the windowX_2 register must be multiplied  
by 24 to find the corresponding column in the pixel array.  
x_kernels. The number of columns that is read out  
(x_kernels*24 in full frame mode) in subsampling mode  
x_kernels*48 represents the number of columns over which  
subsampling is done. The x_kernels value must be written to the  
windowX_4 register.  
In case of windowing, the effective readout time is smaller than  
in full frame mode, because only the relevant part of the image  
array is accessed. As a result, it is possible to achieve higher  
frame rates.  
y_start. The starting line of the readout window, granularity of 1.  
Note that in subsample mode, the correct y_start position must  
be uploaded (exact value depends on color or B/W subsampling  
mode). This value must be written to the windowX_1 and  
windowx_2 register.  
Document Number: 001-24599 Rev. *C  
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Reverse Scan  
Reverse scanning is supported in the X and Y direction. Line 0 (first line on the output) is the top line in normal mode and the bottom  
line in reverse scanning, as shown in Figure 17. As a result, the line numbers always increment. When reverse scanning in X, the  
operation is analogous. To enable reverse readout in X and Y, set the seqmode4[6:7] bits. In addition, the Y_start and X_start  
addresses must be changed to the new starting address.  
Figure 17. Normal and Reverse Scanning in Y  
Multiple Windows  
The sequencer supports the readout of four different windows, randomly positioned over the pixel array. The images are read out  
sequentially. That is, window 1 is read out before window 2, even if both windows show some overlap. Next, windows 3 and 4 are  
read out. You can configure the number of windows used in the application (one to four). Figure 18 shows how to configure two  
windows spread over the image array.  
Figure 18. Multiple Windows Read from the Same Pixel Array  
Document Number: 001-24599 Rev. *C  
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Figure 19 shows the sequence of integration and read out for multiple windows. The handling of integration time is identical to the  
single window mode (except that in this case, the maximum integration time is equal to the sum of the y_widths of the two windows).  
Read out starts with a FOT that is similar to single window mode. After the FOT, all lines of window 1 are read, followed by the lines  
of window 2.  
Figure 19. Exposure and Read Out of Multiple Windows  
Int. Time  
Handling  
Reset  
N+1  
Reset N  
Exposure Time N  
Exposure Time  
Readout  
Handling  
Readout  
N-1  
Readout N-1  
Readout N Readout N  
FOT  
FOT  
Window 2  
Window 1  
Window 1  
ROT  
Line Readout  
Line Readout Window 2  
If the X size of the windows are not identical, the integration time  
in function of the number of lines read presents multiple slopes  
(proportional to the X size of these windows). Because this can  
cause confusion when programming the integration time, it is  
easier to configure all timer registers using the clock cycle  
configuration instead of the 'line' configuration.  
slope capabilities, the pixels p3 and p4 are saturated before the  
end of the exposure time, and no signal is received. However,  
when using multiple slopes, the analog signal is reset to a  
second or third reset level (lower than the original) before the  
integration time ends. The analog signal starts decreasing with  
the same slope as before, and pixels that were saturated before  
could be nonsaturated at read out time. For pixels that never  
reach any of the reset levels (for example, p1 and p2) there is no  
difference between single and multiple slope operation.  
Multiple Slopes  
Dynamic range can be extended by the multiple slope  
capabilities of the sensor. The four colored lines in Figure 20  
represent analog signals of the photodiode of four pixels, which  
decrease as a result of exposure. The slope is determined by the  
amount of light at each pixel (the more light, the steeper the  
slope). When the pixels reach the saturation level, the analog  
does not change despite further exposure. Without the multiple  
By choosing the time stamps of the double and triple slope resets  
(typical at 90% and 99% of the integration, configurable by the  
user), it is possible to have a nonsaturated pixel value even for  
pixels that receive a huge amount of light.  
Figure 20. Dynamic Range Extended by Multiple Slope Capability  
t
Document Number: 001-24599 Rev. *C  
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The reset levels are configured through external (power) pins. In master mode, the time stamps of the double and triple slope resets  
are configured in a method similar to configuring the exposure time. The time stamps are enabled through the registers seqmode1[5]  
and seqmode1[6], and their values are expressed in line or clock cycles in the registers reg_tint_ds_timer and reg_tint_ts_timer.  
Figure 21. Triple Slope Timing in Master Mode  
In slave mode, the values of res_length, tint_timer, tint_DS_timer, and tint_TS_timer in the configuration registers are ignored. You  
have full control through the pins int_time, int_time_ds, and int_time_ts. You must configure the multiple slope parameters for the  
application and interpret the pixel data accordingly.  
Figure 22. Triple Slope Timing in Slave Mode  
Document Number: 001-24599 Rev. *C  
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■
datachannelX_1 with X from 0 to 11. The field [1] of these  
registers enables the offset corrections of the specific output  
channel.  
Column FPN Correction  
The column FPN of the sensor is improved by the offset  
correction of the columns. At the start of every frame, before read  
out of the actual lines is done, a fixed voltage is applied at the  
columns and these values are read out like a real data line. Inside  
the data block, the 'pixel' data for that line is stored in an on-chip  
FPN memory. When the correction is enabled, the corresponding  
FPN value is subtracted from the incoming pixel data.  
Note Do not change the settings of datachannel12_1. This  
channel contains synchronization data, not pixel data. If fpn  
correction is enabled on this channel, the synchronization data  
becomes corrupt.  
■
seqmode3. The field[2] must be '1'. It enables the generation  
of the line of reference voltages at the columns.  
This FPN correction must be enabled for every output separately.  
The registers used to configure the correction are:  
Figure 23 and Figure 24 show the effect of enabling the column  
FPN correction. These images are magnified up to five times.  
Figure 23. Dark Image Without FPN Correction (5x Amplified)  
Figure 24. Dark Image With FPN Correction Enabled (5x Amplified)  
Document Number: 001-24599 Rev. *C  
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Image Format and Read Out Protocol  
The active area read out by the sequencer in full frame mode is shown in Figure 25. Before the actual pixels are read out, one dummy  
line is read to enable column FPN calibration. A reference voltage is applied to the columns and the entire line is read as if real pixel  
values are placed on the columns.  
Pixels are always read in multiples of 24 (one value to every channel in the AFE). The last time slot contains not only valid pixels, but  
also two dummy columns, six grey columns, and eight black columns.  
Figure 25. Sensor Read Out Format  
Document Number: 001-24599 Rev. *C  
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The following sections discuss the appearance of the output (data and synchronization codes) in several relevant configurations.  
Twelve output channels are connected to the 24 ADCs and handle the data. One additional channel contains all the synchronization  
codes for the receiver. This indicates, for example, the start of a frame, the end of a frame, whether the data channels contain data,  
CRC, a training pattern, and so on. The sequencer provides the synchronization channel with the correct synchronization or protocol  
signals, as shown in Figure 26. The synchronization codes are listed in Table 15. Note that a FS also serves as LS, and vice versa.  
Figure 26. Data and Sync Channel Overview  
Table 15. Synchronization Codes  
Sync code  
Frame Start  
Abbreviation  
10-Bit Code  
0x059  
0x056  
0x05A  
0x055  
0x0A9  
0x0A6  
0x13C  
0x193  
T
FS  
LS  
Line Start  
Frame End  
Line End  
FE  
LE  
Grey/Black Cols  
CRC  
GBC  
CRC  
FPN  
D
FPN stored values  
Normal Data  
Training Pattern  
T
Document Number: 001-24599 Rev. *C  
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Full Frame Mode  
In this operation mode, the entire sensor shown in Figure 25 on page 26 is read out. Figure 27 shows the internal state of the  
sequencer, and the behavior of the data and sync channels (overview and detail of one line).  
Figure 27. Full Frame Mode Read Out  
Sequencer  
internal state  
ROT  
ROT  
line  
1022  
line  
FOT ROT black ROT line 0  
line 1  
1023  
Data channel  
Sync Channel  
Data Channel  
Sync Channel  
T
T
T
D
D
D
D
L
GB  
D
D
D
CR  
C
T
FS  
E
C
timeslot timeslot timeslot  
timeslot timeslot  
53 54  
CRC  
timeslot  
2
3
1
Document Number: 001-24599 Rev. *C  
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This table provides a detailed overview of remapping one full row read out.  
Table 16. Remapping Scheme for One Row  
timeslot  
1a  
ch0  
0
ch1  
2
ch2  
4
ch3  
6
ch4  
8
ch5  
10  
ch6  
12  
ch7  
14  
ch8  
16  
ch9  
18  
ch10  
20  
ch11  
22  
1b  
1
3
5
7
9
11  
13  
15  
17  
19  
21  
23  
2a  
47  
45  
43  
41  
39  
37  
35  
33  
31  
29  
27  
25  
2b  
46  
44  
42  
40  
38  
36  
34  
32  
30  
28  
26  
24  
3a  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
3b  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
4a  
95  
93  
91  
89  
87  
85  
83  
81  
79  
77  
75  
73  
4b  
94  
92  
90  
88  
86  
84  
82  
80  
78  
76  
74  
72  
5a  
96  
98  
100  
101  
139  
138  
148  
149  
187  
186  
196  
197  
235  
234  
244  
245  
283  
282  
...  
102  
103  
137  
136  
150  
151  
185  
184  
198  
199  
233  
232  
246  
247  
281  
280  
...  
104  
105  
135  
134  
152  
153  
183  
182  
200  
201  
231  
230  
248  
249  
279  
278  
...  
106  
107  
133  
132  
154  
155  
181  
180  
202  
203  
229  
228  
250  
251  
277  
276  
...  
108  
109  
131  
130  
156  
157  
179  
178  
204  
205  
227  
226  
252  
253  
275  
274  
...  
110  
111  
129  
128  
158  
159  
177  
176  
206  
207  
225  
224  
254  
255  
273  
272  
...  
112  
113  
127  
126  
160  
161  
175  
174  
208  
209  
223  
222  
256  
257  
271  
270  
...  
114  
115  
125  
124  
162  
163  
173  
172  
210  
211  
221  
220  
258  
259  
269  
268  
...  
116  
117  
123  
122  
164  
165  
171  
170  
212  
213  
219  
218  
260  
261  
267  
266  
...  
118  
119  
121  
120  
166  
167  
169  
168  
214  
215  
217  
216  
262  
263  
265  
264  
...  
5b  
97  
99  
6a  
143  
142  
144  
145  
191  
190  
192  
193  
239  
238  
240  
241  
287  
286  
...  
141  
140  
146  
147  
189  
188  
194  
195  
237  
236  
242  
243  
285  
284  
...  
6b  
7a  
7b  
8a  
8b  
9a  
9b  
10a  
10b  
11a  
11b  
12a  
12b  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
53a  
53b  
54a  
54b  
CRC  
1248  
1249  
1295  
1294  
1250  
1251  
1293  
1292  
1252  
1253  
1291  
1290  
1254  
1255  
1289  
1288  
1256  
1257  
1287  
1286  
1258  
1259  
1285  
1284  
1260  
1261  
1283  
1282  
1262  
1263  
1281  
1280  
1264  
1265  
1279  
1278  
1266  
1267  
1277  
1276  
1268  
1269  
1275  
1274  
1270  
1271  
1273  
1272  
Document Number: 001-24599 Rev. *C  
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Single Window Mode Containing Timeslot 54  
In this operation mode, only part of the sensor is read out, as shown by the shaded area in Figure 28. A clear distinction is made with  
the single window mode that does not contain the timeslot 54, because the output synchronization protocol is slightly different.  
Figure 28. Single Window Containing Timeslot 54  
Figure 29 shows the internal state of the sequencer, and the behavior of the data and sync channels (overview and detail of one line)  
for this window mode.  
Figure 29. Waveform for Single Window Containing Timeslot 54  
Line  
Ys+1  
FOT  
ROT  
ROTline Ye  
ROT  
black ROT  
line Ys  
Sequencer internal state  
Data Channel  
Sync Channel  
T
T
Data Channel  
Sync Channel  
T
T
GB  
C
D
D
F
E
CR  
C
L
S
D
D
D
timeslot timeslot  
timeslot timeslot  
X+1  
CRC  
timeslot  
X
53  
54  
Document Number: 001-24599 Rev. *C  
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Single Window Mode Not Containing Timeslot 54  
In this operation mode, only part of the sensor is read out, as shown in Figure 30. Although the window is defined as not containing  
any data from timeslot 54, it is read out to provide information on grey and black columns to the user. This results in some minor  
differences between the waveforms from Figure 29 on page 30 and Figure 31.  
Figure 30. Single Window Not Containing Timeslot 54  
Figure 31 shows the internal state of the sequencer, and the behavior of the data and sync channels (overview and detail of one line)  
for this window mode.  
Figure 31. Waveform for Single Window NOT Containing Timeslot 54  
Sequencer  
internal state  
ROT  
ROT  
FOT  
black  
line Ys  
line  
Ys  
+1  
ROTline Ye  
ROT  
Data Channel  
Sync Channel  
T
T
T
T
GB CR  
T
L
D
D
D
D
L
D
D
S
E
C
C
timeslot timeslot  
Xstart  
timeslot timeslot timeslot CRC  
Xend-1 Xend 54 timeslot  
Note that the dummy black line is read completely.  
Reading out multiple windows does not differ from combining the windowed modes in sections Single Window Mode Containing  
Timeslot 54 on page 30 and Single Window Mode Not Containing Timeslot 54. The dummy black line again spans the entire width of  
the sensor and is processed only once, before all configured windows are read. The dummy black line is independent of the window  
sizes.  
Document Number: 001-24599 Rev. *C  
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Pin List  
Table 17. Pin Placement Layout (Top View)  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24  
A 134 130 127 124 121 118 115 112 109 106 103 100 99 96 93 90 87 84 81 78 75 72 69 65  
131 128 125 122 119 116 113 110 107 104 101 98 95 92 89 86 83 80 77 74 71 68  
B
*
*
C 133 132 129 126 123 120 117 114 111 108 105 102 97 94 91 88 85 82 79 76 73 70 67 66  
D
E
F
G
H
J
K
TOP VIEW  
L
M
N
P
Q
R
S
T 135 139 140 137 145  
U 136 144 141 138 146  
*
*
5
8
9
7
6
*
*
17 19  
20 18  
*
*
*
*
31 29  
30 32  
*
*
43 41  
42 44  
*
*
54 62 60 59 64  
53 61 55 58 63  
V 149 147 142  
W 150 148 143  
*
*
1
2
3
4
11 13 15 21 23 25 27 33 35 37 39 45 47  
*
*
52 57 50  
51 56 49  
10 12 14 16 22 24 26 28 34 36 38 40 46 48  
Document Number: 001-24599 Rev. *C  
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Table 18. Pin List  
nr Pin Name  
Type  
LVDS  
LVDS  
LVDS  
LVDS  
Supply  
Supply  
Supply  
Supply  
LVDS  
LVDS  
LVDS  
LVDS  
LVDS  
LVDS  
LVDS  
LVDS  
Supply  
Supply  
Supply  
Supply  
LVDS  
LVDS  
LVDS  
LVDS  
LVDS  
LVDS  
LVDS  
LVDS  
Supply  
Supply  
Supply  
Supply  
LVDS  
LVDS  
LVDS  
LVDS  
LVDS  
LVDS  
Direction  
O
Description  
Position  
V5  
1
2
3
4
5
6
7
8
9
clkoutp  
clkoutn  
chp[0]  
chn[0]  
gndlvds  
gndadc  
vddadc  
vddlvds  
chp[1]  
chn[1]  
chp[2]  
chn[2]  
chp[3]  
chn[3]  
chp[4]  
chn[4]  
gndlvds  
gndadc  
vddadc  
vddlvds  
chp[5]  
chn[5]  
chp[6]  
chn[6]  
chp[7]  
chn[7]  
chp[8]  
chn[8]  
gndlvds  
gndadc  
vddadc  
vddlvds  
chp[9]  
chn[9]  
chp[10]  
chn[10]  
chp[11]  
chn[11]  
n/a  
p clk output channel  
n clk output channel  
p output channel [0]  
n output channel [0]  
LVDS ground  
O
W5  
O
V6  
O
W6  
I/O  
I/O  
I/O  
I/O  
O
T7  
ADC ground  
U8  
ADC power  
T8  
LVDS power  
U7  
p output channel [1]  
n output channel [1]  
p output channel [2]  
n output channel [2]  
p output channel [3]  
n output channel [3]  
p output channel [4]  
n output channel [4]  
LVDS ground  
V7  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
O
W7  
O
V8  
O
W8  
O
V9  
O
W9  
O
V10  
W10  
T10  
U11  
T11  
U10  
V11  
W11  
V12  
W12  
V13  
W13  
V14  
W14  
T15  
U14  
T14  
U15  
V15  
W15  
V16  
W16  
V17  
W17  
V18  
W18  
T18  
U17  
O
I/O  
I/O  
I/O  
I/O  
O
ADC ground  
ADC power  
LVDS power  
p output channel [5]  
n output channel [5]  
p output channel [6]  
n output channel [6]  
p output channel [7]  
n output channel [7]  
p output channel [8]  
n output channel [8]  
LVDS ground  
O
O
O
O
O
O
O
I/O  
I/O  
I/O  
I/O  
O
ADC ground  
ADC power  
LVDS power  
p output channel [9]  
n output channel [9]  
p output channel [10]  
n output channel [10]  
p output channel [11]  
n output channel [11]  
not assigned  
O
O
O
O
O
n/a  
not assigned  
gndlvds  
gndadc  
Supply  
Supply  
I/O  
I/O  
LVDS ground  
ADC ground  
Document Number: 001-24599 Rev. *C  
Page 33 of 41  
[+] Feedback  
CYIL2SM1300AA  
Table 18. Pin List (continued)  
nr Pin Name  
43 vddadc  
Type  
Direction  
Description  
Position  
T17  
Supply  
Supply  
LVDS  
I/O  
I/O  
I
ADC power  
LVDS power  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
vddlvds  
clkinp  
U18  
V19  
W19  
V20  
W20  
W24  
V24  
W22  
V22  
U20  
T20  
LVDS input clock 315 MHz p-node  
LVDS input clock 315 MHz n-node  
LVDS sync and output  
LVDS sync and output  
digital ground  
clkinn  
LVDS  
I
syncp  
LVDS  
O
syncn  
LVDS  
O
gnddig  
Supply  
Supply  
Analog  
Analog  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Analog  
CMOS  
CMOS  
CMOS  
CMOS  
CMOS  
CMOS  
I/O  
I/O  
O
vdddig  
digital power supply  
cap_vrefm  
cap_vrefp  
gndadc  
vddadc  
gnddig  
lower limit ADC range decoupling  
higher limit ADC range decoupling  
ADC ground  
O
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
ADC power supply  
digital ground  
U22  
W23  
V23  
U23  
T23  
gndbuf  
column buffers ground  
column buffers supply  
column buffers ground  
column buffers supply  
pixel core supply  
vddbuf  
gndana  
vddana  
vpix  
T22  
gndpix  
pixel core ground  
U21  
T21  
vsamp  
image core select and sample supply  
ADC ground  
gndadc  
vdddig  
U24  
T24  
digital power supply  
nbias_colload  
test_ena  
int_time1  
int_time2  
int_time3  
monitor1  
monitor2  
column bias decouple  
scan pin for sequencer  
integration pin first slope  
integration pin dual slope  
integration pin triple slope  
A24  
C24  
C23  
B23  
A23  
I
I
I
I
O
output pin for integration timing, high during integration  
C22  
B22  
O
output pin for dual slope integration timing, high during  
integration  
72  
monitor3  
CMOS  
O
output pin for triple slope integration timing, high during  
integration  
A22  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
cap_vrefadc  
vpix  
Analog  
Supply  
Analog  
CMOS  
CMOS  
CMOS  
CMOS  
Supply  
Supply  
Supply  
Supply  
O
I/O  
O
ADC black reference decoupling  
pixel core supply  
C21  
B21  
A21  
C20  
B20  
A20  
C19  
B19  
A19  
C18  
B18  
cap_vrefcm  
reset_n  
scan_en  
scan_clk  
scan_clk_en  
gndpix  
ADC common mode decoupling  
chip reset (active low)  
DFT scan enable  
I/O  
I
I
DFT clock  
I
DFT clock enable  
I/O  
I/O  
I/O  
I/O  
pixel core ground  
gnddig  
digital ground  
vdddig  
digital power supply  
pixel core supply  
vpix  
Document Number: 001-24599 Rev. *C  
Page 34 of 41  
[+] Feedback  
CYIL2SM1300AA  
Table 18. Pin List (continued)  
nr Pin Name  
84 pixdiode  
Type  
Direction  
O
Description  
Position  
A18  
C17  
B17  
A17  
C16  
B16  
A16  
C15  
B15  
A15  
C14  
B14  
A14  
C13  
B13  
A13  
A12  
B12  
C12  
A11  
B11  
C11  
A10  
B10  
C10  
A9  
Analog  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
pixel diode current pin  
pixel core ground  
85  
gndpix  
vsamp  
vresetab  
vprech  
vmemh  
vmeml  
vreset  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
86  
image core select and sample supply  
anti blooming lower reset level  
pixel precharge level/decoupling pin  
pixel memory reference high  
pixel memory reference low  
pixel reset level  
87  
88  
89  
90  
91  
92  
vresetds  
vresetts  
vresetab  
gndpix  
vresetts  
vresetds  
vreset  
pixel dual slope reset level/decoupling pin  
pixel triple slope reset level/decoupling pin  
anti blooming lower reset level  
pixel core ground  
93  
94  
95  
96  
pixel triple slope reset level/decoupling pin  
pixel dual slope reset level/decoupling pin  
pixel reset level  
97  
98  
99  
vsamp  
vmeml  
vmemh  
vprech  
n/a  
image core select and sample supply  
pixel memory reference low  
pixel memory reference high  
pixel precharge level/decoupling pin  
not assigned  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
gndpix  
vresetab  
vresetts  
vresetds  
vreset  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Analog  
Supply  
Supply  
Supply  
Supply  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
pixel core ground  
anti blooming lower reset level  
pixel triple slope reset level/decoupling pin  
pixel dual slope reset level/decoupling pin  
pixel reset level  
vmeml  
vmemh  
vprech  
vresetab  
vsamp  
gndpix  
ibiaspre  
vpix  
pixel memory reference low  
pixel memory reference high  
pixel precharge level/decoupling pin  
anti blooming lower reset level  
image core select and sample supply  
pixel core ground  
B9  
C9  
A8  
B8  
C8  
external current bias for vprech (not connected by default) A7  
I/O  
I/O  
I/O  
I/O  
pixel core supply  
digital power supply  
digital ground  
B7  
C7  
A6  
B6  
C6  
A5  
B5  
C5  
A4  
B4  
C4  
vdddig  
gnddig  
gndpix  
n/a  
pixel core ground  
not assigned  
n/a  
not assigned  
n/a  
not assigned  
n/a  
not assigned  
cap_vrefcm  
vpix  
Analog  
Supply  
Analog  
O
I/O  
O
ADC common mode decoupling  
pixel core supply  
ADC black reference decoupling  
cap_vrefadc  
Document Number: 001-24599 Rev. *C  
Page 35 of 41  
[+] Feedback  
CYIL2SM1300AA  
Table 18. Pin List (continued)  
nr Pin Name  
127 spics  
Type  
Direction  
I
Description  
Position  
A3  
CMOS  
CMOS  
CMOS  
CMOS  
Analog  
Analog  
Analog  
Analog  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Analog  
Analog  
Supply  
Supply  
SPI chip select  
SPI clock  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
spiclk  
I
B3  
spiin  
I
SPI serial input  
SPI serial output  
C3  
A2  
spiout  
O
mbsbus[0]  
mbsbus[1]  
refbg  
I/O  
I/O  
I/O  
I
first mixed boundary scan bus  
second mixed boundary scan bus  
external bias resistor  
bias current for mbs buffers  
digital power supply  
B2  
C2  
C1  
A1  
cmdmbs  
vdddig  
gndadc  
vsamp  
gndpix  
vpix  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
T1  
ADC ground  
U1  
T4  
image core select and sample supply  
pixel core ground  
U4  
T2  
pixel core supply  
vddana  
gndana  
vddbuf  
gndbuf  
gnddig  
vddadc  
gndadc  
cap_vrefp  
cap_vrefm  
vdddig  
gnddig  
analog power supply  
analog ground  
T3  
U3  
V3  
column buffers supply  
column buffers ground  
digital ground  
W3  
U2  
T5  
ADC power supply  
ADC ground  
U5  
V2  
higher limit ADC range decoupling  
lower limit ADC range decoupling  
digital power supply  
W2  
V1  
digital ground  
W1  
Document Number: 001-24599 Rev. *C  
Page 36 of 41  
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CYIL2SM1300AA  
Package Information  
Figure 32. Package Outline Drawing with Glass  
001-44705 **  
The total distance from the bottom of the µPGA package (same as the PCB plane) to the top of the die surface is 19.016 mm.  
Document Number: 001-24599 Rev. *C  
Page 37 of 41  
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CYIL2SM1300AA  
Figure 33. Pixel Active Area Dimensions  
Package with Glass Cross Section  
Figure 34. Package Cross Section  
Document Number: 001-24599 Rev. *C  
Page 38 of 41  
[+] Feedback  
CYIL2SM1300AA  
Die Specifications  
Figure 35. Die Specifications  
1700 ±  
50 um  
1450  
± 50  
um  
Document Number: 001-24599 Rev. *C  
Page 39 of 41  
[+] Feedback  
CYIL2SM1300AA  
Glass Lid  
The LUPA 1300-2 monochrome and color image sensor uses a glass lid without any coatings. Figure 36 shows the transmission  
characteristics of the glass lid.  
As seen in Figure 36, no infrared attenuating color filter glass is used. You must provide this filter in the optical path when color devices  
are used.  
Figure 36. Transmission Characteristics of the Glass lid  
Handling Precautions  
Application Note References  
For proper handling and storage conditions, refer to the Cypress  
application note AN52561 at www.cypress.com.  
■
AN54468: Interfacing the LUPA1300-2 with FPGA.  
This application note describes the interface between the LUPA  
1300-2 and the FPGA, as implemented in the LUPA 1300-2  
demonstration kit CYIL2SM1300-EVAL. It also provides an  
overview of the architecture of the demonstration kit and the  
method used to synchronize channels.  
Limited Warranty  
Cypress Image Sensor Business Unit warrants that the image  
sensor products mentioned here, if properly used and serviced,  
conform to the seller's published specifications. They are free  
from defects in material and workmanship for one (1) year  
following the date of shipment.  
■
AN54214: High Speed Layout Guidelines for the LUPA 1300-2  
Image Sensor  
Document Number: 001-24599 Rev. *C  
Page 40 of 41  
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CYIL2SM1300AA  
Document History Page  
Document Title: CYIL2SM1300AA LUPA 1300-2: High Speed CMOS Image Sensor  
Document Number: 001-24599  
Revision  
ECN  
Orig. of Change Submission Date  
Description of Change  
Initial Cypress release.  
**  
1438663  
2649816  
FPW  
09/04/07  
*A  
NVEA/AESA  
03/17/2009  
Updated parameters in Table 4 on page 5.  
Updated data sheet template.  
Added Handling Precautions section.  
*B  
*C  
2745961  
2765859  
NVEA/AESA  
NVEA/AESA  
07/29/2009  
09/18/2009  
Updated “Features” on page 1, “Description” on page 1, and  
“Overview” on page 2  
Updated Table on page 1  
Updated Table 13 on page 10  
Modified “Handling Precautions” on page 40  
Added “Application Note References” on page 40  
Updated Ordering Information table  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress offers standard and customized CMOS image sensors for consumer as well as industrial and professional applications.  
Consumer applications include solutions for fast growing high speed machine vision, motion monitoring, medical imaging, intelligent  
traffic systems, security, and barcode applications. Cypress's customized CMOS image sensors are characterized by very high pixel  
counts, large area, very high frame rates, large dynamic range, and high sensitivity.  
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. For more  
information on Image sensors, please contact imagesensors@cypress.com.  
© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used  
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use  
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support  
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-24599 Rev. *C  
Revised September 18, 2009  
Page 41 of 41  
All products and company names mentioned in this document may be the trademarks of their respective holders.  
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