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SZMD24C

型号:

SZMD24C

描述:

瞬态电压抑制器ESD保护[ Transient Voltage Suppressors for ESD Protection ]

品牌:

SECOS[ SECOS HALBLEITERTECHNOLOGIE GMBH ]

页数:

2 页

PDF大小:

205 K

SZMD24C  
100W, 24 V  
Transient Voltage Suppressors  
for ESD Protection  
Elektronische Bauelemente  
RoHS Compliant Product  
A suffix of “-C” specifies halogen & lead-free  
SOT-23  
FEATURES  
A
L
z
z
z
z
SOT-23 package for surface mount application  
Protects 24V components  
Protects two unidirectional line or one bi-direction line  
Provides electrically is olated protection  
3
3
Top View  
C B  
1
1
2
2
K
F
E
D
G
H
J
APPLICATIONS  
z
z
z
z
z
Cellular Handsets and Accessories  
Portable devices  
Industrial Controls  
Set -Top Box  
Millimeter  
Millimeter  
Min. Max.  
0.10 REF.  
0.55 REF.  
REF.  
REF.  
Min.  
Max.  
3.00  
2.55  
1.40  
1.15  
A
B
C
D
2.80  
2.25  
1.20  
0.90  
G
H
J
0.08  
0.15  
K
0.5 REF.  
E
F
1.80  
0.30  
2.00  
0.50  
L
0.95 TYP.  
Servers, Notebook, and Desktop PC  
1
3
2
Marking Code  
KDQ  
ABSOLUTE RATINGS (Tamb = 25°C )  
Rating  
Symbol  
Value  
Units  
IEC 61000-4-2 (ESD)  
Air contact  
Contact discharge  
±15  
±8  
kV  
kV  
ESD voltage  
Per human body model  
16  
kV  
Total power dissipation on FR-5 Board (Note 1) @ TA=25℃  
Junction and storage temperature range  
Lead solder temperature – maximum (10 Second duration)  
PD  
TJ, TSTG  
TL  
150  
-55 ~ +150  
m/W  
°C  
°C  
260  
Stresses exceeding Maximum Ratings may damage the device. Maximum Rating are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.  
1. FR-5 = 1.0*0.75*0.62 in.  
ELECTRICAL CHARACTERISTICS  
(Ratings at 25°C ambient temperature unless otherwise specified. VF = 0.9V at IF = 10mA)  
VC (V)  
@ Max IPP  
(Note 3)  
Max  
IPP  
(A)  
(Note 3)  
Max  
2.0  
C
(pF)  
(Note 4)  
Typ  
VRWM  
(V)  
IR(uA)  
@ VRWM  
V
BR (V)  
IT  
PPK  
(W)*  
Device  
@ IT (Note 2) (mA)  
Max  
24  
Max  
0.1  
Min  
28  
mA  
5.0  
Max  
100  
SZMD24C  
43  
18  
Other voltages available upon request.  
2. VBR is measured with a pulse test current IT at an ambient temperature of 25  
3. Surge current waveform per Figure 3.  
4. Measured at 1MHz 0V.  
http://www.SeCoSGmbH.com/  
Any changes of specification will not be informed individually.  
01-June-2002 Rev. A  
Page 1 of 2  
SZMD24C  
100W, 24 V  
Transient Voltage Suppressors  
for ESD Protection  
Elektronische Bauelemente  
RATINGS AND CHARACTERISTICS CURVES  
Clamping Voltage vs. Peak Pulse Current  
Power Derating Curve  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
60  
Waveform  
Parameters  
tr = 8µs  
td = 20µS  
50  
40  
30  
20  
10  
0
0
1
2
3
0
25  
50  
75  
100  
125  
150  
Peak Pulse Current - IPP (A)  
o
Ambient Temperature - TA ( C)  
Applications Information  
Pulse Waveform  
110  
Device Connection Options  
The SZMD series is designed to protect one  
Wave form  
Paramete rs:  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
tr = 8  
s
bi-directional or two uni-directional data or l/O lines  
operating at 24 volts.Connection options are as  
follows:  
Bidirectional:Pin 1 is connected to the data line and  
pin 2 is connected to ground (Since the device lls  
symmetrical,these conmtions may be re- Ver3ed).For  
best results,the ground connection should be made  
directly to a ground plane on the board.The path  
length should be kept as short as possible to minimize  
parasitic inductance-Pin 3 is not  
connected. Unidirectional:Data lines are connected  
to pin1 and pin2.Pin 3 is connected to ground.For  
best results,this pin should be connected directly to a  
ground plane on the board.The path lengh should be  
kept as short as possible to minimize parasitic  
inductance. Circuit Board Layout Recommendations  
for suppres- sion of ESD. Good circuit board layout is  
critical for the suppression of fast rise-time transients  
such as ESD.The following guidelines are  
td = 20  
s
e-t  
td = IPP /2  
0
5
10  
15  
20  
25  
30  
Time (us)  
recommended (Refer to application note Sl99.01 for  
more detailed information): Place the TVS near the  
input terminals or connec- tors to restrict transient  
coupling. Minimize the path length between the  
TVS and the protected line. Minimize all conductive  
loops including power and ground loops. The ESD  
transient return path toground should be kept as short  
as possible. Never run critical signals near board  
edges  
Use ground planes whenever possib|e.  
http://www.SeCoSGmbH.com/  
Any changes of specification will not be informed individually.  
01-June-2002 Rev. A  
Page 2 of 2  
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