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IXTP70N075T2

型号：

IXTP70N075T2

描述：

DC到DC同步转换器设计[ DC to DC Synchronous Converter Design ]

品牌：

IXYS[ IXYS CORPORATION ]

页数：

11 页

PDF大小：

200 K

下载PDF手册
DC to DC Synchronous Converter Design  
Abdus Sattar, IXYS Corporation  
IXAN0068  
Modern power electronics products require small size and lighter weight of power  
electronics parts. Filter inductor and capacitor sizes must be small. With the small filter,  
the switching semiconductor devices must have small switching loss. And heat sink also  
must be reduced. For the safe operation with the small heat sink, the switching  
semiconductor devices must have small conduction loss. IXYS developed new generation  
of Trench MOSFET (Trench2TM), which has small gate charge and low on-resistance.  
The MOSFET will be well suited for high power applications of synchronous DC to DC  
converters used in various systems. The MOSFET is rugged and has avalanche energy  
capability.  
Table 1: Few Examples of IXYS TrenchT2TM N-Channel Power MOSFETs  
Vdss  
(max) Tc=25C  
(V) (A)  
Id  
@
Rds(on)  
@
Ciss  
(pF)  
Qg  
(nC  
)
trr @  
Tj=  
R(th)JC  
(°C/W)  
Pd  
Package  
Type  
Part Number  
EAS  
(mJ)  
(W)  
Tj=25°C  
(Ω)  
25°C  
(ns)  
600  
600  
300  
300  
400  
400  
600  
600  
300  
300  
400  
400  
IXTA220N04T2  
IXTP220N04T2  
IXTA90N055T2  
IXTP90N055T2  
IXTA110N055T2  
IXTP110N055T2  
IXTA200N055T2  
IXTP200N055T2  
IXTA70N075T2  
IXTP70N075T2  
IXTA90N075T2  
IXTP90N075T2  
360  
360  
150  
150  
180  
180  
360  
360  
150  
150  
180  
180  
TO‐263  
TO‐220  
TO‐263  
TO‐220  
TO‐263  
TO‐220  
TO‐263  
TO‐220  
TO‐263  
TO‐220  
TO‐263  
TO‐220  
40  
220  
0.0035  
0.0035  
0.0084  
0.0084  
0.0066  
0.0066  
0.0042  
0.0042  
0.012  
6500 112  
6500 112  
45  
45  
37  
37  
38  
38  
49  
49  
48  
48  
50  
50  
0.42  
0.42  
1.0  
40  
55  
55  
55  
55  
55  
55  
75  
75  
75  
75  
220  
90  
2670  
2670  
3060  
3060  
42  
42  
57  
57  
90  
1.0  
110  
110  
200  
200  
70  
0.82  
0.82  
0.42  
0.42  
1.0  
6800 109  
6800 109  
2580  
2580  
3100  
3100  
46  
46  
54  
54  
70  
0.012  
1.0  
90  
0.010  
0.82  
0.82  
90  
0.010  
DC-to-DC Synchronous Converter Design:  
Figure 1: Synchronous Buck Converter using IXYS TrenchT2TM Power MOSFET  
1
DC to DC Synchronous Converter Design  
Abdus Sattar, IXYS Corporation  
IXAN0068  
In Figure 1, the Q1 is called the high-side or control FET and Q2 is called the  
low-side or sync FET applied in a step-down DC to DC synchronous converter  
application. The ratio Vo /Vin is controlled by the duty cycle of Q1. To improve the  
efficiency, it’s desirable to have Q2 turned ON when Q1 is turned OFF. A simplified  
switch state diagram is shown in Figure 2 [2]. It depicts the switching sequence as A-B-  
C-B-A where the state B called “dead time” when both Q1 and Q2 are OFF and the  
Schottky diode, D1 is ON to provide the freewheeling operation in the inductive load  
circuit. It’s desirable to reduce the dead time to a minimum to improve the efficiency.  
However, if the dead time is lower than the turn-on or turn-off times of Q1 and Q2, the  
circuit may go into state D, the shoot-through state when both Q1 and Q2 are ON at the  
same time causing a short-circuit in the input voltage source, Vin. The state D is  
undesirable since it would destroy transistors Q1 and Q2.  
Figure 2: Circuit Switch State Diagram [2]  
2
DC to DC Synchronous Converter Design  
Abdus Sattar, IXYS Corporation  
IXAN0068  
Figure 3: Ideal Circuit waveforms (with no dead time)  
1
The Switching Period, TS = Ton +Toff , the Switching frequency, fS =  
TS  
Ton  
Ton  
TS Ton + Toff  
Turn-off time, Toff = (1− D)TS .  
The duty cycle, D =  
=
, Turn-on time, Ton = DTS  
Figure 4: Ideal synchronous buck converter inductor current  
An output DC voltage with lowest ripple is considered the best solution. Ripple appears  
in the output voltage as the L1 current’s ripple component, ΔIL1 (t) , which charges and  
discharges the output capacitor, C1, as shown in Figure 4. C1 is charged during the  
3
DC to DC Synchronous Converter Design  
Abdus Sattar, IXYS Corporation  
IXAN0068  
period when IL1 (t) is greater than Io. The charge (ΔQ ) that flows into C1 at this time  
divided by the value of C1 is the output voltage ripple component.  
Output Inductor Ripple Current and Voltage:  
The inductor voltage can be defined as,  
di  
Δt(Vin −Vo)  
L1  
VL = L1 = Vin −Vo , or, Δi = ΔIL1 (t) =  
, here, Δt = Ton = DTs  
dt  
The inductor ripple current is,  
Vin −Vo D(Vin −Vo)  
ΔIL1 (t) = DTs  
=
(1)  
L1  
fS • L1  
The charge, ΔQ , indicated in Figure 5, can be determined by calculating the area of the  
ΔIL1 (t)  
Ts  
triangle with height  
and width  
shown in Figure 5.  
2
2
ΔIL1 (t) TS ΔIL1 (t) •T S ΔIL1 (t)  
1
2
ΔQ =  
•
•
=
=
2
2
8
8 fS  
The ripple voltage is,  
ΔQ  
C1  
D(1− D)VinTs2 π 2 (1− D)Vo  
ΔIL1 (t)Ts  
f
ΔVL (t) =  
=
=
=
(
C )2 = ΔVO (t)  
(2)  
8C1  
8L1C1  
2
fS  
1
Where, fC =  
, Output low pass filter (LPF) resonant frequency, fS = The  
2π L1C1  
switching frequency. The inductor value of L1 and the effective series resistance (ESR)  
of the output capacitor, C1, affect the output ripple voltage, ΔVL . A capacitor with the  
lowest possible ESR is recommended for the application. For example, 4.7–10 uF  
capacitors in X5R/X7R technology have ESR approximately 10 mΩ..  
Summary of design equations:  
Ripples voltage/current, Inductor and Capacitor:  
ΔIL1 (t)Ts ΔIL1 (t)  
Output ripple voltage, ΔVL (t) =  
=
(3)  
8C1  
8C1fS  
Inductor ripple current, ΔIL1 (t) = 8C1fS • ΔVL (t)  
Vin −Vo D(Vin −Vo)  
(4)  
(5)  
Output inductor, L1 ≥ DTs  
=
ΔIL1 (t)  
fS • ΔIL1 (t)  
ΔIL1  
8 fs ΔVo  
ΔIL1 (t)  
1
Ts  
Output capacitor, C1 ≥  
since ΔQ = •  
•
= C1• ΔVo (6)  
2
2
2
1
Output filter cut-off frequency, fC =  
(7)  
2π L1C1  
4
DC to DC Synchronous Converter Design  
Abdus Sattar, IXYS Corporation  
IXAN0068  
Overview of Synchronous Converter Power Loss: [1]  
The losses in the synchronous converter’s power switches can be defined by:  
P
= P + P + P + PBD  
(8)  
Total  
C
SW  
Gate  
Where PC is the conduction loss, Psw is the switching power loss, PGate is the gate drive  
loss and PBD is the body diode loss. In addition, inductor equivalent DC resistance losses  
and output capacitor’s ESR loss play significant role in the converter design.  
MOSFET Q1 and Q2’s Power Loss: [1]  
The conduction losses: (replace D to 1-D for Sync FET, Q2):  
P = (IO D) 2 • RDS(on)  
(9)  
C
The gate-charge losses:  
Pg−C = VGS •Qg • fs  
(10)  
The switching losses:  
Figure 5: Transitions waveforms of MOSFET for inductive load  
The switching loss is,  
= P + P  
P
Switching  
t(on)  
t(off )  
[VDS(max){IDS(on) •tt(on) + IDS(off ) •tt(off )}• fs ]  
=
(11)  
2
MOSFET Body Diode Loss: [1]  
The body diode loss is a function of dead time and in every switching cycle; there are two  
dead-time intervals, td1 and td2. The dead-time is defined as the time required when both  
the MOSFETs Q1 and Q2 are OFF in order to prevent shoot-through.  
5
DC to DC Synchronous Converter Design  
Abdus Sattar, IXYS Corporation  
IXAN0068  
We can write as:  
PBD = P + P  
(12)  
td1  
td 2  
Where Ptd1 is the body diode loss during dead time td1 and Ptd2 is the body diode loss  
during dead time td2.  
ΔIL  
2
1
⎛
⎞
⎟
P = P + P = V • I −  
•td1• f + •V • I •t • f  
(13)  
(14)  
⎜
td1  
cd1  
rr1  
f
O
S
in  
rr  
rr  
S
2
⎝
⎠
ΔIL  
2
⎛
⎞
⎟
P
= P  
(
P = 0  
)
= V • I +  
•td2 • f  
⎜
td 2  
cd 2  
rr2  
f
O
S
⎝
⎠
PWM Gate Driver Power loss: [1]  
The power dissipation in the driver is defined by,  
PDRIVER = QG(onl) •VDD • fS  
(15)  
where Qg(onl) is the total gate charge of the MOSFET and VDD is the driver power supply.  
The gate “point of voltage” is,  
IO  
VSP = VTH  
+
(16)  
g fs  
The driver current is,  
VDD −VSP  
RDRIVER(PULL−UP) + RGate  
VDD −VSP  
IDRIVER(L−H )  
IDRIVER(H −L)  
=
=
(17)  
(18)  
RDRIVER(PULL−DOWN ) + RGate  
The rise time is,  
QG(on)  
tt(on)  
=
(19)  
(20)  
IDRIVER(L−H )  
The fall time is,  
QG(on)  
tt(off )  
=
IDRIVER(H −L)  
If an external Schottky diode (D1) is used across Q2, the Schottky’s capacitance needs to  
be charged during Q1 turn-on. The power loss to charge the Schottky’s capacitance is,  
CSCHOTTKY •VIN2 • fS  
P
=
(21)  
C(SCHOTTKY )  
2
6
DC to DC Synchronous Converter Design  
Abdus Sattar, IXYS Corporation  
IXAN0068  
Design Example 1:  
Assume design parameters as VIN=12V, VO=3.3V and Io=12A.  
Table 1: Design Consideration 1 for synchronous buck converter  
Input Voltage, Vin  
Output Voltage, Vo  
Output Current, Io  
12V  
3.3V  
12A  
Assume the output ripple voltage is within ± 1% of Vo. For Vo =3.3V, the output ripple  
is limited within, ΔVL (t) ≤ 0.033V . When the output capacitor (C1) is 10uF, the inductor  
L1 values for the range of switching frequencies from 100 kHz to 500 kHz are given in  
Table: 2 based on equations 3-7.  
Table 2: When C1= 10uF  
Vin Vo  
(V) (V)  
ΔVL  
(V)  
fs  
(kHz)  
C1  
(uF)  
ΔΙL1  
(A)  
L1  
(uH)  
fc  
(kHz)  
D
12 3.3 0.275 0.033  
12 3.3 0.275 0.033  
12 3.3 0.275 0.033  
12 3.3 0.275 0.033  
12 3.3 0.275 0.033  
100  
10  
0.264  
90  
45.31  
30.20  
22.65 10.60  
18.12 11.83  
5.31  
7.48  
9.16  
200  
300  
400  
500  
10  
10  
10  
10  
0.528  
0.792  
1.056  
1.32  
Synchronous Driver Controller: ISL6594D from Intersil:  
Based on equation 18 and 19, From ISL6594D driver datasheet, given high-side: tr=26nS,  
tf=18nS and source/sink current = 1.25/2A (max). For low-side, trr=18nS, tf=12nS and  
source/sink current = 2/3.0 A (max):  
Table 4: from Datasheet  
High-Side  
Rise time  
Source Current (A) Required Qg(on)  
Source  
Sink  
26 ns  
18 ns  
1.25  
2
32.5nC  
36nC  
Low-Side  
Rise time  
Source Current (A) Required Qg(on)  
Source  
Sink  
18nS  
12ns  
2
3
36nC  
36nC  
7
DC to DC Synchronous Converter Design  
Abdus Sattar, IXYS Corporation  
IXAN0068  
ISL6594D Specification:  
Recommended devices for this application:  
1. IXTA90N055T2  
VDS = 55V, Id25=90A  
Qg(on) = 42nC, Qgs = 14nC, Qgd = 8.5nC,  
td(on) = 19nS, tr = 21nS, td(off) = 39nS, tf = 19nS.  
Rds(on) = 8.4mΩ  
Vgs(th) = 2-4V, gfs = 43  
Ciss = 2670pF, Coss = 420pF, Crss = 100pF  
Or,  
1. IXTA110N055T2  
Vds = 55V, Id25=110A  
Qg(on) = 57nC, Qgs = 16nC, Qgd = 11nC,  
td(on) = 18nS, tr = 25nS, td(off) = 40nS, tf = 23nS.  
Rds(on) = 6.6mΩ , Vgs(th) = 2-4V, gfs = 49  
Ciss = 3060pF, Coss = 497pF, Crss = 105pF  
Analysis based on Above IXTA90N055T2:  
14nC  
QG(SW ) = 8.5nC +  
= 15.5nC  
2
IO  
15  
43  
The “point of voltage” is defined by, VSP = VTH  
+
= 3 +  
= 3.35V  
g fs  
The driver current is,  
VDD −VSP  
RDRIVER(PULL−UP) + RGate  
10 − 3.35 6.65  
IDRIVER(L−H )  
=
=
=
= 1.33A  
3 + 2  
5
8
DC to DC Synchronous Converter Design  
Abdus Sattar, IXYS Corporation  
IXAN0068  
VDD −VSP  
RDRIVER(PULL−DOWN ) + RGate  
10 − 3.35  
2.2 + 2  
IDRIVER(H −L)  
=
=
= 1.58A  
The rise time is, tt(on) = 26nS +10nS = 36nS  
The fall time is, tt(off ) = 18ns +10nS = 28nS  
High-Side MOSFET loss (Q1=IXTA90N055T2):  
The conduction loss is,  
P
= IO2 • RDS (on) • D  
Cond _ Q1  
= 122 • 0.0084 • 0.275 = 0.332 = 332mW  
The Gate-Charge losses: (assume fs = 200 kHz)  
PGC _ Q1 = VGS • Qg • fs = 10.0x42x10−9 x200x103 = 84mW  
And estimated switching loss is,  
[VDS(max){IDS (on) •tt(on) + IDS (off ) •tt(off )}• fs ]  
Pt =  
2
12 •12  
=
• (36 + 28)x10−9 x200x103 = 0.921W=921mW  
2
Total high-side losses: 332mW+84mW+921mW = 1337mW=1.337W  
Low-Side MOSFET loss (Q2):  
The conduction loss is,  
P
= IO2 • RDS(on) • (1− D)  
Cond _ Q2  
= 122 • 0.0084 • 0.725 = 0.877W = 877mW  
The Gate-Charge loss:  
PGC _ Q1 = VGS • Qg • fs = 10.0x42x10−9 x200x103 = 84mW  
Total low-side losses: 877mW+84mW =961mW  
ISL6594D Driver loss:  
From datasheet: VDD = 5V  
Table 6: IXS839 Driver Output Stage from datasheet  
Driver pull up resistance  
Driver pull down resistance RDRIVER(PULL_DOWN) 2.2Ω  
Driver gate resistance RGATE 2Ω  
RDRIVER(PULL_UP)  
3.0Ω  
9
DC to DC Synchronous Converter Design  
Abdus Sattar, IXYS Corporation  
IXAN0068  
The power dissipation in the driver is defined by,  
TJ − Ta  
RthJC  
PDRIVER  
=
= QG(total) •VDD • fSW  
where VDD = 10V and fS = 200 kHz (assume for this case)  
The estimated driver power dissipation, PD ≈ 42 •10−9 •10 • 200 •103 = 84mW  
Dead-Time Power Loss: [3]  
The dead-time is defined as the time required when both the MOSFETs are off in order to  
prevent shoot-through. In this period, the Schottky diode (or integral body diode is  
forward-biased and provided a power loss defined by,  
Driver IXS839 provides delay time in the datasheet,  
tDelay _Time (nS) = CDelay (pF) • (0.5nS / pF)  
(22)  
Assume, td1 = td 2 = 100nS , which provides CDelay ( pF) = 200pF  
The Delay-Time loss is define in (11-13) as  
ΔIL  
2
1
⎛
⎞
P = P + P = V • I −  
•td1• f + •V • I •t • f  
⎜
⎟
td1  
cd1  
rr1  
f
O
S
in  
rr  
rr  
S
2
⎝
⎠
0.528  
1
⎛
⎝
⎞
⎟
= 0.85• 12 −  
•100x10−9 • 200x103 + •12 • 2.2 •37x10−9 • 200x103  
⎜
2
2
⎠
= 0.19905+0.09768= 0.297W= 297mW  
ΔIL  
2
⎛
⎞
⎟
P
= P  
(
P
= 0  
)
= V • I +  
•td2 • f  
⎜
td 2  
cd 2  
rr2  
f
O
S
⎝
⎠
0.528  
2
⎛
⎝
⎞
⎟
= 0.85• 12 +  
•100x10−9 • 200x103 =0.208W= 208mW  
⎜
⎠
PBD = P + P = 297mW + 208mW = 505mW  
td1  
td 2  
Synchronous Converter Efficiency:  
If we neglect inductor’s DC power loss and capacitor’s ESR loss then the total  
estimated power loss, Ploss= 1337mW+1007mW+84mW+505mW=2933mW= 2.933W  
Given output power, Po = Vo*Io = 3.3*12= 39.6W  
Estimated input power, Pin= 39.6+2.933=42.6W  
VoIo  
Po  
The efficiency is defined as, η =  
=
(23)  
Vin • Iin Pin  
10  
DC to DC Synchronous Converter Design  
Abdus Sattar, IXYS Corporation  
IXAN0068  
39.6  
The estimated efficiency, η =  
= 0.93 = 93% %,  
42.6  
Estimated input current:  
If we assume only 93% efficiency, then the estimated input current can be obtained,  
VoIo  
3.3•12  
Vin •η 12 • 0.93  
Estimated input current, Iin =  
=
= 3.5A A  
Bootstrap Circuit Design: [3]  
Selecting bootstrap circuit components are done with consideration of the electrical rating  
and characteristics of the high-side MOSFET (Q1).  
The capacitance is defined by datasheet of IXS839 driver,  
QG(total)  
CBST  
=
(24)  
ΔVBST  
Where QG(total) is the total gate charge of high-side MOSFET (Q1), and ΔVBST is the  
allowable voltage droop in Q1. Assume this voltage droop equal to 0.1V.  
42nC  
CBST  
=
= 0.210uF  
200mV  
The bootstrap diode and capacitor voltage rating should be  
VBootstrap _ DiodeandCapacitor > VIN +VDD  
The average forward current is defined by,  
IF ( Avg) = QG(total) • fSW  
(25)  
= 42 •10−9 • 250 •103 = 10.5mA  
Bibliography  
[1] “Synchronous Buck MOSFETs loss calculation” AN-6005, Jon Klein, Fairchild  
Semiconductor, 01/04/2006, www.fairchildsemi.com  
[2] “Examination of reverse recovery losses in a synchronous buck converter circuit”  
Application Note from Silicon Semiconductor, 2003, www.siliconsemi.com  
[3] Datasheet for ISL6594D “Advanced Synchronous Rectified Buck MOSFET Driver”  
from Intersil Corporation, 2007, www.intersil.com  
11  
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