OZ964
FUNCTIONAL INFORMATION
the voltage at ENA (pin 3) is greater than 2V. The
soft-start time is determined by an external
capacitor (C9) connected to the SST (pin 4). At
start-up, as C9 charges via a charging current,
the voltage level at the capacitor controls the
gradual increase in power delivered to the
transformer T1.
1. Steady-State Operation
Referring to the example schematic shown in
Figure 2, page 9, OZ964 drives a full-bridge
power train where the transformer couples the
energy from the power supply source to the
CCFL. The switches in the bridge denoted as
QA, QB, QC and QD are configured such that the
transistors in each pair, QA/QB and QC/QD, are
turned-on complementarily. The turn-on duration
of the diagonal switches, QA/QD and QB/QC,
simultaneously determines the amount of energy
delivered to the transformer and subsequently to
the CCFL. The current in the CCFL is sensed
and regulated by adjusting the turn-on time
(overlap) for both diagonal switches. This is
accomplished through an error amplifier in the
current feedback loop.
4. Ignition
The OZ964 provides an option of selecting a
different frequency for striking the CCFLs. The
striking time is user-defined and determined by
an external capacitor CCTIMR (C6) and external
resistor RCTIMR (R5) connected to CTIMR (pin 1).
The approximate striking time is determined by
the following equation.
CCTIMR[µF] x (3-(RCTIMR[kΩ] x 0.0026))
A voltage loop is used to regulate the output
voltage for CCFL ignition and is programmable
by using a capacitor divider (C8/C13).
T[second] =
2.6
The approximate striking frequency is determined
by the following equation.
Over Voltage Protection (OVP) limits the
transformer voltage under an open-lamp
condition. A soft-start circuit ensures a gradual
increase in power to the CCFL. The soft-start
capacitor (C9) determines the rate of rise of the
voltage on the SST pin. Meanwhile, the voltage
level determines the turn-on time of the diagonal
switches QA/QD and QB/QC.
65•104
fstriking[kHz] =
C
CT[pF]•(RRT // RRT1) [kΩ]
Note: RRT // RRT1 means RRT is in parallel with RRT.1.
5. Normal Operation
The output drives for the power MOSFET gates
include PDR_A, NDR_B, PDR_C and NDR_D
that output a complementary square pulse. The
operation of the four switches is implemented
with zero-voltage switching that provides a high-
efficiency power conversion.
Once the IC is enabled, the voltage at SST (pin
4) controls the rate of power delivered to the
load. SST voltage increases to a level such that
the CCFLs are ignited. The striking frequency is
determined by external components R10, R9 and
C5 connected to RT1 (pin 8), RT (pin 17) and CT
(pin 18) respectively.
2. Enable
Once the external resistor R16 senses sufficient
current, the control loop takes control and
regulates the CCFL current. The normal
operating frequency is determined by the
combination of external resistor R9 and external
capacitor C5. The operating frequency is
approximated by the following equation.
OZ964 is enabled when the voltage on ENA (pin
3) is greater than 2V. A voltage of less than 1V
disables the IC. When the inverter controller is
disabled, it draws approximately 200uA. An
under-voltage lockout protection feature is
provided that will disable the IC if VDDA voltage
drops below an ~3.4V threshold. The IC will
resume normal operation once VDDA reaches a
threshold voltage of greater than ~4.3V.
65•104
fop[kHz] =
CCT[pF]•RRT[kΩ]
3. Soft-Start
To avoid component stresses and in-rush current
to the CCFLs during ignition, a soft start function
is implemented to provide reliable CCFL
operation. The soft-start function is initiated when
CONFIDENTIAL
OZ964-DS-1.2
Page 7
