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OZ960ID

型号:

OZ960ID

品牌:

ETC[ ETC ]

页数:

12 页

PDF大小:

244 K

OZ960  
Intelligent CCFL Inverter Controller  
FEATURES  
quality waveform received, at the CCFL voltage  
and current.  
Supports  
applications (8v to 20v)  
wide-range  
voltage  
input  
Built-in intelligence to manage ignition and  
normal operation of CCFLs  
Reduces the number of components and  
board size by 30% compared with  
conventional designs  
85% efficiency vs. typical 70% efficiency of  
conventional designs  
Zero-voltage-switching full bridge topology  
Built-in internal open-lamp and over-voltage  
protections  
The OZ960 operates at a single, constant  
frequency in a phase-shift PWM mode. Intelligent  
open-lamp and over-voltage protections provide  
design flexibility so various transformer  
models/manufacturers may be used. The built-in  
burst mode control provides a wide dimming  
range and simplifies the application circuit  
designs. Both operating and burst-mode  
frequencies are user-programmable parameters.  
Integrated burst mode control, and wide  
dimming range (10% to 100%) with  
integrated burst mode control  
Supports multiple CCFL lamps  
Simple and reliable 2-winding transformer  
design  
The single stage design results in a low cost,  
reliable transformer without expensive, less  
reliable secondary fold-back treatment. The  
transformer does not require a more expensive  
center tapped primary.  
Constant-frequency  
interference with LCDs  
Low stand-by power  
design  
eliminates  
The OZ960 is available in a 20-pin SSOP  
package. It is specified over the commercial  
temperature range of 0°C to +70°C, and the  
industrial temperature range of -40°C to +85°C.  
ORDERING INFORMATION  
FUNCTIONAL BLOCK  
DIAGRAM  
OZ960S - 20-pin plastic SSOP 150mil  
OZ960IS - 20-pin plastic SSOP 150mil  
OZ960G - 20-pin plastic SOP 300mil  
OZ960IG - 20-pin plastic SOP 300mil  
OZ960D - 20-pin plastic DIP 300mil  
OZ960ID - 20-pin plastic DIP 300mil  
Refer to the functional block diagram in Figure 2,  
page 3, and the Pin Description Table on page 4.  
A
precision reference provides a reference  
voltage for both internal and external uses. An  
oscillator circuit generates a user-programmable  
operating frequency with an external capacitor  
and a timing resistor. In addition, another resistor  
to program striking frequency is provided. The  
drive circuit consists of four outputs. These are  
designed to achieve zero-voltage switching, full-  
bridge applications. An error amplifier is provided  
to regulate the CCFL current. The Soft-start  
circuit offers a gradual increase of the power to  
the CCFL during the ignition period. The over-  
GENERAL DESCRIPTION  
The OZ960 is a unique, high-efficiency, Cold  
Cathode Fluorescent Lamp (CCFL) backlight  
inverter controller that is designed for wide input  
voltage inverter applications. Additionally, the  
OZ960 performs the lamp dimming function with  
an analog voltage or low frequency Pulse Width  
Modulation (PWM) control.  
Operating Principle:  
voltage protection block offers  
a regulated  
Operating in a zero-voltage switching, full-bridge  
configuration, the inverter circuit achieves a very  
high efficiency power conversion. In addition, the  
transformer in the OZ960 does not require any  
specific gap-less arrangement. The simple, low  
cost transformer provides designers a high  
degree of design flexibility in specifying  
transformers. Setting the switching frequency  
higher than the resonant frequency of a high-  
quality-factor resonant tank circuit yields a good-  
striking voltage for CCFLs. The striking time is  
programmable simply through an external  
component. The open-lamp protection is  
integrated in the protection block. This block  
intelligently differentiates the striking condition  
and open-lamp condition. ENA circuitry enables  
the operation of the IC through a TTL signal  
interface. Wide-dimming control is achieved  
through the burst-mode control block.  
10/23/01  
Copyright 2000 - 01 by O2Micro  
OZ960-DS-1.6  
All Rights Reserved  
Page 1  
U.S. Patent #6,259,615  
OZ960  
TYPICAL APPLICATION CIRCUIT  
Figure 1: An 8-22V Application Circuit of OZ960  
OZ960-DS-1.6  
Page 2  
OZ960  
I=3uA  
NDR_B  
PDR_A  
1
2
20  
CTIMR  
OVP  
NDR_B  
I=6uA  
+
-
OVP  
hys.  
Protection  
POFF  
19  
PDR_A  
Soft  
Start  
COMP  
+
-
3
18  
ENA  
ACTIVE  
"HIGH"  
CT  
ENA  
hys.  
HF  
OSC  
COMP  
4
17  
SST  
VDDA  
GNDA  
REF  
RT  
POFF  
5
Reference  
16  
PGND  
6
15  
2.75V  
LCT  
-
Burst-  
Mode  
Control  
OPLAMP  
ZVS  
Phase-Shift  
Controller  
2.50V  
7
14  
+
DIM  
8
Ignition  
13  
RT1  
LPWM  
-
PDR_C  
9
12  
FB  
PDR_C  
EA  
+
1.25V  
10  
11  
NDR_D  
CMP  
NDR_D  
Figure 2. Functional Block Diagram  
OZ960-DS-1.6  
Page 3  
OZ960  
PIN DESCRIPTION  
Names  
Pin No.  
I/O  
Description  
Capacitor for CCFL ignition duration  
Output voltage sense Vth=2.0V  
Enable input; TTL signal is applicable  
Soft-start capacitor  
CTIMR  
OVP  
ENA  
1
2
3
I
I
I
SST  
4
I
VDDA  
GNDA  
REF  
RT1  
FB  
CMP  
NDR_D  
PDR_C  
LPWM  
DIM  
LCT  
PGND  
RT  
5
6
7
8
I
I
O
I
I
O
O
O
O
I
I
I
I
I
O
O
Voltage source for the IC  
Analog signal ground reference  
Reference voltage output; 2.5V typical  
Resistor for programming ignition frequency  
CCFL current feedback signal  
Compensation output of the current error amplifier  
NMOSFET drive output  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
PMOSFET drive output  
Low-frequency PWM signal for burst-mode dimming control  
Input analog signal for burst-mode dimming control  
Triangular wave for burst-mode dimming; frequency  
Power ground reference  
Timing resistor set operating frequency  
Timing capacitor set operating frequency  
PMOSFET drive output  
CT  
PDR_A  
NDR_B  
NMOSFET drive output  
ABSOLUTE MAXIMUM RATINGS WITH  
RESPECT TO INPUT POWER SOURCE  
RETURN REFERENCE  
VDDA  
7.0V(1)  
+/- 0.3V  
GNDA, PGND  
Logic inputs  
-0.3V to VDD +0.3V  
OZ960  
0oC to 70oC  
OZ960I  
-40oC to 85oC  
Operating temp.  
Operating junction temp.  
Storage temp.  
150 oC  
-55 oC to 150 oC  
RECOMMENDED OPERATING RANGE  
VDDA  
Fosc  
4.7V ~ 5.5V  
30 KHz to 150 KHz  
50 k to 150 k  
Rosc  
Note (1): The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed.  
The device should not be operated at these limits. The “Functional Specifications” table will define the conditions for  
actual device operation. Exposure to absolute maximum rated conditions for extended periods may affect device  
reliability.  
OZ960-DS-1.6  
Page 4  
OZ960  
FUNCTIONAL SPECIFICATIONS  
Parameter  
Symbol  
Test Conditions  
Limits  
Unit  
VDDA=5V; Tamb = 25oC  
Min  
Typ  
Max  
Reference Voltage  
Nominal voltage  
Line regulation  
Vref  
Iload = 0.1mA  
2.37  
2.5  
4
2.63  
V
VDDA = 4.7V – 5.3V  
Iload = 0.025 mA to 0.25 mA  
-
-
-
-
mV/V  
mV/mA  
Load regulation  
High Frequency Oscillator  
Initial accuracy  
2
fosc  
CT = 100pF, RT = 120k(1)  
TA = 0 oC to 70oC  
53  
-
57  
3.0  
1.0  
200  
60  
-
KHz  
Ramp peak  
V
V
Ramp valley  
-
-
Temp. stability  
-
-
ppm/ oC  
Low Frequency Oscillator  
Initial accuracy  
See Table 1, page 6  
Ramp peak  
2.85  
0.94  
3.0  
3.15  
1.06  
V
V
Ramp valley  
1.0  
Low Frequency PWM  
Duty Cycle Range  
0
-
100  
%
Error Amplifier  
Input offset voltage  
Input voltage range  
Offset current at FB pin  
-
0
-
7
-
-
mV  
V
VDD-1.5V  
100  
-
nA  
Reference voltage at non-  
inverting input pin (internal)  
VADJ  
1.19  
1.25  
1.31  
V
Open loop voltage gain  
Unity gain bandwidth  
Power supply rejection  
Threshold  
-
-
-
80  
1.0  
60  
-
-
-
dB  
MHz  
dB  
Over Voltage Protection  
Supply  
1.90  
-
2
2.15  
200  
V
Supply current  
IOFF  
ENA = low  
150  
µA  
ENA = high; VDDA = 5V;  
Vdim = 2V; LPWM = 50k(2)  
Ca=Cb=Cc=Cd=2nF(3)  
Supply current  
ION  
-
4.4  
5.5  
mA  
HF = 60kHz; LF = 185Hz  
SST current  
See Table 1, page 6  
See Table 1, page 6  
CTIMR current  
NDR-PDR Output  
Output resistance  
Output resistance  
Rp  
Rn  
Current source  
Current sink  
-
-
27  
14  
-
-
OZ960-DS-1.6  
Page 5  
OZ960  
Parameter  
Symbol  
Test Conditions  
Limits  
Unit  
Max. / Min. Overlap  
VDDA = 5V; Tamb = 25oC  
Min  
3.0  
Typ  
4.5  
Max  
HF = 60kHz  
Ca=Cb=Cc=Cd=2nF(3)  
HF = 60kHz  
Min. Overlap between  
diagonal switches  
5.5  
84  
%
%
Max. Overlap between  
diagonal switches  
78  
81  
Ca=Cb=Cc=Cd=2nF(3)  
Brake before Make  
PDR_A / NDR_B  
PDR_C / NDR_D  
See Table 1, below  
See Table 1, below  
OZ960  
OZ960I  
Limits  
Parameter  
Symbol  
Test Conditions  
Limits  
Unit  
Unit  
Min  
160  
Typ  
Max  
250  
Min  
150  
Typ  
Max  
Low Frequency Oscillator  
Initial accuracy  
LCT = 6.8nF, LPWM = 50k(2)  
220  
340  
Hz  
fosc  
220  
Hz  
Supply  
ISST  
4.9  
2.2  
7.5  
3.3  
10  
SST current  
4.9  
2.0  
6.0  
3.0  
12  
µA  
µA  
µA  
µA  
ICTIMR  
4.5  
CTIMR current  
5.2  
Brake before Make  
PDR_A / NDR_B  
PDR_C / NDR_D  
HF = 60kHz  
HF = 60kHz  
250  
250  
380  
380  
530  
520  
ns  
ns  
250  
250  
380  
380  
565  
545  
ns  
ns  
Threshold  
Enable  
1.35  
1.50  
1.65  
V
1.25  
1.50  
1.65  
V
Table 1. Low Frequency Oscillator, Supply and Brake  
before Make Specifications for OZ960 and OZ960I  
Note (1)  
CT: capacitor from CT (Pin 18) to ground  
RT: resistor from RT (Pin 17) to ground  
Note (2)  
LCT: capacitor from LCT (Pin 15) to ground  
LPWM: resistor from LPWM (Pin 13) to ground  
Note (3)  
Ca: capacitor from PDR_A (Pin 19) to VDDA  
Cb: capacitor from NDR_B (Pin 20) to ground  
Cc: capacitor from PDR_C (Pin 12) to VDDA  
Cd: capacitor from NDR_D (Pin 11) to ground  
OZ960-DS-1.6  
Page 6  
OZ960  
FUNCTIONAL INFORMATION  
regulated through a voltage feedback loop where  
output voltage is monitored. The signal, being  
sent to the OVP pin, commands the output drives  
to provide the desired output voltage. This design  
provides high degree of flexibility while  
1. Steady-State Operation  
Refer to the schematic shown in Figure 1, the  
OZ960 drives a full-bridge power train where the  
transformer couples the energy from the power  
source to the secondary CCFL load. The  
switches in the bridge denoted as QA, QB, QC  
and QD are configured such that QA and QB, QC  
and QD are turned on complementarily. The  
duration of QA and QD, QB and QC turn on  
simultaneously determines an amount of energy  
put into the transformer which in turn delivers to  
the CCFL. The current in CCFL is sensed via  
resistor R9 and regulated through the adjustment  
of the turn-on time for both diagonal switches.  
This is accomplished through an error amplifier in  
the current feedback loop. A voltage loop is also  
established to monitor the output voltage so that  
a programmable striking voltage is achieved. The  
OVP represents the peak-detect signal of the  
voltage on the output of the transformer. A soft-  
start circuit ensures a gradual increase in the  
input and output power. The soft-start capacitor  
determines the rate of rise of the voltage on SST  
pin where the voltage level determines the on-  
time duration of QA and QD, QB and QC  
diagonal switches. This minimizes the surge  
impacts in circuit designs.  
maintaining OZ960  
device.  
a very high integration  
One protection feature needed is removing the  
lamp during normal operation. The OZ960  
senses the missing current signal through current  
amplifier, it shuts off the output drives and stay in  
the latched mode. This is differentiated  
intelligently with turning on the inverter while  
CCFL is not connected. Recycle of the IC power  
is necessary to resume normal operation.  
Dimming control: dimming control of the inverter  
is implemented by adjusting the amount of  
energy processed and delivered to the CCFL. A  
PWM burst-mode scheme is internally generated  
which provides 0% to 100% wide dimming  
control. An input analog voltage signal is fed into  
DIM pin and determines the dimming level of the  
CCFL.  
The  
burst-mode  
frequency  
is  
programmable through a capacitor C10 as shown  
in the schematic.  
The OZ960 inverter operates in a constant  
frequency mode. This eliminates any undesired  
interference between inverter and LCD panels  
where the interference is usually associated with  
variable-frequency designs.  
Apply enable signal to the ENA pin of the IC after  
the bias voltage applied to VDDA initiates the  
operation of the circuit. The output drives, include  
PDR_A, NDR_B, PDR_C and NDR_D put out a  
complementary square pulse. The frequency is  
determined by R4 and C5 where they are  
connected to RT and CT pins respectively.  
Initially, the energy converted from the power  
source to the CCFL is low due to the soft start  
function. It increases as soft start capacitor  
voltage increases linearly with time. The voltage  
at the secondary side of the transformer T1  
Symmetrical drive to the power transformer gives  
a very dynamic choice of selecting transformers.  
This vulnerable design offers flexibility to the  
system designers to choose transformer sources.  
There is no limitation to the gap-less transformer.  
2. CCFL Ignition Time  
increases  
correspondingly.  
This  
process  
continues until the CCFL current is detected and  
reaches a regulated value. The output of the  
error amplifier, CMP, follows the feedback signal,  
commands a proper switching among the four  
output drives to maintain current regulation. The  
operations of the four switches are implemented  
with zero-voltage-switching to provide a high-  
efficiency power conversion.  
Ignition time for CCFLs varies with CCFL length,  
diameter, module package and temperature. The  
OZ960 provides a flexible design where a  
capacitor is connected to CTIMR pin to determine  
the necessary striking time. An approximate of  
the timing calculation is:  
T[second] = C[uF]  
In the case of open-lamp condition, the OZ960  
provides  
a
programmable striking-frequency  
This capacitor remains reset at no charge if lamp  
is connected and at normal operation.  
intelligence to optimize the ignition scheme. This  
is implemented through resistor R5. Effectively,  
R5 is in parallel with R4 to yield a required  
striking frequency. In addition, the striking time is  
also programmable through the capacitor C8.  
Striking voltage, or the open-lamp voltage, is  
OZ960-DS-1.6  
Page 7  
OZ960  
striking voltage and frequency. This add-on  
feature could optimally accomplish the ignition  
process so that the CCFL life could be extended.  
When RT1 is used, it is connected in parallel with  
RT during the ignition period.  
3. Protection  
Open-lamp protection in the ignition period is  
provided through both OVP and CTIMR to ensure  
a rated voltage is achieved and a required timing  
is satisfied. Removal of the CCFL during normal  
operation will trigger the current amplifier output  
and shuts off the inverter. This is a latch function.  
9. Burst-Mode Dimming Control  
The OZ960 integrates a burst-mode dimming  
function to perform a wide dimming control for the  
CCFLs. The burst-mode frequency is determined  
by a capacitor C10 connected to LCT pin. The  
frequency can be calculated approximately by:  
4. OVP  
The OVP threshold is set at 2V nominal. When  
the output voltage reaches the threshold, it  
commands the PWM controller to maintain the  
driving level. This ensures that output gets  
sufficient striking voltage while operating the  
power transformer safely.  
1496  
f[Hz] =  
CLCT[nF]  
5. ENA  
Applying positive TTL logic to the ENA pin  
enables the operation of the IC. The threshold of  
the ENA is set at 1.5V. Apply logic low to the  
ENA pin will disable the operation of the inverter.  
Toggle this signal allows the on/off tests for the  
inverter.  
The Dim pin compares with the triangle wave in  
LCT and yields a proper pulse width to modulate  
the CCFL current. This pulse can also be  
monitored through LPWM pin. The peak and  
valley of the LCT signal is 3V and 1V  
respectively.  
6. Soft-Start -- SST  
10. Output Drives  
The soft-start function is provided with  
a
The four output drives are designed so that  
switches QA and QB, QC and QD never turn on  
simultaneously. These include two NMOS and  
two PMOS transistors. The configuration  
prevents any shoot-through issue associated with  
bridge-type power conversion applications.  
Adjusting the overlap conduction between QA  
and QD, QB and QC, the CCFL current  
regulation is achieved. This overlap is also  
adjusted while the voltage applied from the  
battery varies. At a specific CCFL current, the  
input power is maintained almost constant.  
capacitor connected to SST pin. The soft-start  
time is not related to the striking time for the  
CCFL. It simply provides a rate of rise for the  
pulse width where diagonal switches are turned  
on. Normally, a 0.47uF capacitor is connected.  
7. Error Amplifier  
The CCFL current is regulated through this error  
amplifier. It also provides an intelligence of  
differentiating open-lamp striking versus  
removing the lamp during normal operation. The  
non-inverting reference is at 1.25V nominal.  
8. Operating frequency  
A resistor RT and a capacitor CT determine the  
operating frequency of OZ960. The frequency is  
calculated as:  
68.5104  
f[kHz] =  
CT[pF]RT[k]  
The OZ960 also provides an optional striking  
frequency as desired. CCFL in a LCD module  
possesses parasitic that may require different  
OZ960-DS-1.6  
Page 8  
OZ960  
PACKAGE INFORMATION (SSOP 150mil)  
D
Detail A  
E1  
E
c
1
ZD  
A2  
0.10MM C  
SEATING PLANE  
B
e
NOTES:  
DIMENSION D DOES NOT INCLUDE MOLD PROTRUSIONS OR GATE BURRS  
MOLD PROTRUSIONS AND GATE BURRS SHALL NOT EXCEED 0.006 INCH PER SIDE  
DIM  
MILLIMETERS  
INCHES  
NOM  
0.064  
MIN  
1.35  
0.10  
NOM  
1.63  
0.15  
MAX  
MIN  
0.053  
0.004  
MAX  
0.069  
0.010  
0.059  
0.012  
0.010  
θ2  
A
A1  
A2  
B
1.75  
0.25  
1.50  
0.30  
0.25  
0.006  
0.20  
0.18  
0.008  
0.007  
c
θ1  
e
D
E
E1  
L
0.635 BASIC  
8.66  
0.025 BASIC  
0.341  
R1  
8.56  
5.79  
3.81  
0.41  
0.25  
8.74  
6.20  
3.99  
1.27  
0.50  
0.337  
0.228  
0.150  
0.016  
0.010  
0.344  
0.244  
0.157  
0.050  
0.020  
Gauge Plane  
R
5.99  
3.91  
0.635  
0.236  
0.154  
0.025  
h
θ
ZD  
R1  
R
1.4732 REF  
0.058 REF  
L
0.20  
0.20  
0°  
0.33  
8°  
0.008  
0.008  
0°  
0.013  
8°  
Detail A  
θ
θ1  
θ2  
JEDEC  
0°  
5°  
0°  
5°  
10°  
15°  
10°  
15°  
MO-137 (AD)  
OZ960-DS-1.6  
Page 9  
OZ960  
PACKAGE INFORMATION (SOP 300mil)  
b
1 1  
2 0  
D e ta il X  
H
E
1
1 0  
e
c
D
Y
S E A T IN G P L A N E  
N O T E S :  
1 . R E F E R T O J E D E C S T D . M S -0 1 3 A C .  
2 . D IM E N S IO N S " D " D O S E N O T IN C L U D E M O L D F L A S H , P R O T R U S IO N S O R G A T E B U R R S . M O L D  
F L A S H , P R O T R U S IO N S A N D G A T E B U R R S S H A L L N O T E X C E E D 0 .1 5 m m (6 m il) P E R S ID E .  
3 . D IM E N S IO N S " E " D O S E N O T IN C L U D E IN T E R L E A D F L A S H O R P R O T U R S IO N S . IN T E R -L E A D  
F L A S H A N D P R O T R U S IO N S S H A L L N O T E X C E E D 0 .2 5 m m (1 0 m il) P E R S ID E .  
4 . C O N T R O L L IN G D IM E N S IO N : M IL L IM E T E R  
h x 45O  
SYMBOL  
MM  
NOM  
2.54  
MIL  
NOM  
100  
8
16  
10  
504  
295  
50 BSC  
406  
26  
MIN  
2.36  
0.10  
0.35  
0.23  
12.60  
7.40  
MAX  
2.64  
0.30  
0.48  
0.31  
13.00  
7.60  
MIN  
93  
4
14  
9
MAX  
104  
12  
19  
12  
A
A1  
b
0.20  
0.406  
0.254  
12.80  
7.50  
1.27 BSC  
10.31  
0.66  
c
D
E
e
H
h
L
Y
θ
496  
291  
512  
299  
10.00  
0.25  
0.51  
10.65  
0.75  
1.02  
0.075  
8°  
394  
10  
20  
419  
30  
40  
3
θ
0.76  
30  
L
DETAIL "X"  
0°  
0°  
8°  
OZ960-DS-1.6  
Page 10  
OZ960  
PACKAGE INFORMATION (DIP 300mil)  
D
H
SEATING  
PLANE  
0.100typ.  
0.018typ.  
0.060typ.  
SYMBOL  
MIN  
-
0.015  
0.125  
0.98  
NOR  
-
-
0.130  
1.030  
MAX  
0.210  
-
0.135  
1.060  
A
A1  
A2  
D
E
E1  
L
eB  
θ
0.300 BSC  
0.250  
0.130  
0.355  
7°  
0.245  
0.115  
0.335  
0°  
0.255  
0.150  
0.375  
15°  
NOTES:  
1. JEDEC OUTLINE: MS-001 AD  
2. “D”, “E” DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.MOLD FLASH OR PROTRUSIONS  
SHALL NOT EXCEED .010 INCH  
3. eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED.  
4. POINTED OR ROUNDED LEAD TIPS ARE PREFERRED TO EASE INSERTION.  
5. DISTANCE BETWEEN LEADS INCLUDING DAM BAR PROTRUSIONS TO BE .005 INCH MINIMUM.  
6. DATUM PLANE H COINCIDENT WITH THE BOTTOM OF LEAD, WHERE LEAD EXITS BODY.  
OZ960-DS-1.6  
Page 11  
OZ960  
IMPORTANT NOTICE  
No portion of O2Micro specifications/datasheets or any of its subparts may be reproduced in any form, or by  
any means, without prior written permission from O2Micro.  
O2Micro and its subsidiaries reserve the right to make changes to their datasheets and/or products or to  
discontinue any product or service without notice, and advise customers to obtain the latest version of  
relevant information to verify, before placing orders, that information being relied on is current and complete.  
All products are sold subject to the terms and conditions of sale supplied at the time of order  
acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability.  
O2Micro warrants performance of its products to the specifications applicable at the time of sale in  
accordance with O2Micro’s standard warranty. Testing and other quality control techniques are utilized to the  
extent O2Micro deems necessary to support this warranty. Specific testing of all parameters of each device  
is not necessarily performed, except those mandated by government requirements.  
Copyright © 2002, O2Micro International Limited  
OZ960-DS-1.6  
Page 12  
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