HYMD564M646A(L)8-J/K/H
DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Speed
-K
Parameter
Operating Current
Operating Current
Symbol
IDD0
Test Condition
Unit Note
-J
-H
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle ; address and control inputs
changing once per clock cycle
1120
960
960
mA
mA
One bank; Active - Read - Precharge; Burst Length =2;
tRC=tRC(min); tCK=tCK(min); address and control
inputs changing once per clock cycle
IDD1
1440
80
1200
1200
80
Precharge Power
Down Standby Current
All banks idle; Power down mode; CKE=Low, tCK=
tCK(min)
IDD2P
IDD2N
80
mA
mA
Idle Standby Current
Idle Standby Current
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
280
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
IDD2F
280
mA
/CS>=Vih(min); All banks idle; CKE>=Vih(min);
Addresses and other control inputs stable, Vin=Vref for
DQ, DQS and DM
Idle Quiet Standby
Current
IDD2Q
IDD3P
200
96
mA
mA
Active Power Down
Standby Current
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
Active Standby Current
Operating Current
Operating Current
IDD3N
IDD4R
IDD4W
IDD5
360
320
320
mA
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
2000
2000
2240
1680
1680
2080
1680
1680
2080
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM, and DQS inputs
changing twice per clock cycle
mA
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
Auto Refresh Current
Self Refresh Current
Normal
40
20
mA
mA
CKE=<0.2V; External clock on; tCK
IDD6
IDD7
=tCK(min)
Low Power
Operating Current -
Four Bank Operation
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
3680
3680
3040
3040
3040
mA
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0
mA, 100% DQ, DM and DQS inputs changing twice
per clock cycle; 100% addresses changing once per
clock cycle
Random Read Current
IDD7A
3040
mA
Rev. 0.2 / Apr. 2004
9
