请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

HYM321000S-50

型号：

HYM321000S-50

描述：

1M ×32位动态RAM模块2M ×16位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module ]

品牌：

INFINEON[ Infineon ]

页数：

10 页

PDF大小：

83 K

下载PDF手册
1M × 32-Bit Dynamic RAM Module  
(2M × 16-Bit Dynamic RAM Module)  
HYM 321000S/GS-50/-60  
Advanced Information  
• 1 048 576 words by 32-bit organization  
(alternative 2 097 152 words by 16-bit)  
• Fast access and cycle time  
50 ns access time  
90 ns cycle time (-50 version)  
60 ns access time  
110 ns cycle time (-60 version)  
• Fast page mode capability with  
35 ns cycle time (-50 version)  
40 ns cycle time (-60 version)  
• Single + 5 V (± 10 %) supply  
• Low power dissipation  
max 2200 mW active (-50 version)  
max. 1980 mW active (-60 version)  
CMOS – 11 mW standby  
TTL  
– 22 mW standby  
• CAS-before-RAS refresh, RAS-only-refresh, Hidden refresh  
• 2 decoupling capacitors mounted on substrate  
• All inputs, outputs and clock fully TTL compatible  
• 72 pin Single in-Line Memory Module  
• Utilizes two 1M × 16 -DRAMs in SOJ-42 packages  
• 1024 refresh cycles/16 ms  
• Optimized for use in byte-write non-parity applications  
• Tin-Lead contact pads HYM 321000S  
• Gold-Lead contact pads HYM 321000GS  
• single sided module with 20.32 mm (800 mil) height  
Semiconductor Group  
1
12.95  
HYM 321000S/GS-50/-60  
1M × 32-Bit  
The HYM 321000S/GS-50/-60 is a 4 MByte DRAM module organized as 1 048 576 words by  
32-  
bit in a 72-pin single-in-line package comprising two HYB 5118160BSJ 1M × 16 DRAMs in 400 mil  
wide SOJ-packages mounted together with two 0.2 µF ceramic decoupling capacitors on a PC  
board.  
The HYM 321000S/GS-60/-70 can also be used as a 2 097 152 words by 16-bits dynamic RAM  
module by means of connecting DQ0 and DQ16, DQ1 and DQ17, DQ2 and DQ18, …, DQ15 and  
DQ31, respectively.  
Each HYB 5118160BSJ is described in the data sheet and is fully electrically tested and processed  
according to Siemens standard quality procedure prior to module assembly. After assembly onto  
the board, a further set of electrical tests is performed.  
The speed of the module can be detected by the use of four presence detect pins.  
The common I/O feature on the HYM 321000S/GS-50/-60 dictates the use of early write cycles.  
Ordering Information  
Type  
Ordering Code  
Package  
Descriptions  
HYM 321000S-50  
Q67100 - Q2051  
L-SIM-72-10  
DRAM module  
(access time50 ns)  
HYM 321000S-60  
HYM 321000GS-50  
HYM 321000GS-60  
Q67100 - Q2056  
Q67100 - Q2053  
Q67100 - Q2058  
L-SIM-72-10  
L-SIM-72-10  
L-SIM-72-10  
DRAM module  
(access time 60 ns)  
DRAM module  
(access time 50 ns)  
DRAM module  
(access time 60 ns)  
Semiconductor Group  
2
HYM 321000S/GS-50/-60  
1M × 32-Bit  
Pin Names  
VSS  
1 DQ0  
2
4
6
8
DQ16 3 DQ1  
DQ17 5 DQ2  
DQ18 7 DQ3  
DQ19 9 VCC 10  
N.C. 11 A0  
A1  
A3  
A5  
N.C. 19 DQ4 20  
DQ20 21 DQ5 22  
DQ21 23 DQ6 24  
DQ22 25 DQ7 26  
DQ23 27 A7  
N.C. 29 VCC 30  
A8 31 A9 32  
A0-A9  
Address Inputs  
DQ0-DQ31  
CAS0 - CAS3  
RAS0, RAS2  
WE  
Data Input/Output  
Column Address Strobe  
Row Address Strobe  
Read/Write Input  
Power (+ 5 V)  
12  
14  
16  
18  
13 A2  
15 A4  
17 A6  
VCC  
VSS  
Ground  
28  
PD  
Presence Detect Pin  
No Connection  
N.C. 33 RAS2 34  
N.C. 35 N.C. 36  
N.C.  
N.C. 37 N.C. 38  
VSS  
39 CAS0 40  
CAS2 41 CAS3 42  
CAS1 43 RAS0 44  
N.C. 45 N.C. 46  
Presence Detect Pins  
WE  
47 N.C. 48  
DQ8 49 DQ24 50  
DQ9 51 DQ25 52  
DQ10 53 DQ26 54  
DQ11 55 DQ27 56  
DQ12 57 DQ28 58  
VCC 59 DQ29 60  
DQ13 61 DQ30 62  
DQ14 63 DQ31 64  
DQ15 65 N.C. 66  
-50  
-60  
PD0  
PD1  
PD2  
PD3  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
N.C.  
N.C.  
PD0  
PD2  
67 PD1 68  
69 PD3 70  
N.C. 71 VSS 72  
Pin Configuration  
Semiconductor Group  
3
HYM 321000S/GS-50/-60  
1M × 32-Bit  
RAS0  
CAS0  
CAS1  
UCAS LCAS RAS  
I/O1-I/O8  
DQ0-DQ7  
DQ8-DQ15  
I/O9-I/O16  
OE  
D1  
RAS2  
CAS2  
CAS3  
UCAS LCAS RAS  
I/O1-I/O8  
DQ16-DQ23  
DQ24-DQ31  
I/O9-I/O16  
OE  
D2  
A0 - A9  
WE  
D1 , D2  
D1 , D2  
VCC  
VSS  
C1 , C2  
Block Diagram  
Semiconductor Group  
4
HYM 321000S/GS-50/-60  
1M × 32-Bit  
Absolute Maximum Ratings  
Operating temperature range .........................................................................................0 to + 70 °C  
Storage temperature range......................................................................................– 55 to + 125 °C  
Input/output voltage ........................................................................... – 0.5 to min (Vcc + 0.5, 7.0) V  
Power supply voltage...................................................................................................... – 1 to + 7 V  
Power dissipation................................................................................................................... 2.52 W  
Data out current (short circuit) ................................................................................................ 50 mA  
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent  
damage to the device. Exposure to absolute maximum rating conditions for extended periods  
may affect device reliability.  
DC Characteristics 1)  
TA = 0 to 70 °C; VCC = 5 V ± 10 %  
Parameter  
Symbol  
Limit Values  
Unit Test  
Condition  
min.  
max.  
5.5  
0.8  
–
Input high voltage  
VIH  
VIL  
2.4  
– 1.0  
2.4  
–
V
–
Input low voltage  
V
–
–
–
–
Output high voltage (IOUT = – 5 mA)  
Output low voltage (IOUT = 4.2 mA)  
VOH  
VOL  
II(L)  
V
0.4  
10  
V
Input leakage current  
– 10  
µA  
(0 V < VIN < 6.5 V, all other pins = 0 V)  
Output leakage current  
(DO is disabled, 0 V < VOUT < 5.5 V)  
IO(L)  
ICC1  
– 10  
10  
µA  
–
Average VCC supply current:  
HYM 321000S/GS-50  
HYM 321000S/GS-60  
2), 3),4)  
–
–
–
400  
360  
mA  
mA  
(RAS, CAS, address cycling, tRC = tRC min.)  
Standby VCC supply current  
(RAS = CAS = VIH)  
ICC2  
ICC3  
–
4
mA  
–
Average VCC supply current during RAS  
only refresh cycles:  
2),4)  
HYM 321000S/GS-50  
HYM 321000S/GS-60  
–
–
–
400  
360  
mA  
mA  
(RAS cycling, CAS = VIH , tRC = tRC min.)  
Semiconductor Group  
5
HYM 321000S/GS-50/-60  
1M × 32-Bit  
DC Characteristics (cont’d) 1)  
Parameter  
Symbol  
Limit Values  
Unit Test  
Condition  
min.  
max.  
Average VCC supply current during fast  
page mode:  
ICC4  
2), 3),4)  
HYM 321000S/GS-50  
HYM 321000S/GS-60  
–
–
–
110  
100  
mA  
mA  
(RAS = VIL, CAS, address cycling  
tPC = tPC min.)  
Standby VCC supply current  
(RAS = CAS = VCC – 0.2 V)  
ICC5  
ICC6  
–
2
mA  
–
Average VCC supply current during  
CAS-before-RAS refresh mode:  
2),4)  
HYM 321000S/GS-50  
HYM 321000S/GS-60  
–
–
–
400  
360  
mA  
mA  
(RAS, CAS cycling, tRC = tRC min.)  
Capacitance  
TA = 0 to 70 °C; VCC = 5 V ± 10 %; f = 1 MHz  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
max.  
25  
Input capacitance (A0 to A9)  
Input capacitance (RAS0, RAS2)  
Input capacitance (CAS0-CAS3)  
Input capacitance (WE)  
CI1  
CI2  
CI3  
CI4  
CIO1  
–
–
–
–
–
pF  
pF  
pF  
pF  
pF  
20  
20  
25  
I/O capacitance (DQ0-DQ31)  
15  
Semiconductor Group  
6
HYM 321000S/GS-50/-60  
1M × 32-Bit  
5)6)  
M16F  
AC Characteristics  
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns  
Symbol  
Note  
Parameter  
Limit Values  
-50 -60  
min. max. min. max.  
Unit  
common parameters  
Random read or write cycle time  
RAS precharge time  
tRC  
90  
30  
50  
13  
0
–
110  
40  
60  
15  
0
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tRP  
–
–
RAS pulse width  
tRAS  
tCAS  
tASR  
tRAH  
tASC  
tCAH  
tRCD  
tRAD  
tRSH  
tCSH  
tCRP  
tT  
10k  
10k  
–
10k  
10k  
–
CAS pulse width  
Row address setup time  
Row address hold time  
Column address setup time  
Column address hold time  
RAS to CAS delay time  
RAS to column address delay time  
RAS hold time  
8
–
10  
0
–
0
–
–
10  
18  
13  
13  
50  
5
–
15  
20  
15  
15  
60  
5
–
37  
25  
45  
30  
–
ns  
ns  
ns  
ns  
ns  
ms  
CAS hold time  
–
CAS to RAS precharge time  
Transition time (rise and fall)  
Refresh period  
–
–
3
50  
16  
3
50  
16  
7
tREF  
–
–
Read Cycle  
Access time from RAS  
tRAC  
tCAC  
tAA  
–
50  
13  
25  
–
–
60  
15  
30  
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
8, 9  
8, 9  
8,10  
Access time from CAS  
–
–
Access time from column address  
Column address to RAS lead time  
Read command setup time  
Read command hold time  
–
–
tRAL  
tRCS  
tRCH  
tRRH  
25  
0
30  
0
–
–
0
–
0
–
11  
11  
Read command hold time referenced to  
RAS  
0
–
0
–
CAS to output in low-Z  
tCLZ  
tOFF  
0
0
–
0
0
–
ns  
ns  
8
Output buffer turn-off delay  
13  
15  
12  
Semiconductor Group  
7
HYM 321000S/GS-50/-60  
1M × 32-Bit  
5)6)  
M16F  
AC Characteristics (cont’d)  
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns  
Symbol  
Note  
Parameter  
Limit Values  
-50 -60  
min. max. min. max.  
Unit  
Early Write Cycle  
Write command hold time  
Write command pulse width  
Write command setup time  
Write command to RAS lead time  
Write command to CAS lead time  
Data setup time  
tWCH  
tWP  
8
–
–
–
–
–
–
–
10  
10  
0
–
–
–
–
–
–
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
8
tWCS  
tRWL  
tCWL  
tDS  
0
13  
13  
13  
0
15  
15  
0
14  
14  
Data hold time  
tDH  
10  
10  
Fast Page Mode Cycle  
Fast page mode cycle time  
CAS precharge time  
tPC  
35  
10  
–
–
40  
10  
–
–
ns  
ns  
ns  
tCP  
–
–
Access time from CAS precharge  
RAS pulse width  
tCPA  
tRAS  
tRHCP  
30  
35  
7
50  
30  
200k 60  
200k ns  
CAS precharge to RAS Delay  
–
35  
–
ns  
CAS-before-RAS Refresh Cycle  
CAS setup time  
tCSR  
tCHR  
tRPC  
tWRP  
tWRH  
10  
10  
5
–
–
–
–
–
10  
10  
5
–
–
–
–
–
ns  
ns  
ns  
ns  
ns  
CAS hold time  
RAS to CAS precharge time  
Write to RAS precharge time  
Write hold time referenced to RAS  
10  
10  
10  
10  
Semiconductor Group  
8
HYM 321000S/GS-50/-60  
1M × 32-Bit  
Notes:  
1) All voltages are referenced to VSS.  
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.  
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.  
4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less  
during a fast page mode cycle (tPC).  
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has  
to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a  
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.  
6) AC measurements assume tT = 5 ns.  
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also  
measured between VIH and VIL.  
8) Measured with a load equivalent to 2 TTL loads and 100 pF.  
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a  
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by  
tCAC.  
10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a  
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by  
tAA.  
11)Either tRCH or tRRH must be satisfied for a read cycle.  
12)tOFF (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to  
output voltage levels  
.
13)tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics  
only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high  
impedance) through the entire cycle.  
14)These parameters are referenced to the CAS leading edge.  
Semiconductor Group  
9
HYM 321000S/GS-50/-60  
1M × 32-Bit  
L-SIM-72-10  
Module package  
(single in-line memory module)  
GLS05833  
Semiconductor Group  
10  
厂商 型号 描述 页数 下载

ETC

 		HYM22100S-60 X8快速页模式DRAM模块\n[ x8 Fast Page Mode DRAM Module ] 9 页

ETC

 		HYM22100S-70 X8快速页模式DRAM模块\n[ x8 Fast Page Mode DRAM Module ] 9 页

ETC

 		HYM22100S-80 X8快速页模式DRAM模块\n[ x8 Fast Page Mode DRAM Module ] 9 页

INFINEON

 		HYM321000GS-50 1M ×32位动态RAM模块2M ×16位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module ] 10 页

INFINEON

 		HYM321000GS-60 1M ×32位动态RAM模块2M ×16位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module ] 10 页

INFINEON

 		HYM321000S 1M ×32位动态RAM模块2M ×16位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module ] 10 页

INFINEON

 		HYM321000S-60 1M ×32位动态RAM模块2M ×16位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module ] 10 页

INFINEON

 		HYM321005GS-50 1M ×32位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module ] 10 页

INFINEON

 		HYM321005GS-60 1M ×32位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module ] 10 页

INFINEON

 		HYM321005S 1M ×32位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module ] 10 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于达普

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：smail@ic72.com

服务时间：周一至周六 8:30-17:30

达普官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.213906s