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HYMD564M646AL6-D43

型号：

HYMD564M646AL6-D43

描述：

无缓冲DDR SO -DIMM[ Unbuffered DDR SO-DIMM ]

品牌：

HYNIX[ HYNIX SEMICONDUCTOR ]

页数：

17 页

PDF大小：

327 K

下载PDF手册
64Mx64 bits  
Unbuffered DDR SO-DIMM  
HYMD564M646A(L)6-D43/D4/J  
Document Title  
64Mx64 bits Unbuffered DDR SO-DIMM  
Revision History  
No.  
History  
Draft Date  
Remark  
0.1  
Initial draft  
Oct. 2003  
1) Reflected a “notational” change in module thickness on page 14 - Not Real ! -  
2) Corrected some typos  
0.2  
Apr. 2004  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.2 / Apr. 2004  
1
64Mx64 bits  
Unbuffered DDR SO-DIMM  
HYMD564M646A(L)6-D43/D4/J  
Preliminary  
DESCRIPTION  
Hynix HYMD564M646A(L)6-D43/D4/J series is unbuffered 200-pin double data rate Synchronous DRAM Small Out-  
line Dual In-Line Memory Modules (SO-DIMMs) which are organized as 64Mx64 high-speed memory arrays. Hynix  
HYMD564M646A(L)6-D43/D4/J series consists of eight 32Mx16 DDR SDRAM in 400mil TSOP II packages on a  
200pin glass-epoxy substrate. Hynix HYMD564M646A(L)6-D43/D4/J series provide a high performance 8-byte inter-  
face in 67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.  
Hynix HYMD564M646A(L)6-D43/D4/J series is designed for high speed of up to 200MHz and offers fully synchronous  
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs  
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-  
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.  
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and  
burst lengths allow variety of device operation in high performance memory system.  
Hynix HYMD564M646A(L)6-D43/D4/J series incorporates SPD(serial presence detect). Serial presence detect func-  
tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to  
identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.  
FEATURES  
•
200-pin small outline dual in-line memory  
module(SO-DIMM)  
•
•
Programmable CAS Latency 3 (clock) for DDR400,  
2.5 (clock) for DDR333  
•
•
2.6V +/-0.1V VDD and VDDQ Power supply  
Programmable Burst Length 2/4/8 with both  
sequential and interleave mode  
Double data rate architecture; two data accesses  
per clock cycle  
•
•
Internal four bank operations with single pulsed RAS  
•
•
Differential Clock inputs (CK & /CK)  
Auto & Self refresh mode  
; 8192 refresh cycles /64ms  
Data inputs on DQS centers when write  
(centered DQ)  
•
Bidirectional data strobes synchronized with output  
data for read and input data for write  
ORDERING INFORMATION  
Part No.  
Power Supply  
Clock Frequency  
CL-tRCD-tRP  
Form Pactor  
HYMD564M646A(L)6-D43  
HYMD564M646A(L)6-D4  
HYMD564M646A(L)6-J  
200MHz (*DDR400)  
200MHz (*DDR400)  
166MHz (*DDR333)  
3-3-3  
3-4-4  
VDD,VDDQ=2.6V  
VDD,VDDQ=2.5V  
200pin Unbuffered SO-DIMM  
67.6mm x 31.75mm x 1mm  
2.5-3-3  
* JEDEC Defined Specifications compliant  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.2 / Apr. 2004  
2
HYMD564M646A(L)6-D43/D4/J  
PIN DESCRIPTION  
Pin  
Pin Description  
Differential Clock Inputs  
Chip Select Input  
Clock Enable Input  
Commend Sets Inputs  
Address  
Pin  
Pin Description  
DQs Power Supply  
Ground  
CK0, /CK0, CK1, /CK1  
CS0, CS1  
VDDQ  
VSS  
CKE0, CKE1  
/RAS, /CAS, /WE  
A0 ~ A12  
VREF  
Reference Power Supply  
Power Supply for SPD  
VDDSPD  
SA0~SA2  
2
E PROM Address Inputs  
2
BA0, BA1  
Bank Address  
SCL  
SDA  
E PROM Clock  
2
DQ0~DQ63  
Data Inputs/Outputs  
E PROM Data I/O  
DQS0~DQS7  
DM0~DM7  
VDD  
Data Strobe Inputs/Outputs  
Data-in Mask  
VDDID  
DU  
VDD Identification Flag  
Do not Use  
Power Supply  
NC  
No Connection  
PIN ASSIGNMENT  
Pin  
Name  
Pin  
Name  
Pin  
Name  
Pin  
Name  
Pin  
Name  
Pin  
Name  
Pin  
Name  
Pin  
Name  
1
A9  
VREF  
2
VREF  
51  
VSS  
52  
VSS  
101  
102  
A8  
151  
DQ42  
152  
DQ46  
3
VSS  
DQ0  
4
VSS  
DQ4  
DQ5  
VDD  
DM0  
DQ6  
VSS  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
73  
75  
77  
79  
81  
83  
85  
87  
89  
91  
93  
95  
97  
99  
DQ19  
DQ24  
VDD  
DQ25  
DQS3  
VSS  
DQ26  
DQ27  
VDD  
NC  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
74  
76  
78  
80  
82  
84  
86  
88  
90  
92  
94  
96  
98  
100  
DQ23  
DQ28  
VDD  
DQ29  
DM3  
VSS  
DQ30  
DQ31  
VDD  
NC  
103  
105  
107  
109  
111  
113  
115  
117  
119  
121  
123  
125  
127  
129  
131  
133  
135  
137  
139  
141  
143  
145  
147  
149  
VSS  
A7  
104  
106  
108  
110  
112  
114  
116  
118  
120  
122  
124  
126  
128  
130  
132  
134  
136  
138  
140  
142  
144  
146  
148  
150  
VSS  
A6  
153  
155  
157  
159  
161  
163  
165  
167  
169  
171  
173  
175  
177  
179  
181  
183  
185  
187  
189  
191  
193  
195  
DQ43  
VDD  
154  
156  
158  
160  
162  
164  
166  
168  
170  
172  
174  
176  
178  
180  
182  
184  
186  
188  
190  
192  
194  
196  
DQ47  
VDD  
/CK1  
CK1  
5
6
7
DQ1  
8
A5  
A4  
VDD  
9
VDD  
DQS0  
DQ2  
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
A3  
A2  
VSS  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
A1  
A0  
VSS  
VSS  
VDD  
A10/AP  
BA0  
VDD  
BA1  
/RAS  
/CAS  
/CS1  
DU  
DQ48  
DQ49  
VDD  
DQ52  
DQ53  
VDD  
DM6  
DQ54  
VSS  
VSS  
DQ3  
DQ7  
DQ12  
VDD  
DQ13  
DM1  
VSS  
DQ8  
/WE  
DQS6  
DQ50  
VSS  
VDD  
DQ9  
/CS0  
DU  
NC  
NC  
DQS1  
VSS  
VSS  
NC  
VSS  
NC  
VSS  
DQ32  
DQ33  
VDD  
DQS4  
DQ34  
VSS  
DQ35  
DQ40  
VDD  
DQ41  
DQS5  
VSS  
VSS  
DQ36  
DQ37  
VDD  
DM4  
DQ38  
VSS  
DQ39  
DQ44  
VDD  
DQ45  
DM5  
VSS  
DQ51  
DQ56  
VDD  
DQ55  
DQ60  
VDD  
DQ61  
DM7  
VSS  
DQ10  
DQ11  
VDD  
CK0  
DQ14  
DQ15  
VDD  
VDD  
VSS  
NC  
NC  
VDD  
NC  
VDD  
NC  
DQ57  
DQS7  
VSS  
DU  
DU  
/CK0  
VSS  
VSS  
NC  
VSS  
VSS  
VDD  
VDD  
CKE0  
DU  
DQ58  
DQ59  
VDD  
DQ62  
DQ63  
VDD  
SA0  
VSS  
DQ16  
DQ17  
VDD  
DQS2  
DQ18  
DQ20  
DQ21  
VDD  
DM2  
DQ22  
NC  
VDD  
CKE1  
NC  
SDA  
SCL  
SA1  
197 VDDSPD 198  
199 VDDID 200  
SA2  
A12  
A11  
DU  
Rev. 0.2 / Apr. 2004  
3
HYMD564M646A(L)6-D43/D4/J  
FUNCTIONAL BLOCK DIAGRAM  
/CS1  
/CS1  
/CS1  
/CS0  
/CS0  
/CS0  
/
CS  
/
CS  
/
C
S
/CS  
D
D
Q
M
S
0
DQQS4  
DQS4  
DQS4  
D
Q
S
LDQS  
L
D
Q
S
L
L
D
Q
S
0
DMM4  
DM4  
DM4  
D
M
L
D
M
LDM  
L
L
D
M
D
D
Q
Q
0
0
DQQ32  
DQ32  
DQ32  
/
O
0
I
/
O
0
I/O 0  
I
I
/
O
0
D
D
Q
Q
1
1
DQQ33  
DQ33  
DQ33  
/
O
1
I
/
O
1
I/O 1  
I
I
/
O
1
D
D
Q
Q
2
2
DQQ34  
DQ34  
DQ34  
/
O
2
I
/
O
2
I/O 2  
I
I/O 2  
D
D
Q
Q
3
3
DQQ35  
DQ35  
DQ35  
/
O
3
I
/
O
3
I/O 3  
I
I
/
O
3
D
D
Q
Q
4
4
DQQ36  
DQ36  
DQ36  
/
O
4
I
/
O
4
I/O 4  
I
I
/
O
4
D
D
Q
Q
5
5
DQQ37  
DQ37  
DQ37  
O
5
I
O
5
/
I/O 5  
I
I
/
O
5
D
D
Q
Q
6
6
DQQ38  
DQ38  
DQ38  
D
0
D
4
D
2
D6  
6
/
O
6
I
/
O
6
I
/
O
I
I
O
6
D
D
Q
Q
7
7
DQQ39  
DQ39  
DQ39  
/
O
7
I
/
O
7
I/O 7  
I
I/  
O
7
UDQS  
UDQS  
UDQS  
U
D
Q
S
DQS55  
DQS5  
DQS5  
DM5  
DM5  
DMM5  
D
M
U
D
M
UDM  
U
U
D
M
D
D
Q
Q
8
8
DQQ40  
DQ40  
DQ40  
/
O
8
I
/
O
8
I/O 8  
I
I
/
O
8
D
D
Q
Q
9
9
DQQ41  
DQ41  
DQ41  
/
O
9
I
/
O
9
I/O 9  
I
I
/
O
9
D
D
Q
Q
1
1
0
0
DQQ42  
DQ42  
DQ42  
/
O
1
0
I
/
O
1
0
I
/
O
1
0
I/O 10  
I
D
D
Q
Q
1
1
1
1
DQQ43  
DQ43  
DQ43  
/
O
1
1
I
/
O
1
1
I
/
O
1
1
I/O 11  
I
D
D
Q
Q
1
1
2
2
DQQ44  
DQ44  
DQ44  
O
1
2
I
O
1
2
I
/
/
O
1
2
I/O 12  
I
D
D
Q
Q
1
1
3
3
DQQ45  
DQ45  
DQ45  
/
O
1
3
I
/
O
1
3
I
O
1
3
I/O 13  
I
D
D
Q
Q
1
1
4
4
DQQ46  
DQ46  
DQ46  
/
O
1
4
I
/
O
1
4
I/  
O
1
4
I/O 14  
I/O 15  
I
D
D
Q
Q
1
1
5
5
DQQ47  
DQ47  
DQ47  
/
O
1
5
I
/
O
1
5
I/  
O
1
5
I
/
C
S
/
CS  
/
C
S
/CS  
D
D
Q
M
S
2
DQS6  
DQS6  
DQS6  
D
Q
S
LDQS  
L
D
Q
S
L
L
D
Q
S
2
DM6  
DM6  
DM6  
D
M
L
D
M
L
D
M
LDM  
L
D
D
Q
Q
1
1
6
6
DQ48  
DQ48  
DQ48  
/
O
0
I
/
O
0
I
/
O
0
I/O 0  
I
D
D
Q
Q
1
1
7
7
DQ49  
DQ49  
DQ49  
/
O
1
I
/
O
1
I
/
O
1
I/O 1  
I
D
D
Q
Q
1
1
8
8
DQ50  
DQ50  
DQ50  
/
O
2
I
/
O
2
I
/
O
2
I/O 2  
I
D
D
Q
Q
1
1
9
9
DQ51  
DQ51  
DQ51  
/
/
O
3
I
/
O
3
I
/
/
O
3
I/O 3  
I
D
D
Q
Q
2
2
0
0
DQ52  
DQ52  
DQ52  
O
4
I
/
O
4
I
O
4
I/O 4  
I
D
D
Q
Q
2
2
1
1
DQ53  
DQ53  
DQ53  
O
5
I/  
O
5
I/  
O
5
I/O 5  
I/  
D
D
Q
Q
2
2
2
2
DQ54  
DQ54  
DQ54  
D
1
D
5
D
I/O 6  
3
D7  
6
/
O
6
I/  
O
6
I
/
O
I
D
D
Q
Q
2
2
3
3
DQ55  
DQ55  
DQ55  
/
O
7
I
/
O
7
I
/
O
7
I/O 7  
I
UDQS  
UDQS  
UDQS  
UDQS  
DQS7  
DQS7  
DQS7  
DM7  
DM7  
DM7  
D
M
U
D
M
U
D
M
UDM  
U
D
D
Q
Q
2
2
4
4
DQ56  
DQ56  
DQ56  
/
O
8
I
/
O
8
I
/
O
8
I/O 8  
I
D
D
Q
Q
2
2
5
5
DQ57  
DQ57  
DQ57  
/
O
9
I
/
O
9
I
/
O
9
I/O 9  
I
D
D
Q
Q
2
2
6
6
DQ58  
DQ58  
DQ58  
/
O
1
0
I
/
O
1
0
I
/
O
1
0
I/O 10  
I
D
D
Q
Q
2
2
7
7
DQ59  
DQ59  
DQ59  
/
O
1
1
I
/
O
1
1
I
/
O
1
1
I/O 11  
I
D
D
Q
Q
2
2
8
8
DQ60  
DQ60  
DQ60  
/
/
O
1
2
I
/
/
O
1
2
I
/
/
O
1
2
I/O 12  
I
D
D
Q
Q
2
2
9
9
DQ61  
DQ61  
DQ61  
O
1
3
I
O
1
3
I
O
1
3
I/O 13  
I
D
D
Q
Q
3
3
0
0
DQ62  
DQ62  
DQ62  
O
1
4
I/  
O
1
4
I/  
O
1
4
I/O 14  
I/  
D
D
Q
Q
3
3
1
1
DQ63  
DQ63  
DQ63  
O
1
5
I/  
O
1
5
I/  
O
1
5
I/O 15  
I/  
.
.
SSPD  
SPD  
VVDDDSSPPD  
VDDSPD  
SSeeriial PPD  
Serial PD  
.
.
==  
=
D0 -- D7  
D0 - D7  
VDD/VVDDDQ  
VDD/VDDQ  
S
S
SA0  
SSA0  
SA1  
SSA1  
SSA2  
SA2  
C
C
L
L
=
=
.
.
=
=
D
D
D0 -- D7  
D0 - D7  
A
0
1
VRREF  
VREF  
SSDA  
SDA  
A
=
. . .. .  
. . . .  
D
D
SStrrap::see  
Strap:see  
WP  
VVSS  
VSS  
0 -- D7  
0 - D7  
A2  
....  
..  
V
V
D
D
D
D
I
I
Notee 4  
Note 4  
B
B
A
A
0
0
-
-
B
B
A
A
1
1
SSDDRAMMss D00 –– D7  
SDRAMs D0 – D7  
Notes:  
Notes:  
A
A
0
0
-
-
A
A
1
1
2
2
SSDDRAMMss D00 –– D7  
SDRAMs D0 – D7  
DQ wiring may differ from that described in this drawing ;  
DQ wiring may differ from that described in this drawing ;  
however DQ/DM/DQS relationship are maintained as shown.  
however DQ/DM/DQS relationship are maintained as shown.  
/
/
R
R
A
A
S
S
SSDDRAMMss D00 –– D7  
SDRAMs D0 – D7  
VDDID strap connections;  
VDDID strap connections;  
(for memory device VDD, VDDQ) :  
(for memory device VDD, VDDQ) :  
/
/
C
C
A
A
S
S
SSDDRAMMss D00 –– D7  
SDRAMs D0 – D7  
/
/
W
W
E
E
SSDDRAMMss D00 –– D7  
SDRAMs D0 – D7  
Strap out :(open) : VDD=VDDQ  
Strap out :(open) : VDD=VDDQ  
C
C
K
K
E
E
0
0
S
S
D
D
R
R
A
A
M
M
s
s
D0  
D0  
–
–
D3  
D3  
Strap In (Vss) : VDD= VDDQ  
Strap In (Vss) : VDD= VDDQ  
C
C
K
K
E
E
1
1
SSDDRAMMzz D44 -- D7  
SDRAMz D4 - D7  
Rev. 0.2 / Apr. 2004  
4
HYMD564M646A(L)6-D43/D4/J  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
Rating  
Unit  
oC  
Operating Temperature (Ambient)  
TA  
0 ~ 70  
oC  
V
Storage Temperature  
TSTG  
-55 ~ 125  
-0.5 ~ 3.6  
-0.5 ~ 3.6  
-0.5 ~ 3.6  
50  
Voltage on Any Pin relative to VSS  
Voltage on VDD relative to VSS  
Voltage on VDDQ relative to VSS  
Output Short Circuit Current  
Power Dissipation  
VIN, VOUT  
VDD  
V
VDDQ  
IOS  
V
mA  
W
PD  
1.0 x # of Components  
260 / 10  
oC / Sec  
Soldering Temperature Þ Time  
TSOLDER  
Note : Operation at above absolute maximum rating can adversely affect device reliability  
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS= 0V)  
Parameter  
Symbol  
Min  
Typ.  
Max  
Unit  
Note  
Power Supply Voltage  
Power Supply Voltage  
Input High Voltage  
Input Low Voltage  
VDD  
2.5  
2.5  
2.6  
2.7  
V
V
V
V
V
V
VDDQ  
VIH  
2.6  
2.7  
1
2
3
VREF + 0.15  
-0.3  
-
-
VDDQ + 0.3  
VREF - 0.15  
VREF + 0.04  
0.51*VDDQ  
VIL  
Termination Voltage  
Reference Voltage  
VTT  
VREF - 0.04  
0.49*VDDQ  
VREF  
0.5*VDDQ  
VREF  
Note :  
1. VDDQ must not exceed the level of VDD.  
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.  
3. The value of VREF is approximately equal to 0.5VDDQ.  
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)  
Parameter  
Symbol  
Min  
Max  
Unit  
Note  
Input High (Logic 1) Voltage, DQ, DQS and DM signals  
Input Low (Logic 0) Voltage, DQ, DQS and DM signals  
Input Differential Voltage, CK and /CK inputs  
VIH(AC)  
VIL(AC)  
VID(AC)  
VIX(AC)  
VREF + 0.31  
V
V
V
V
VREF - 0.31  
VDDQ + 0.6  
0.7  
1
2
Input Crossing Point Voltage, CK and /CK inputs  
0.5*VDDQ-0.2  
0.5*VDDQ+0.2  
Note :  
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.  
2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.  
Rev. 0.2 / Apr. 2004  
5
HYMD564M646A(L)6-D43/D4/J  
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)  
Parameter  
Value  
Unit  
Reference Voltage  
Termination Voltage  
VDDQ x 0.5  
V
V
VDDQ x 0.5  
AC Input High Level Voltage (VIH, min)  
AC Input Low Level Voltage (VIL, max)  
Input Timing Measurement Reference Level Voltage  
Output Timing Measurement Reference Level Voltage  
Input Signal maximum peak swing  
VREF + 0.31  
V
VREF - 0.31  
V
VREF  
VTT  
1.5  
1
V
V
V
Input minimum Signal Slew Rate  
V/ns  
Ω
Termination Resistor (RT)  
50  
Series Resistor (RS)  
25  
Ω
Output Load Capacitance for Access Time Measurement (CL)  
30  
pF  
Rev. 0.2 / Apr. 2004  
6
HYMD564M646A(L)6-D43/D4/J  
CAPACITANCE (T  
A
=25oC, f=100MHz )  
Parameter  
Input Capacitance  
Pin  
Symbol  
Min  
Max  
Unit  
A0 ~ A12, BA0, BA1  
CIN1  
CIN2  
CIN3  
CIN4  
CIN5  
CIN6  
CIO1  
36  
36  
28  
28  
18  
12  
12  
48  
48  
40  
40  
27  
18  
18  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
Input Capacitance  
/RAS, /CAS, /WE  
CKE0, CKE1  
/CS0, /CS1  
Input Capacitance  
Input Capacitance  
Input Capacitance  
CK0, /CK0, CK1, /CK1  
DM0 ~ DM7  
Input Capacitance  
Data Input / Output Capacitance  
DQ0 ~ DQ63, DQS0 ~ DQS7  
Note :  
1. VDD = min. to max., VDDQ = 2.5V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V  
2. Pins not under test are tied to GND.  
3. These values are guaranteed by design and are tested on a sample basis only.  
OUTPUT LOAD CIRCUIT  
V
TT  
Ω
R =50  
T
Output  
Ω
Zo=50  
V
REF  
C =30pF  
L
Rev. 0.2 / Apr. 2004  
7
HYMD564M646A(L)6-D43/D4/J  
DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V)  
Parameter  
Symbol  
Min.  
Max  
Unit  
Note  
Add, CMD, /CS, /CKE  
-16  
16  
Input Leakage  
Current  
CK0, /CK0, CK1, /CK1  
CK2, /CK2  
ILI  
-8  
8
uA  
1
0
0
Output Leakage Current  
Output High Voltage  
Output Low Voltage  
ILO  
VOH  
VOL  
-10  
10  
uA  
V
2
VTT + 0.76  
-
-
IOH = -15.2mA  
IOL = +15.2mA  
VTT - 0.76  
V
Note :  
1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V  
2. DOUT is disabled, VOUT=0 to 2.7V  
Rev. 0.2 / Apr. 2004  
8
HYMD564M646A(L)6-D43/D4/J  
DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)  
Speed  
D4  
Parameter  
Operating Current  
Operating Current  
Symbol  
IDD0  
Test Condition  
Unit Note  
D43  
J
One bank; Active - Precharge; tRC=tRC(min);  
tCK=tCK(min); DQ,DM and DQS inputs changing  
twice per clock cycle ; address and control inputs  
changing once per clock cycle  
640  
600  
mA  
mA  
One bank; Active - Read - Precharge; Burst Length =2;  
tRC=tRC(min); tCK=tCK(min); address and control  
inputs changing once per clock cycle  
IDD1  
840  
760  
Precharge Power  
Down Standby Current  
All banks idle; Power down mode; CKE=Low, tCK=  
tCK(min)  
IDD2P  
IDD2N  
80  
mA  
mA  
Idle Standby Current  
Idle Standby Current  
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM  
180  
/CS=High, All banks idle; tCK=tCK(min); CKE= High;  
address and control inputs changing once per clock  
cycle. VIN=VREF for DQ, DQS and DM  
IDD2F  
180  
mA  
/CS>=Vih(min); All banks idle; CKE>=Vih(min);  
Addresses and other control inputs stable, Vin=Vref for  
DQ, DQS and DM  
Idle Quiet Standby  
Current  
IDD2Q  
IDD3P  
140  
96  
180  
mA  
mA  
Active Power Down  
Standby Current  
One bank active ; Power down mode; CKE=Low,  
tCK=tCK(min)  
120  
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;  
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS  
inputs changing twice per clock cycle; Address and  
other control inputs changing once per clock cycle  
Active Standby Current  
Operating Current  
Operating Current  
IDD3N  
IDD4R  
IDD4W  
IDD5  
240  
220  
mA  
Burst=2; Reads; Continuous burst; One bank active;  
Address and control inputs changing once per clock  
cycle; tCK=tCK(min); IOUT=0mA  
1120  
1120  
1040  
1040  
1080  
Burst=2; Writes; Continuous burst; One bank active;  
Address and control inputs changing once per clock  
cycle; tCK=tCK(min); DQ, DM, and DQS inputs  
changing twice per clock cycle  
mA  
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,  
10*tCK for DDR266A & DDR266B at 133Mhz;  
distributed refresh  
Auto Refresh Current  
Self Refresh Current  
1240  
Normal  
40  
20  
mA  
mA  
CKE=<0.2V; External clock on; tCK  
IDD6  
IDD7  
=tCK(min)  
Low Power  
Operating Current -  
Four Bank Operation  
Four bank interleaving with BL=4 Refer to the following  
page for detailed test condition  
2200  
2200  
1880  
1880  
mA  
4banks active read with activate every 20ns, AP(Auto  
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0  
mA, 100% DQ, DM and DQS inputs changing twice  
per clock cycle; 100% addresses changing once per  
clock cycle  
Random Read Current  
IDD7A  
mA  
Rev. 0.2 / Apr. 2004  
9
HYMD564M646A(L)6-D43/D4/J  
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)  
D43(DDR400)  
D4(DDR400)  
J(DDR333)  
Parameter  
Row Cycle Time  
Symbol  
Unit  
Note  
Min  
55  
Max  
Min  
58  
Max  
Min  
60  
Max  
tRC  
tRFC  
tRAS  
-
-
-
-
-
-
ns  
ns  
ns  
Auto Refresh Row Cycle Time  
Row Active Time  
70  
70  
72  
40  
70K  
40  
70K  
42  
70K  
tRCD or  
tRASmin  
tRCD or  
tRASmin  
tRCD or  
tRASmin  
Active to Read with Auto Precharge Delay  
tRAP  
-
-
-
ns  
16  
Row Address to Column Address Delay  
Row Active to Row Active Delay  
tRCD  
tRRD  
15  
10  
-
-
18  
10  
-
-
18  
12  
-
-
ns  
ns  
Column Address to Column Address  
Delay  
tCCD  
1
-
1
-
1
-
CK  
Row Precharge Time  
tRP  
tWR  
tWTR  
15  
15  
2
-
-
-
18  
15  
2
-
-
-
18  
15  
1
-
-
-
ns  
ns  
Write Recovery Time  
Write to Read Command Delay  
CK  
Auto Precharge Write  
Recovery+Precharge Time  
(tWR/tCK)+  
(tRP/tCK)  
(tWR/tCK)+  
(tRP/tCK)  
(tWR/tCK)+  
(tRP/tCK)  
tDAL  
-
-
-
CK  
15  
CL=3  
5
-
10  
-
5
-
10  
-
-
6
-
ns  
ns  
ns  
CK  
CK  
ns  
ns  
ns  
System Clock Cycle  
CL = 2.5  
tCK  
12  
Time  
CL = 2  
-
-
-
-
7.5  
0.45  
0.45  
-0.7  
-0.55  
-
12  
Clock High Level Width  
tCH  
tCL  
0.45  
0.45  
-0.7  
-0.55  
-
0.55  
0.55  
0.7  
0.55  
0.4  
0.45  
0.45  
-0.7  
-0.55  
-
0.55  
0.55  
0.7  
0.55  
0.4  
0.55  
0.55  
0.7  
Clock Low Level Width  
Data-Out edge to Clock edge Skew  
DQS-Out edge to Clock edge Skew  
DQS-Out edge to Data-Out edge Skew  
tAC  
tDQSCK  
tDQSQ  
0.55  
0.45  
tHPmin  
-tQHS  
tHPmin  
-tQHS  
tHPmin  
-tQHS  
Data-Out hold time from DQS  
tQH  
-
-
-
ns  
1, 10  
tCH/L  
min  
tCH/L  
min  
tCH/L  
min  
Clock Half Period  
tHP  
tQHS  
tHZ  
-
-
-
ns  
ns  
ns  
1,9  
10  
Data Hold Skew Factor  
-
0.5  
-
0.5  
-
0.55  
0.7  
Data-out high-impedance window from  
CK, /CK  
tAC  
(Max)  
tAC  
(Max)  
-0.7  
Data-out low-impedance window from CK,  
/CK  
tAC  
(Min)  
tAC  
(Max)  
tAC  
(Min)  
tAC  
(Max)  
tLZ  
tIS  
tIH  
tIS  
-0.7  
0.75  
0.75  
0.8  
0.7  
ns  
ns  
ns  
ns  
2,3,5,  
6
Input Setup Time (fast slew rate)  
Input Hold Time (fast slew rate)  
Input Setup Time (slow slew rate)  
0.6  
0.6  
0.7  
-
-
-
0.6  
0.6  
0.7  
-
-
-
-
-
-
2,3,5,  
6
2,4,5,  
6
2,4,5,  
6
Input Hold Time (slow slew rate)  
Input Pulse Width  
tIH  
0.7  
2.2  
-
-
0.7  
2.2  
-
-
0.8  
2.2  
-
-
ns  
ns  
tIPW  
6
Rev. 0.2 / Apr. 2004  
10  
HYMD564M646A(L)6-D43/D4/J  
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)  
- continued -  
D43(DDR400)  
D4(DDR400)  
J(DDR333)  
Parameter  
Symbol  
Unit  
Note  
Min  
0.35  
0.35  
0.72  
Max  
Min  
0.35  
0.35  
0.72  
Max  
Min  
0.35  
0.35  
0.75  
Max  
Write DQS High Level Width  
Write DQS Low Level Width  
tDQSH  
tDQSL  
tDQSS  
-
-
-
-
-
-
CK  
CK  
CK  
Clock to First Rising edge of DQS-In  
1.28  
1.28  
1.25  
6,7,  
11~13  
Data-In Setup Time to DQS-In (DQ & DM)  
Data-in Hold Time to DQS-In (DQ & DM)  
tDS  
tDH  
0.4  
0.4  
-
-
0.4  
0.4  
-
-
0.45  
0.45  
-
-
ns  
ns  
6,7,  
11~13  
DQ & DM Input Pulse Width  
Read DQS Preamble Time  
Read DQS Postamble Time  
Write DQS Preamble Setup Time  
Write DQS Preamble Hold Time  
Write DQS Postamble Time  
Mode Register Set Delay  
tDIPW  
tRPRE  
tRPST  
1.6  
0.9  
0.4  
0
-
1.1  
0.6  
-
1.6  
0.9  
0.4  
0
-
1.1  
0.6  
-
1.75  
0.9  
0.4  
0
-
1.1  
0.6  
-
ns  
CK  
CK  
CK  
CK  
CK  
CK  
tWPRES  
tWPREH  
tWPST  
tMRD  
0.25  
0.4  
2
-
0.25  
0.4  
2
-
0.25  
0.4  
2
-
0.6  
-
0.6  
-
0.6  
-
Exit Self Refresh to Any Execute  
Command  
tXSC  
tREFI  
200  
-
-
200  
-
-
200  
-
-
CK  
us  
8
Average Periodic Refresh Interval  
7.8  
7.8  
7.8  
Note :  
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.  
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.  
3. For command/address input slew rate >=1.0V/ns  
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns  
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.  
Input Setup / Hold Slew-rate Derating Table.  
Input Setup / Hold Slew-rate  
Delta tIS  
ps  
Delta tIH  
V/ns  
0.5  
ps  
0
0
0.4  
+50  
0
0.3  
+100  
0
5. CK, /CK slew rates are >=1.0V/ns  
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by  
design or tester correlation  
7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.  
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete  
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.  
9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this  
value can be greater than the minimum specification limits for tCL and tCH).  
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of  
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to  
n-channel variation of the output drivers.  
Rev. 0.2 / Apr. 2004  
11  
HYMD564M646A(L)6-D43/D4/J  
11.This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.  
Input Setup / Hold Slew-rate Derating Table.  
Input Setup / Hold Slew-rate  
Delta tDS  
Delta tDH  
V/ns  
0.5  
ps  
0
ps  
0
0.4  
+75  
+150  
+75  
+150  
0.3  
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF  
+/-310mV for a duration of up to 2ns.  
I/O Input Level  
mV  
Delta tDS  
ps  
Delta tDH  
ps  
+280  
+50  
+50  
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS  
slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns  
and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.  
(1/SlewRate1)-(1/SlewRate2)  
Delta tDS  
Delta tDH  
ns/V  
0
ps  
0
ps  
0
+/-0.25  
+/- 0.5  
+50  
+100  
+50  
+100  
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi  
tions through the DC region must be monotonic.  
15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK  
is equal to the actual system clock cycle time.  
Example: For DDR400(D4) at CL=3 and tCK = 5 ns,  
tDAL = (15.0 ns / 5.0 ns) + (18.0ns / 5.0ns) = (3.00) + (3.60)  
Round up each non-integer to the next highest integer: = (3) + (4), tDAL = 7clock  
16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be  
tRAS - BL/2 x tCK.  
Rev. 0.2 / Apr. 2004  
12  
HYMD564M646A(L)6-D43/D4/J  
SIMPLIFIED COMMAND TRUTH TABLE  
A10/  
AP  
ADDR  
Command  
CKEn-1  
CKEn  
/CS  
/RAS  
/CAS  
/WE  
BA  
Note  
Extended Mode Register Set  
Mode Register Set  
Device Deselect  
No Operation  
H
H
X
X
L
L
H
L
L
L
L
L
L
L
L
OP code  
OP code  
1,2  
1,2  
X
H
L
X
H
H
X
H
H
H
H
H
X
X
X
X
1
Bank Active  
RA  
V
V
1
1
Read  
L
H
L
L
L
L
H
H
L
L
L
H
L
L
CA  
CA  
X
Read with Autoprecharge  
Write  
1,3  
1
H
H
X
X
V
Write with Autoprecharge  
Precharge All Banks  
Precharge selected Bank  
Read Burst Stop  
Auto Refresh  
H
H
L
1,4  
1,5  
1
X
V
H
H
H
H
X
H
L
L
L
H
L
H
L
L
H
H
X
H
X
H
X
H
X
V
X
X
1
1
Entry  
L
L
L
1
Self Refresh  
Exit  
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
L
H
L
H
L
1
H
L
1
1
1
1
1
1
1
Entry  
Precharge  
Power Down  
H
L
Mode  
Exit  
H
H
L
Active Power  
Down Mode  
(Clock Suspend)  
Entry  
Exit  
H
L
L
H
X
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )  
Note :  
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.  
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.  
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP  
period from Prechagre command.  
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented  
to activated bank until CK(n+BL/2+tRP).  
4. If a Write with Autoprecharge command is detected by memory compoment in CK(n), then there will be no command presented  
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time  
(tWR) is needed to guarantee that the last data has been completely written.  
5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be  
precharged.  
Rev. 0.2 / Apr. 2004  
13  
HYMD564M646A(L)6-D43/D4/J  
PACKAGE DIMENSIONS  
Front  
67.60 mm  
2.00 mm  
Component  
Keepout  
Area  
2.00 mm  
31.75 mm  
20.00 mm  
1
39  
41  
199  
Side  
Back  
3.8mm  
2.0 mm  
2.0 mm  
MAX.  
2
40  
42  
200  
(Front)  
1.1mm  
MAX.  
Rev. 0.2 / Apr. 2004  
14  
SERIAL PRESENCE DETECT  
SPD SPECIFICATION  
(64Mx64 Unbuffered DDR SO-DIMM)  
Rev. 0.2 / Apr. 2004  
15  
HYMD564M646A(L)6-D43/D4/J  
SERIAL PRESENCE DETECT  
Bin Sort : D43(DDR400@CL=3, D4(DDR400@CL=3), J(DDR333@CL=2.5)  
Function Supported  
Hexa Value  
D4  
Byte#  
Function Description  
Note  
D43  
D4  
J
D43  
J
0
Number of Bytes written into serial memory at module  
manufacturer  
128 Bytes  
80h  
1
2
Total number of Bytes in SPD device  
Fundamental memory type  
256 Bytes  
DDR SDRAM  
13  
08h  
07h  
0Dh  
0Ah  
02h  
40h  
00h  
04h  
50h  
70h  
00h  
82h  
10h  
00h  
3
Number of row address on this assembly  
Number of column address on this assembly  
Number of physical banks on DIMM  
Module data width  
1
1
4
10  
5
2Bank  
6
64 Bits  
-
7
Module data width (continued)  
8
Module voltage Interface levels(VDDQ)  
DDR SDRAM cycle time at CAS Latency=2.5(tCK)  
DDR SDRAM access time from clock at CL=2.5 (tAC)  
Module configuration type  
SSTL 2.5V  
5.0ns  
9
5.0ns  
6.0ns  
50h  
60h  
2
2
10  
11  
12  
13  
14  
15  
+/-0.7ns  
Non-ECC  
Refresh rate and type  
7.8us & Self refresh  
Primary DDR SDRAM width  
x16  
N/A  
Error checking DDR SDRAM data width  
Minimum clock delay for back-to-back random column  
address(tCCD)  
1 CLK  
01h  
16  
17  
18  
Burst lengths supported  
2,4,8  
0Eh  
04h  
Number of banks on each DDR SDRAM  
CAS latency supported  
4 Banks  
2, 2.5, 3  
2, 2.5  
1Ch  
0Ch  
19  
20  
21  
22  
CS latency  
0
1
01h  
02h  
20h  
WE latency  
DDR SDRAM module attributes  
DDR SDRAM device attributes : General  
Differential Clock Input  
+/-0.2Voltage tolerance,  
Concurrent Auto Precharge  
tRAS Lock Out  
C0h  
23  
24  
25  
DDR SDRAM cycle time at CL=2.0(tCK)  
6.0ns  
6.0ns  
7.5ns  
60h  
60h  
70h  
75h  
DDR SDRAM access time from clock at CL=2.0(tAC)  
DDR SDRAM cycle time at CL=1.5(tCK)  
+/-0.7ns  
7.5ns  
75h  
75h  
00h  
00h  
48h  
-
-
26  
DDR SDRAM access time from clock at CL=1.5(tAC)  
+/-0.75ns  
27  
28  
29  
30  
31  
32  
33  
34  
35  
Minimum row precharge time(tRP)  
15ns  
18ns  
10ns  
18ns  
12ns  
18ns  
42ns  
3Ch  
28h  
3Ch  
28h  
48h  
28h  
48h  
28h  
40h  
60h  
60h  
40h  
40h  
00h  
3Ah  
Minimum row activate to row active delay(tRRD)  
Minimum RAS to CAS delay(tRCD)  
Minimum active to precharge time(tRAS)  
Module row density  
10ns  
15ns  
40ns  
30h  
48h  
2Ah  
18ns  
40ns  
256MB  
0.60ns  
0.60ns  
0.40ns  
0.40ns  
Undefined  
58ns  
Command and address signal input setup time(tIS)  
Command and address signal input hold time(tIH)  
Data signal input setup time(tDS)  
0.60ns  
0.60ns  
0.40ns  
0.40ns  
0.75ns  
0.75ns  
0.45ns  
0.45ns  
60h  
60h  
40h  
40h  
75h  
75h  
45h  
45h  
Data signal input hold time(tDH)  
36~40 Reserved for VCSDRAM  
41  
Minimum active / auto-refresh Time (tRC)  
55ns  
70ns  
60ns  
72ns  
37h  
46h  
3Ch  
48h  
Minimum auto-refresh to active / auto-refresh  
command period (tRFC)  
42  
70ns  
46h  
43  
Maximum cycle time (tCK max)  
10ns  
10ns  
12ns  
28h  
28h  
28h  
30h  
44  
45  
Maximum DQS-DQ skew time (tDQSQ)  
0.40ns  
0.50ns  
0.40ns  
0.45ns  
0.55ns  
28h  
50h  
2Dh  
55h  
Maximum read data hold skew factor (tQHS)  
0.50ns  
Undefined  
Initial release  
-
50h  
00h  
00h  
8Ah  
46~61 Superset Information(may be used in future)  
62  
63  
SPD Revision code  
Checksum for Bytes 0~62  
6Fh  
09h  
Rev. 0.2 / Apr. 2004  
16  
HYMD564M646A(L)6-D43/D4/J  
SERIAL PRESENCE DETECT(continued)  
Function Supported  
Hexa Value  
D4  
Byte #  
Function Description  
Manufacturer JEDEC ID Code  
Note  
D43  
D4  
J
D43  
J
64  
Hynix JEDEC ID  
-
ADh  
00h  
65~71  
--------- Manufacturer JEDEC ID Code  
Hynix(Korea Area)  
0*h  
1*h  
2*h  
3*h  
4*h  
5*h  
HSA(United States Area)  
HSE(Europe Area)  
HSJ(Japan Area)  
Singapore  
72  
Manufacturing location  
6
Asia Area  
73  
74  
Manufacture part number(Hynix Memory Module)  
-------- Manufacture part number(Hynix Memory Module)  
-------- Manufacture part number(Hynix Memory Module)  
Manufacture part number (DDR SDRAM)  
Manufacture part number(Memory density)  
Manufacture part number(Module Depth)  
------- Manufacture part number(Module Depth)  
Manufacture part number(Module type)  
Manufacture part number(Data width)  
H
48h  
59h  
4Dh  
44h  
35h  
36h  
34h  
4Dh  
36h  
34h  
36h  
41h  
36h  
2Dh  
44h  
34h  
20h  
20h  
-
Y
75  
M
76  
D
77  
5
78  
6
79  
4
80  
M
81  
6
82  
-------Manufacture part number(Data width)  
Manufacture part number(Refresh, # of Bank.)  
Manufacture part number(Component Generation)  
Manufacture part number(Component configuration)  
Manufacture part number(Hyphen)  
4
83  
6(8K refresh,4Bank)  
84  
A
6
85  
86  
‘-’  
87  
Manufacture part number(Minimum cycle time)  
Manufacture part number(Minimum cycle time)  
Manufacture part number(Minimum cycle time)  
Manufacture part number(T.B.D)  
D
4
3
D
J
44h  
34h  
33h  
4Ah  
20h  
20h  
88  
4
Blank  
Blank  
89  
Blank  
90  
Blank  
91  
Manufacture revision code(for Component)  
Manufacture revision code (for PCB)  
-
92  
-
-
93  
Manufacturing date(Year)  
-
-
3
3
4
5
5
94  
Manufacturing date(Week)  
-
-
95~98  
99~127  
Module serial number  
-
-
Manufacturer specific data (may be used in future)  
Undefined  
Undefined  
00h  
00h  
128~255 Open for customer use  
Note :  
1. The bank address is excluded  
2. These value is based on the component specification  
3. These bytes are programmed by code of date week & date year  
4. These bytes apply to Hynix’s own Module Serial Number system  
5. These bytes undefined and coded as ‘00h’  
6. Refer to Hynix web site  
Byte 85~86, Low power part  
Function Supported  
Hexa Value  
D4  
Byte#  
Function Description  
Note  
D43  
D4  
J
D43  
J
85  
86  
Manufacture part number(Low power part)  
Manufacture part number(Component Configuration)  
L
6
4Ch  
36h  
Rev. 0.2 / Apr. 2004  
17  
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