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OZ965G

型号：

OZ965G

描述：

高效率逆变控制器[ High-Efficiency Inverter Controller ]

品牌：

ETC[ ETC ]

页数：

7 页

PDF大小：

69 K

下载PDF手册
OZ965  
High-Efficiency Inverter Controller  
FEATURES  
dimming function with an analog voltage or low  
frequency Pulse Width Modulation (PWM)  
control.  
•
Single-stage power conversion, requiring  
only a +5 V voltage source  
Reduces the number of components and  
board size by 30% compared with  
conventional design  
•
Operating Principle:  
The CCFL tube, transformer secondary, and  
capacitor form a resonant circuit. The OZ965  
utilizes the low energy loss resonate mode  
principle to deliver a very high efficiency inverter.  
•
•
•
Supports both floating and grounded  
secondary designs  
90% efficiency vs. typical 75% efficiency of  
conventional designs  
Internal open-lamp and short-circuit  
protections  
Wide dimming range  
Supports multiple CCFLs  
Simple and reliable 2-winding transformer  
design  
Eliminates leakage current when used in a  
floating secondary design  
The OZ965 drives the transformer primary with a  
variable pulse width voltage directly from the +5v  
supply. The resultant primary drive current is  
alternately reversing with zero-voltage-switching.  
Because of the transformer leakage inductance  
and the secondary resonant circuit, the  
secondary voltage and current are approximately  
sinusoidal. This sinusoid results in very little  
harmonic emi/rfi emissions.  
•
•
•
•
•
Constant-frequency  
design  
eliminates  
interference with LCDs  
The OZ965 operates at a single, constant  
frequency in a PWM mode. Typical operating  
frequency ranges between 30 KHz to 200 KHz,  
dependent upon the CCFL and transformer  
characteristics. Intelligent open-lamp protection  
provides design flexibility so various transformer  
models/manufacturers may be used.  
ORDERING INFORMATION  
OZ965G - 16-pin plastic SOP  
OZ965R - 16-pin plastic TSSOP  
OZ965IG - 16-pin plastic SOP  
OZ965IR - 16-pin plastic TSSOP  
Its high driving capability allows the OZ965 to  
drive high power MOSFETs.  
GENERAL DESCRIPTION  
The single stage design results in a low cost,  
reliable transformer without expensive, less  
reliable secondary fold-back treatment. The  
transformer does not require a more expensive  
center tapped primary.  
The OZ965 is a single chip, high-efficiency, Cold  
Cathode Fluorescent Lamp (CCFL) backlight  
inverter controller whose primary function is to  
convert +5 volt DC power to approximately 600  
VAC. Additionally, the OZ965 performs the lamp  
The OZ965 is available in 16-pin SOP and  
TSSOP packages. It is specified over the  
commercial temperature range of 0°C to +70°C,  
and the industrial temperature range of -40°C to  
+85°C.  
Figure 1. Typical Application Circuit  
J1  
1
5V  
5V  
2
3
4
5
6
ENA  
DIM  
GND  
GND  
C2  
22u  
100k  
R1  
C1  
R2  
22  
0.1u  
R3  
150k  
C3  
10u  
R4  
20k  
C4  
0.1u  
R5  
15k  
C5  
J2  
2
17:2200  
5
7
6
1
2
59.0k  
R6  
HV  
RTN  
U1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
68p 3kv  
REF  
VDD  
RT  
CT  
OPS  
ENA  
NDR  
PDR  
SST  
U2  
HCLMP  
LCLMP  
SCP  
ADJ  
FB  
CMP  
GND  
2
1
8
7
470p  
C6  
T1  
Q1  
Q2  
C7  
10u  
4
3
6
5
C9  
0.01u  
C10  
2.2u  
OZ965  
C8  
0.1u  
Si4532  
2
CR3  
BAV99L  
R13  
510k  
C11  
0.1u  
R15  
4.3k  
R16  
100k  
R17  
1.02k  
C12  
0.1u  
06/20/00  
Copyright 2000 by O2Micro  
OZ965-SF-3.0  
All Rights Reserved  
Page 1  
U.S. Patent #5,619,402  
OZ965  
“Soft start” gradually increases the energy  
delivered to the secondary.  
FUNCTIONAL BLOCK  
DIAGRAM  
When the OZ965 is enabled at pin ENA, the  
capacitor on pin SST determines the duration of  
the “soft-start” period, gradually increasing the  
NDR pulse width to the regulated brightness. The  
“soft-start” period provides sufficient time for the  
lamp to ignite.  
Refer to the functional block diagram in Figure 2,  
below, and the Pin Description Table on page 3.  
Power is transferred to the transformer primary  
by the N-MOSFET, driven by the MOSFET gate  
driver out of pin NDR. The P-MOSFET resets the  
primary field, driven by pin PDR. The usual  
design results in approximately 50% duty cycle at  
full lamp intensity. Terminating the NDR signal  
earlier than the full brightness lamp pulse width  
performs lamp dimming, using the analog  
dimming. The voltages on pins HCLMP and  
LCLMP set a threshold voltage for the ramp  
comparator setting the maximum duty cycle for  
NDR.  
For system reliability there are several circuit  
protections provided. To ensure a controlled  
output, the secondary current is monitored on pin  
FB and is compared to a reference voltage on pin  
ADJ. The NDR signal is shortened or lengthened  
dependent upon this feedback. Protection is  
provided by the resultant signal, CMP, monitoring  
for a lamp removal condition. Short circuit  
protection is provided at pin SCP. The OPS  
signal selects either HCLMP or LCLMP providing  
current protection against an “Open Lamp”  
condition at start-up. The OPS signal also allows  
adjustment to different transformer models.  
A pulse generator circuit creates the clock signal  
with the frequency determined by an external,  
constant current setting resistor (RT) and timing  
capacitor (CT).  
To reduce power dissipation, the switch  
(MOSFET) drive signals are “break-before-make”  
with a short, fixed off time between activation of  
The “soft-start” circuit ensures a reliable and long  
lamp life starting condition.  
NDR or PDR.  
Vdd  
16  
REF  
IBIAS  
&
2.50V  
POFF  
1
REFERENCE  
HCLMP  
2
Vset  
RT  
+
+
Vmax  
Vmax=2.6V-Vset  
RAMP  
COMP.  
15  
V>Vmax -- -> Vmax  
Vmin<V<Vmax ->V  
V<Vmin -- ->Vmin  
V
-
-
2.5V  
+
LCLMP  
3
COMP  
-
PULSE GEN  
Vmin  
(fix value)  
CT  
+
COMP  
COMP  
14  
SCP  
4
0.5V  
-
0.6V  
+
LAMP  
OPS  
13  
ON/OFF  
ADJ  
5
-
Vdd  
RESET  
UVLO  
UNDER VOLTAGE  
LOCKOUT  
+
-
SS1  
EA  
ENA  
12  
+
ENABLE  
FB  
6
COMP  
R1  
t1  
300k  
ACTIVE  
"HIGH"  
-
(slow start)  
1.5V  
ZVS  
CONTROLLER  
PDR  
11  
CMP  
7
PDRV  
NDRV  
Pgate  
R4  
70k  
NDR  
10  
Ngate  
I=12uA  
SS1  
+
PROTECTION  
OLPROT  
COMP  
2.5V  
R5  
-
I=2.5uA  
630k  
SS2  
GND  
8
SST  
9
t1+t2  
(slow start)  
V_SS2  
R2  
4K  
MN1  
POFF  
Note:  
OVP – Over Voltage Protection  
SCP – Short-Circuit Protection  
UVL – Under Voltage Lockout  
Figure 2. Functional Block Diagram  
OZ965-SF-3.0  
Page 2  
OZ965  
PIN DESCRIPTION  
Names  
REF  
HCLMP  
LCLMP  
SCP  
ADJ  
FB  
CMP  
GND  
SST  
Pin No.  
I/O  
O
I
I
I
I
I
O
GND  
I
Description  
1
2
3
4
5
6
7
8
9
Reference voltage output. Nominal voltage is 2.5 V.  
Clamping maximum duty cycle under normal operation.  
Clamping maximum duty cycle under open-lamp condition.  
Short-circuit protection input (VTH=0.6V)  
Reference voltage input for dimming control.  
Current sense feedback.  
Compensation for the current sense feedback.  
Ground.  
Soft-start ensures lamp current pulses gradually increases to its normal  
value  
PDR  
NDR  
ENA  
OPS  
CT  
10  
11  
12  
13  
14  
15  
O
O
I
Gate drive output for the P-MOSFET.  
Gate drive output for the N-MOSFET.  
Enable input, active high (VTH=1.5V)  
Output current sense (VTH=0.6V)  
I
I/O  
I/O  
Timing capacitor. CT and RT set the clock frequency.  
RT  
Timing resistor. Fosc = 1.91 / (Rt • Ct)  
VDD  
16  
PWR  
Supply voltage input.  
ABSOLUTE MAXIMUM RATINGS  
VDD  
5.5V  
OZ965  
OZ965I  
GND  
+/- 0.3V  
Power dissipation  
-
-
16-pin SOP  
16-pin TSSOP  
.720W  
.690W  
.580W  
.550W  
Logic inputs  
-0.3 V to VDD+0.3V  
Thermal Impedance  
-
-
16-pin SOP  
16-pin TSSOP  
111oC/W  
115oC/W  
111oC/W  
115oC/W  
OZ965  
0oC to 70oC  
OZ965I  
-40oC to 85oC  
Operating temp.  
Operating junction temp.  
Storage temp.  
150oC  
-55oC to 150oC  
RECOMMENDED OPERATING RANGE  
VDD  
5.0 V +/- 5%  
30 KHz to 200 KHz  
50 k to 150 k  
Fosc  
Rosc  
OZ965-SF-3.0  
Page 3  
OZ965  
FUNCTIONAL SPECIFICATIONS  
Parameter  
Symbol  
Test Conditions  
Limits  
Unit  
4.75 V < VDD < 5.25 V  
Min  
Typ  
Max  
Reference Voltage  
Nominal voltage  
Line regulation  
Load regulation  
Oscillator  
Vref  
Iload = 0.1 mA,  
2.37  
2.50  
6
2.63  
V
-
-
-
-
mV/V  
mV/mA  
Iload = 0.2 mA to 1.0 mA  
Ct = 470 pF, Rt = 49.9 k  
1
Initial accuracy  
Ramp peak  
fosc  
81  
2.54  
0.48  
-
KHz  
-
-
-
-
-
V
V
Ramp valley  
Temp. stability  
Error Amplifier  
Input bias current  
Input offset voltage  
Input voltage range  
TA = -40oC to 85oC  
200  
ppm/ oC  
ADJ=FB=2.0 V  
VFB = 4.0 V  
-
0.25  
-
uA  
mV  
V
5
-
10  
0
VDD-  
1.5  
Open loop voltage gain  
Unity gain bandwidth  
-
-
-
65  
1.5  
60  
-
-
-
dB  
MHz  
dB  
Power supply rejection  
Under-Voltage Lockout  
Positive-going threshold voltage  
Negative-going threshold voltage  
Supply  
See Table 1, page 5  
See Table 1, page 5  
Supply current - Enable Low  
IOFF  
ION  
-
-
195  
1.0  
-
-
µA  
Supply current - Enable High  
NDR output  
VDD = 5.0 V  
mA  
Output high voltage  
Output low voltage  
Output resistance  
PDR output  
VOH  
VOL  
Isource = 10 mA, VDD = 5V  
Isink = 10 mA, VDD = 5V  
-
-
-
4.75  
0.25  
10  
-
0.5  
-
V
V
Ω
ROUT  
Output high voltage  
Output low voltage  
Output resistance  
Break-Before-Make  
Qn off to Qp on delay  
Qp off to Qn on delay  
High Clamp  
VOH  
VOL  
Isource = 10 mA, VDD = 5V  
Isink = 10 mA, VDD = 5V  
-
-
-
4.7  
0.5  
15  
-
-
V
V
Ω
ROUT  
-
THL  
TLH  
-
-
250  
220  
-
-
ns  
Ns  
Duty cycle of NDR  
HCLMP  
LCLMP  
OPS=1 V VHCLMP=0V  
92  
-
94  
14  
96  
-
%
%
%
OPS=1 V, VHCLMP=1.8V  
Low Clamp  
Duty cycle of NDR  
OPS=0 V, VLCLMP=0V  
OPS=0 V, VLCLMP=1.8V  
92  
-
94  
14  
96  
-
Max. / Min. Duty cycle  
Duty cycle of NDR  
6
-
95  
OZ965-SF-3.0  
Page 4  
OZ965  
OZ965  
Limits  
OZ965I  
Limits  
Parameter  
Test Conditions  
Unit  
Unit  
4.75V < VDD < 5.25V  
Min  
Typ  
Max  
Min  
Typ  
Max  
Under-Voltage Lockout  
-
3.9  
3.4  
4.3  
-
V
V
Positive-going threshold voltage  
Negative-going threshold voltage  
-
3.9  
3.4  
4.5  
-
V
V
3.2  
3.0  
Table 1. Under-Voltage Lockout for OZ965 and OZ965I  
OZ965-SF-3.0  
Page 5  
OZ965  
PACKAGE INFORMATION  
A2 A1  
A
16  
TSSOP-16  
PACKAGE  
E
E1  
1
θ
2
D
R1  
Gauge Plane  
R
b
e
b
θ
1
L
c
c1  
θ
3
L1  
b1  
DIM  
INCHES  
MIN MAX  
MILLIMETERS  
Lead Cross Section  
MIN  
-
MAX  
1.20  
0.15  
1.05  
0.75  
5.10  
4.50  
A
A1  
A2  
L
D
E1  
E
-
0.043  
0.006  
0.041  
0.030  
-
0.002  
0.031  
0.020  
-
0.169  
0.252BSC  
0.05  
0.80  
0.45  
4.90  
4.30  
0.177  
6.40BSC  
R
R1  
b
b1  
c
c1  
L1  
e
0.004  
0.004  
0.007  
0.007  
0.004  
0.004  
0.039REF  
0.026BSC  
0° 8°  
-
-
0.09  
0.09  
0.19  
0.19  
0.09  
0.09  
1.0REF  
0.65BSC  
0° 8°  
-
-
0.012  
0.010  
0.008  
0.006  
0.30  
0.25  
0.20  
0.16  
θ1  
θ2  
θ3  
12°REF  
12°REF  
12°REF  
12°REF  
OZ965-SF-3.0  
Page 6  
OZ965  
DIM  
INCHES  
MIN MAX  
0.0532 0.0688  
0.0040 0.0098  
MILLIMETERS  
MIN  
1.35  
0.10  
0.33  
0.19  
9.80  
3.80  
MAX  
1.75  
0.25  
0.51  
0.25  
10.00  
4.00  
A
A1  
B
C
D
E
0.013  
0.020  
SOP-16  
PACKAGE  
0.0075 0.0098  
0.3859 0.3937  
0.1497 0.1574  
0.050 BCS.  
E H  
e
1.27 BCS.  
H
0.2284  
0.244  
0
5.80  
6.20  
L
α
0.016  
0°  
0.050  
8°  
0.40  
0°  
1.27  
8°  
D
C
D
A
L
B
e
A1  
OZ965-SF-3.0  
Page 7  
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