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CYW312OXC

型号：

CYW312OXC

描述：

FTG的VIA ™ K7系列芯片组具有可编程输出频率[ FTG for VIA⑩ K7 Series Chipset with Programmable Output Frequency ]

品牌：

CYPRESS[ CYPRESS ]

页数：

20 页

PDF大小：

254 K

下载PDF手册
W312-02  
FTG for VIA™ K7 Series Chipset with  
Programmable Output Frequency  
• Low jitter and tightly controlled clock skew  
• Two pairs of differential CPU clocks  
Features  
• Single chip FTG solution for VIA™ K7 Series chipsets  
• Programmable clock output frequency with less than  
• Eleven copies of PCI clocks  
• Three copies of 66-MHz outputs  
1 MHz increment  
• Two copies of 48-MHz outputs  
• Integrated fail-safe Watchdog timer for system  
recovery  
• Automatically switch to HW selected or SW  
programmed clock frequency when watchdog timer  
time-out  
• Three copies of 14.31818-MHz reference clocks  
• One RESET output for system recovery  
• Power management control support  
• Capable of generate system RESET after a watchdog  
timer time-out occurs or a change in output frequency  
via SMBus interface  
Key Specifications  
CPU Outputs Cycle-to-cycle Jitter: .............................250 ps  
• Support SMBus byte read/write and block read/ write  
48-MHz, 3V66, PCI Outputs  
operations to simplify system BIOS development  
Cycle-to-cycle Jitter:....................................................500 ps  
• Vendor ID and Revision ID support  
• Programmable drive strength for PCI output clocks  
• ProgrammableoutputskewbetweenCPU,AGPandPCI  
CPU, 3V66 Output Skew:............................................200 ps  
48-MHz Output Skew: .................................................250 ps  
PCI Output Skew:........................................................500 ps  
• Maximized EMI suppression using Cypress’s Spread  
Spectrum technology  
Block Diagram  
Pin Configuration[1]  
VDD_REF  
REF2  
VDD_REF  
GND_REF  
X1  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
REF0/FS0*  
REF1/FS1*  
REF2  
1
2
X1  
X2  
3
XTAL  
OSC  
REF1/FS1*  
REF0/FS0*  
X2  
REF_STOP#*  
AGP_STOP#*  
GND_CPU  
CPUT0  
4
VDD_48MHz  
*FS2/48MHz  
*FS3/24_48MHz  
GND_48MHz  
*FS4/PCI_F  
*SEL24_48#/PCI0  
PCI1  
5
PLL REF FREQ  
VDD_CPU  
6
7
CPUT0,CPUC0  
CPUT_CS,CPUC_CS  
VDD_AGP  
Divider,  
Delay,  
and  
8
CPUC0  
2
SDATA  
SCLK  
SMBus  
Logic  
VDD_CPU  
CPUT_CS  
CPUC_CS  
GND_CPU  
CPU_STOP#*  
PCI_STOP#*  
PD#*  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Phase  
Control  
Logic  
AGP0:2  
GND_PCI  
PCI2  
3
(FS0:4)  
PCI3  
VDD_PCI  
PCI4  
VDD_PCI  
VDD_CORE  
GND_CORE  
SDATA  
PCI0/SEL24_48#*  
PCI5  
PLL 1  
PCI1:8  
PCI6  
5
GND_PCI  
PCI7  
SCLK  
PD#  
CPU_STOP#  
PCI_STOP#  
AGP_STOP#  
REF_STOP#  
GND_AGP  
AGP2  
PCI9_E  
PCI8  
PCI9_E  
AGP1  
VDD_PCI  
RST#  
AGP0  
RST#  
VDD_AGP  
VDD_48MHz  
48MHz/FS3*  
Note:  
1. Internal 100K pull-up resistors present on inputs marked with *. De-  
sign should not rely solely on internal pull-up resistor to set I/O pins  
HIGH.  
PLL2  
24_48MHz/FS4*  
/2  
SEL24_48#*  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-07259 Rev. *C  
Revised April 28, 2005  
W312-02  
I
Pin Definitions  
Pin  
Pin Name  
Pin No.  
Type  
Pin Description  
REF0/FS0  
48  
I/O  
Reference Clock Output 0/Frequency Select 0: 3.3V 14.318-MHz clock  
output. REF0 will be disabled when REF_STOP# is active. This pin also serves  
as the select strap to determines device operating frequency as described in  
Table 5.  
REF1/FS1  
47  
I/O  
Reference Clock Output 0/Frequency Select 1: 3.3V 14.318-MHz clock  
output. REF1 will be disabled when REF_STOP# is active. This pin also serves  
as the select strap to determines device operating frequency as described in  
Table 5.  
REF2  
X1  
46  
3
I/O  
Reference Clock Output 2: 3.3V 14.318-MHz clock output. REF2 will be  
disabled when REF_STOP# is active.  
I
I
I
Crystal Input: This pin has dual functions. It can be used as an external 14.318-  
MHz crystal connection or as an external reference frequency input.  
X2  
4
Crystal Output: An input connection for an external 14.318-MHz crystal  
connection. If using an external reference, this pin must be left unconnected.  
PCI_F/FS4  
9
Free-Running PCI Clock/Frequency Select 4: 3.3V 33-MHz free running PCI  
clock output. This pin also serves as the select strap to determines device  
operating frequency as described in Table 5.  
PCI_0/SEL24_48#  
10  
I/O  
PCI Clock 0/Select 24 or 48 MHz: 3.3V 33-MHz PCI clock outputs. This output  
will be disabled when PCI_STOP# is active. This pin also serves as the select  
strap to determine device operating frequency of 24_48MHz output.  
PCI1:8  
PCI9_E  
AGP0:2  
11, 13, 14, 16,  
17, 18, 20, 21  
O
O
O
PCI Clock 1 through 8: 3.3V 33-MHz PCI clock outputs. PCI1:8 will be disabled  
when PCI_STOP# is active.  
22  
Early PCI Clock 9: 3.3V 33-MHz PCI clock outputs. PCI9_E will be disabled  
when PCI_STOP# is active.  
26, 27, 28  
AGP Clock 0 through 2: 3.3V 66-MHz clock outputs. The operating frequency  
is controlled by FS0:4 (see Table 5). AGP0:2 will be disabled when  
AGP_STOP# is active.  
48MHz/FS2  
6
7
I/O  
I/O  
48-MHz Output/Frequency Selection 3: 3.3V 48-MHz non-spread spectrum  
output. 48MHz will be disabled when REF_STOP# is active. This pin also serves  
as the select strap to determine device operating frequency as described in  
Table 5.  
24 or 48-MHz Output/Select 24 or 48 MHz: 3.3V 24 or 48-MHz non-spread  
spectrum output. 24_48MHz will be disabled when REF_STOP# is active. This  
pin also serves as the select strap to determine device operating frequency as  
described in Table 5.  
24_48MHz/FS3  
RST#  
24  
O
Reset#: Open-drain RESET# output.  
(open-  
drain)  
CPUT0, CPUC0  
42, 41  
39, 38  
36  
O
CPU Clock Output 0: CPUT0 and CPUC0 are the differential CPU clock  
(open- outputs for the K7 processor. They are open-drain outputs.  
drain)  
CPUT_CS,  
CPUC_CS  
O
CPU Clock Output for Chipset: CPUT_CS and CPUC_CS are the differential  
CPU clock outputs for the chipset. They are push-pull outputs. These outputs  
will be disabled when CPU_STOP# is active.  
CPU_STOP#  
I
CPU STOP Input: This input will disable CPUT_CS and CPUC_CS when it is  
active.  
PCI_STOP#  
AGP_STOP#  
REF_STOP#  
35  
44  
45  
I
I
I
PCI STOP Input: This input will disable PCI0:8 and PCI9_E when it is active.  
AGP STOP Input: This input will disable AGP0:2 when it is active.  
REF STOP Input: This input will disable REF0:2, 24_48MHz and 48 MHz  
outputs when it is active.  
Document #: 38-07259 Rev. *C  
Page 2 of 20  
W312-02  
Pin Definitions (continued)  
Pin  
Pin Name  
Pin No.  
Type  
Pin Description  
PD#  
34  
I
Power-Down Input: This input will trigger the clock generator into Power Down  
mode when it is active.  
SDATA  
SCLK  
VDD_CPU  
31  
30  
40  
I/O  
I
P
Data pin for SMBus circuitry.  
Clock pin for SMBus circuitry.  
2.5V Power Connection: Power supply for CPU output buffers. Connect to  
2.5V.  
VDDQ_AGP  
25  
P
3.3V Power Connection: Power supply for AGP output buffers. Connect to  
3.3V.  
VDDQ_PCI  
VDDQ_48MHz  
15, 23  
5
P
P
3.3V Power Connection: Power supply for PCI output buffers. Connect to 3.3V.  
3.3V Power Connection: Power supply for 48 MHz output buffers. Connect to  
3.3V.  
VDD_REF  
VDD_Core  
1
P
3.3V Power Connection: Power supply for reference output buffers. Connect  
to 3.3V.  
33  
P
3.3V Power Connection: Power supply for PLL core. Connect to 3.3V.  
GND_REF,  
GND_48MHz,  
GND_PCI,  
GND_AGP,  
GND_Core,  
GND_CPU  
2, 8, 29, 32, 37,  
43  
G
Ground Connections: Connect all ground pins to the common system ground  
plane.  
Document #: 38-07259 Rev. *C  
Page 3 of 20  
W312-02  
Serial Data Interface  
The W312-02 features a two-pin, serial data interface that can  
be used to configure internal register settings that control  
particular device functions.  
accessed in sequential order from lowest to highest byte with  
the ability to stop after any complete byte has been trans-  
ferred. For byte/word write and byte read operations, system  
controller can access individual indexed byte. The offset of the  
indexed byte is encoded in the command code.  
.The block write and block read protocol is outlined in Table 1  
while Table 2 outlines the corresponding byte write and byte  
read protocol. The slave receiver address is 11010010 (D2h)  
Data Protocol  
The clock driver serial protocol supports byte/word write,  
byte/word read, block write and block read operations from the  
controller. For block write/read operation, the bytes must be  
Table 1. Command Code Definitions  
Bit  
Descriptions  
7
0 = Block read or block write operation  
1 = Byte/Word read or byte/word write operation  
6:0  
Byte offset for byte/word read or write operation. For block read or write operations, these bits  
need to be set at ‘0000000’.  
Table 2. Block Read and Block Write Protocol  
Block Write Protocol  
Block Read Protocol  
Description  
Bit  
1
Description  
Bit  
1
Start  
Start  
2:8  
9
Slave address – 7 bits  
Write  
2:8  
9
Slave address – 7 bits  
Write  
10  
Acknowledge from slave  
10  
Acknowledge from slave  
11:18  
Command Code – 8 bits  
11:18  
Command Code – 8 bits  
‘00000000’ stands for block operation  
‘00000000’ stands for block operation  
19  
20:27  
28  
29:36  
37  
38:45  
46  
...  
Acknowledge from slave  
Byte Count – 8 bits  
Acknowledge from slave  
Data byte 0 – 8 bits  
Acknowledge from slave  
Data byte 1 – 8 bits  
Acknowledge from slave  
Data Byte N/Slave Acknowledge...  
Data Byte N – 8 bits  
Acknowledge from slave  
Stop  
19  
20  
21:27  
28  
29  
30:37  
38  
39:46  
47  
48:55  
56  
Acknowledge from slave  
Repeat start  
Slave address – 7 bits  
Read  
Acknowledge from slave  
Byte count from slave – 8 bits  
Acknowledge  
Data byte from slave – 8 bits  
Acknowledge  
...  
...  
...  
Data byte from slave – 8 bits  
Acknowledge  
...  
...  
...  
Data bytes from slave/Acknowledge  
Data byte N from slave – 8 bits  
Not Acknowledge  
...  
Stop  
Document #: 38-07259 Rev. *C  
Page 4 of 20  
W312-02  
Table 3. Word Read and Word Write Protocol  
Word Write Protocol  
Word Read Protocol  
Description  
Bit  
1
Description  
Bit  
1
Start  
Start  
2:8  
9
Slave address – 7 bits (D2)  
Write  
2:8  
9
Slave address – 7 bits (D3)  
Write  
10  
11:18  
Acknowledge from slave  
10  
11:18  
Acknowledge from slave  
Command Code – 8 bits  
Command Code – 8 bits  
‘1xxxxxxx’ stands for byte or word operation  
bit[6:0] of the command code represents the  
offset of the byte to be accessed  
‘1xxxxxxx’ stands for byte or word operation  
bit[6:0] of the command code represents the  
offset of the byte to be accessed  
19  
20:27  
28  
29:36  
37  
Acknowledge from slave  
Data byte low – 8 bits  
Acknowledge from slave  
Data byte high – 8 bits  
Acknowledge from slave  
Stop  
19  
20  
21:27  
28  
29  
30:37  
38  
Acknowledge from slave  
Repeat start  
Slave address – 7 bits  
Read  
Acknowledge from slave  
Data byte low from slave – 8 bits  
Acknowledge  
38  
39:46  
47  
48  
Data byte high from slave – 8 bits  
NOT acknowledge  
Stop  
Table 4. Byte Read and Byte Write Protocol  
Byte Write Protocol  
Byte Read Protocol  
Description  
Bit  
1
Description  
Bit  
1
Start  
Start  
2:8  
9
Slave address – 7 bits  
Write  
2:8  
9
Slave address – 7 bits  
Write  
10  
Acknowledge from slave  
10  
Acknowledge from slave  
11:18  
Command Code – 8 bits  
11:18  
Command Code – 8 bits  
‘1xxxxxxx’ stands for byte operation  
bit[6:0] of the command code represents the  
offset of the byte to be accessed  
‘1xxxxxxx’ stands for byte operation  
bit[6:0] of the command code represents the  
offset of the byte to be accessed  
19  
20:27  
28  
Acknowledge from slave  
Data byte – 8 bits  
Acknowledge from slave  
Stop  
19  
20  
21:27  
28  
Acknowledge from slave  
Repeat start  
Slave address – 7 bits  
Read  
29  
29  
30:37  
38  
Acknowledge from slave  
Data byte from slave – 8 bits  
Not Acknowledge  
Stop  
39  
Document #: 38-07259 Rev. *C  
Page 5 of 20  
W312-02  
2. All unused register bits (reserved and N/A) should be  
W312-02 Serial Configuration Map  
written to a “0” level.  
1. The serial bits will be read by the clock driver in the following  
3. All register bits labeled “Initialize to 0" must be written to  
order:  
zero during initialization.  
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0  
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0  
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0  
Byte 0: Control Register 0  
Bit  
Pin#  
Name  
Default  
Description  
Bit 7  
–
Spread Enable  
0
0 = Disabled  
1 = Enabled  
Bit 6  
Bit 5  
Bit 4  
–
–
–
Spread Select2  
Spread Select1  
Spread Select0  
0
0
0
‘000’ = ±0.25%  
‘001’ = –0.5%  
‘010’ = ±0.5%  
‘011’ = ±0.38%  
‘100’ = Reserved  
‘101’ = Reserved  
‘110’ = Reserved  
‘111’ = Reserved  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
–
–
–
–
SEL3  
SEL2  
SEL1  
SEL0  
0
0
0
0
SW Frequency selection bits. See Table 5.  
Byte 1: Control Register 1  
Bit  
Pin#  
Name  
CPUT0, CPUC0  
CPUT_CS,  
CPUC_CS  
Default  
Description  
(Active/Inactive)  
(Active/Inactive)  
Bit 7  
Bit 6  
42, 41  
39, 38  
1
1
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
6
7
–
28  
27  
26  
48MHz  
24_48MHz  
Reserved  
AGP2  
AGP1  
AGP0  
1
1
0
1
1
1
(Active/Inactive)  
(Active/Inactive)  
Reserved  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
Byte 2: Control Register 2  
Bit Pin#  
Name  
PCI7  
PCI6  
PCI5  
PCI4  
PCI3  
PCI2  
PCI1  
PCI0  
Default  
Description  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
20  
18  
17  
16  
14  
13  
11  
10  
1
1
1
1
1
1
1
1
Document #: 38-07259 Rev. *C  
Page 6 of 20  
W312-02  
\
Byte 3: Control Register  
Bit  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Pin#  
9
22  
–
21  
46  
–
47  
48  
Name  
PCI_F  
PCI9_E  
Reserved  
PCI8  
REF2  
Reserved  
REF1  
Default  
Description  
1
1
0
1
1
0
1
1
(Active/Inactive)  
(Active/Inactive)  
Reserved  
(Active/Inactive)  
(Active/Inactive)  
Reserved  
(Active/Inactive)  
(Active/Inactive)  
REF0  
Byte 4: Watchdog Timer Register  
Bit  
Pin#  
–
–
Name  
Reserved  
FS_Override  
Default  
Description  
Bit 7  
Bit 6  
0
0
Reserved  
0 = Select operating frequency by FS[4:0] input pins  
1 = Select operating frequency by SEL[4:0] settings  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
–
–
–
–
–
WD_TIMER4  
WD_TIMER3  
WD_TIMER2  
WD_TIMER1  
WD_TIMER0  
1
1
1
1
1
These bits store the time-out value of the Watchdog  
timer. The scale of the timer is determine by the  
prescaler.  
The timer can support a value of 150 ms to 4.8 sec  
when the prescaler is set to 150 ms. If the prescaler is  
set to 2.5 sec, it can support a value from 2.5 sec to 80  
sec.  
When the Watchdog timer reaches “0”, it will set the  
WD_TO_STATUS bit.  
Bit 0  
–
WD_PRE_SCAL  
ER  
0
0 = 150 ms  
1 = 2.5 sec  
Byte 5: Control Register 5  
Bit  
Pin#  
9
7
Name  
Latched FS4 input  
Default  
Description  
Latched FS[4:0] inputs. These bits are read only.  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
X
X
X
X
X
0
Latched FS3 input  
Latched FS2 input  
Latched FS1 input  
Latched FS0 input  
Reserved  
6
47  
48  
–
Reserved  
–
–
Reserved  
SEL4  
0
0
Reserved  
SW Frequency selection bits. See Table 5.  
Document #: 38-07259 Rev. *C  
Page 7 of 20  
W312-02  
Byte 6: Reserved Register  
Bit  
Name  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Default  
Pin Description  
Pin Description  
Pin Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
1
1
1
1
1
1
1
1
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Byte 7: Reserved Register  
Bit Name  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
1
1
1
1
1
1
1
1
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Byte 8: Vendor ID and Revision ID Register (Read Only)  
Bit  
Name  
Revision_ID3  
Revision_ID2  
Revision_ID1  
Revision_ID0  
Vendor_ID3  
Vendor_ID2  
Vendor _ID1  
Vendor _ID0  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
1
0
0
0
Revision ID bit[3]  
Revision ID bit[2]  
Revision ID bit[1]  
Revision ID bit[0]  
Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only.  
Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only.  
Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only.  
Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only.  
Document #: 38-07259 Rev. *C  
Page 8 of 20  
W312-02  
Byte 9: System Reset and Watchdog Timer Register  
Bit  
Name  
Reserved  
PCI_DRV  
Default  
Pin Description  
Bit 7  
Bit 6  
0
0
Reserved  
PCI clock output drive strength  
0 = Normal  
1 = High Drive  
Bit 5  
Bit 4  
Reserved  
RST_EN_WD  
0
0
Reserved  
This bit will enable the generation of a Reset pulse when a watchdog timer time-  
out occurs.  
0 = Disabled  
1 = Enabled  
Bit 3  
RST_EN_FC  
0
This bit will enable the generation of a Reset pulse after a frequency change  
occurs.  
0 = Disabled  
1 = Enabled  
Bit 2  
Bit 1  
Bit 0  
WD_TO_STATUS  
WD_EN  
0
0
0
Watchdog Timer Time-out Status bit  
0 = No time-out occurs (READ); Ignore (WRITE)  
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)  
0 = Stop and re-load Watchdog timer  
1 = Enable Watchdog timer. It will start counting down after a frequency change  
occurs.  
Reserved  
Reserved  
Byte 10: Skew Control Register  
Bit  
Name  
CPU_Skew2  
CPU_Skew1  
CPU_Skew0  
Default  
Description  
Bit 7  
Bit 6  
Bit 5  
0
0
0
CPU skew control  
000 = Normal  
001 = –150 ps  
010 = –300 ps  
011 = –450 ps  
100 = +150 ps  
101 = +300 ps  
110 = +450 ps  
111 = +600 ps  
Bit 4  
Bit 3  
Bit 2  
Reserved  
PCI_Skew1  
PCI_Skew0  
0
0
0
Reserved  
PCI skew control  
00 = Normal  
01 = –500 ps  
10 = Reserved  
11 = +500 ps  
Bit 1  
Bit 0  
AGP_Skew1  
AGP_Skew0  
0
0
AGP skew control  
00 = Normal  
01 = –150 ps  
10 = +150 ps  
11 = +300 ps  
Document #: 38-07259 Rev. *C  
Page 9 of 20  
W312-02  
Byte 11: Recovery Frequency N - Value Register  
Bit  
Name  
Default  
Pin Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
ROCV_FREQ_N7  
ROCV_FREQ_N6  
ROCV_FREQ_N5  
ROCV_FREQ_N4  
ROCV_FREQ_N3  
ROCV_FREQ_N2  
ROCV_FREQ_N1  
ROCV_FREQ_N0  
0
0
0
0
0
0
0
0
If ROCV_FREQ_SEL is set, W312-02 will use the values programmed in  
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery  
CPU output frequency.when a Watchdog timer time-out occurs.  
The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM,  
AGP and SDRAM. When it is cleared, W312-02 will use the same frequency  
ratio stated in the Latched FS[4:0] register. When it is set,  
W312-02 will use the frequency ratio stated in the SEL[4:0] register.  
W312-02 supports programmable CPU frequency ranging from 50 MHz to 248  
MHz.  
W312-02 will change the output frequency whenever there is an update to either  
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended  
to use Word or Block write to update both registers within the same SMBus bus  
operation.  
Byte 12: Recovery Frequency M- Value Register  
Bit  
Name  
Default  
Pin Description  
Bit 7  
ROCV_FREQ_SEL  
0
ROCV_FREQ_SEL determines the source of the recover frequency when a  
Watchdog timer time-out occurs. The clock generator will automatically switch  
to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL.  
0 = From latched FS[4:0]  
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
ROCV_FREQ_M6  
ROCV_FREQ_M5  
ROCV_FREQ_M4  
ROCV_FREQ_M3  
ROCV_FREQ_M2  
ROCV_FREQ_M1  
ROCV_FREQ_M0  
0
0
0
0
0
0
0
If ROCV_FREQ_SEL is set, W312-02 will use the values programmed in  
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery  
CPU output frequency.when a Watchdog timer time-out occurs  
The setting of FS_Override bit determines the frequency ratio for CPU,  
SDRAM, AGP and SDRAM. When it is cleared, W312-02 will use the same  
frequency ratio stated in the Latched FS[4:0] register. When it is set, W312-02  
will use the frequency ratio stated in the SEL[4:0] register.  
W312-02 supports programmable CPU frequency ranging from 50 MHz to 248  
MHz.  
W312-02 will change the output frequency whenever there is an update to  
either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recom-  
mended to use Word or Block write to update both registers within the same  
SMBus bus operation.  
Byte 13: Programmable Frequency Select N-Value Register  
Bit  
Name  
Default  
Pin Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
CPU_FSEL_N7  
CPU_FSEL_N6  
CPU_FSEL_N5  
CPU_FSEL_N4  
CPU_FSEL_N3  
CPU_FSEL_N2  
CPU_FSEL_N1  
CPU_FSEL_N0  
0
0
0
0
0
0
0
0
If Prog_Freq_EN is set, W300 will use the values programmed in  
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output  
frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is  
updated.  
The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM,  
AGP and SDRAM. When it is cleared, W312 will use the same frequency ratio  
stated in the Latched FS[4:0] register. When it is set, W312-02 will use the  
frequency ratio stated in the SEL[4:0] register.  
W312-02 supports programmable CPU frequency ranging from 50 MHz to 248  
MHz.  
Document #: 38-07259 Rev. *C  
Page 10 of 20  
W312-02  
Byte 14: Programmable Frequency Select N-Value Register  
Bit  
Name  
Default  
Description  
Bit 7  
Pro_Freq_EN  
0
Programmable output frequencies enabled  
0 = disabled  
1 = enabled  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
CPU_FSEL_M6  
CPU_FSEL_M5  
CPU_FSEL_M4  
CPU_FSEL_M3  
CPU_FSEL_M2  
CPU_FSEL_M1  
CPU_FSEL_M0  
0
0
0
0
0
0
0
If Prog_Freq_EN is set, W300 will use the values programmed in  
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output  
frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is  
updated.  
The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM,  
AGP and SDRAM. When it is cleared, W312-02 will use the same frequency  
ratio stated in the Latched FS[4:0] register. When it is set, W312-02 will use the  
frequency ratio stated in the SEL[4:0] register.  
W312-02 supports programmable CPU frequency ranging from 50 MHz to 248  
MHz.  
Byte 15: Reserved Register  
Bit Pin#  
Name  
Reserved  
Default  
Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
–
–
–
–
–
–
–
–
0
0
0
0
0
0
1
1
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved. Write with ‘1’  
Reserved. Write with ‘1’  
Byte 16: Reserved Register  
Bit  
Pin#  
Name  
Default  
Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
–
–
–
–
–
–
–
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Byte 17: Reserved Register  
Bit Pin#  
Name  
Default  
Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
–
–
–
–
–
–
–
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Document #: 38-07259 Rev. *C  
Page 11 of 20  
W312-02  
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes  
Input Conditions  
Output Frequency  
PLL Gear  
Constants  
(G)  
FS4  
SEL4  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS3  
SEL3  
0
FS2  
SEL2  
0
FS1  
SEL1  
0
FS0  
SEL0  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CPU  
156.0  
154.0  
152.0  
147.0  
144.0  
142.0  
138.0  
136.0  
124.0  
122.0  
117.0  
115.0  
113.0  
108.0  
105.0  
102.0  
Reserved  
Reserved  
Reserved  
200.0  
190.0  
180.0  
170.0  
150.0  
140.0  
120.0  
110.0  
66.6  
3V66  
78.0  
77.0  
76.0  
73.5  
72.0  
71.0  
69.0  
68.0  
62.0  
61.0  
78.0  
76.7  
75.3  
72.0  
70.0  
68.0  
PCI  
39.0  
38.5  
38.0  
36.8  
36.0  
35.5  
34.5  
34.0  
31.0  
30.5  
39.0  
38.3  
37.7  
36.0  
35.0  
34.0  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
Reserved  
Reserved  
Reserved  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Reserved  
Reserved  
Reserved  
66.6  
Reserved  
Reserved  
Reserved  
33.3  
76.0  
72.0  
68.0  
75.0  
70.0  
60.0  
73.3  
66.6  
66.6  
66.6  
66.6  
66.6  
38.0  
36.0  
34.0  
37.5  
35.0  
30.0  
33.3  
33.3  
33.3  
33.3  
33.3  
33.3  
200.0  
166.6  
100.0  
133.3  
1
1
Programmable Output Frequency, Watchdog Timer and  
Recovery Output Frequency Functional Description  
The Programmable Output Frequency feature allows users to  
generate any CPU output frequency from the range of 50 MHz  
to 248 MHz. Cypress offers the most dynamic and the simplest  
programming interface for system developers to utilize this  
feature in their platforms.  
The Watchdog Timer and Recovery Output Frequency  
features allow users to implement a recovery mechanism  
when the system hangs or getting unstable. System BIOS or  
other control software can enable the Watchdog timer before  
they attempt to make a frequency change. If the system hangs  
and a Watchdog timer time-out occurs, a system reset will be  
generated and a recovery frequency will be activated.  
All of the related registers are summarized inTable 7.  
Document #: 38-07259 Rev. *C  
Page 12 of 20  
W312-02  
Table 6. Register Summary  
Name  
Description  
Pro_Freq_EN  
Programmable output frequencies enabled  
0 = Disabled (default)  
1 = Enabled  
When it is disabled, the operating output frequency will be determined by either the latched value of  
FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs  
will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used.  
When it is enabled, the CPU output frequency will be determined by the programmed value of  
CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0]  
or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between  
CPU and other frequency outputs  
FS_Override  
When Pro_Freq_EN is cleared or disabled,  
0 = Select operating frequency by FS input pins (default)  
1 = Select operating frequency by SEL bits in SMBus control bytes  
When Pro_Freq_EN is set or enabled,  
0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are  
based on the latched value of FS input pins (default)  
1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are  
based on the programmed value of SEL bits in SMBus control bytes  
CPU_FSEL_N,  
CPU_FSEL_M  
When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and  
CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load  
whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recom-  
mended to use Word or Block write to update both registers within the same SMBus bus operation.  
The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When  
FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins.  
When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in  
SMBus control bytes.  
ROCV_FREQ_SEL  
ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out  
occurs. The clock generator will automatically switch to the recovery CPU frequency based on the  
selection on ROCV_FREQ_SEL.  
0 = From latched FS[4:0]  
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]  
ROCV_FREQ_N[7:0], When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and  
ROCV_FREQ_M[6:0] ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a  
Watchdog timer time-out occurs  
The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. Whenit is cleared,  
the same frequency ratio stated in the Latched FS[4:0] register will be used.  
When it is set, the frequency ratio stated in the SEL[4:0] register will be used.  
The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and  
ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers  
within the same SMBus bus operation.  
WD_EN  
0 = Stop and reload Watchdog timer  
1 = Enable Watchdog timer. It will start counting down after a frequency change occurs.  
WD_TO_STATUS  
Watchdog Timer Time-out Status bit  
0 = No time-out occurs (READ); Ignore (WRITE)  
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)  
WD_TIMER[4:0]  
These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the  
prescaler.  
The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If the pre-  
scaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec.  
When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit.  
WD_PRE_SCALER  
0 = 150 ms  
1 = 2.5 sec  
Document #: 38-07259 Rev. *C  
Page 13 of 20  
W312-02  
Table 6. Register Summary (continued)  
Name  
Description  
RST_EN_WD  
This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs.  
0 = Disabled  
1 = Enabled  
RST_EN_FC  
This bit will enable the generation of a Reset pulse after a frequency change occurs.  
0 = Disabled  
1 = Enabled  
How to Program CPU Output Frequency  
When the programmable output frequency feature is enabled  
(Pro_Freq_EN bit is set), the CPU output frequency is deter-  
mined by the following equation:  
“G” stands for the PLL Gear Constant, which is determined by  
the programmed value of FS[4:0] or SEL[4:0]. The value is  
listed in Table 5. The ratio of (N+3) and (M+3) need to be  
greater than “1” [(N+3)/(M+3) > 1].  
Table 7 lists set of N and M values for different frequency  
output ranges.This example use a fixed value for the M-Value  
Register and select the CPU output frequency by changing the  
value of the N-Value Register.  
Fcpu = G * (N+3)/(M+3)  
“N” and “M” are the values programmed in Programmable  
Frequency Select N-Value Register and M-Value Register,  
respectively.  
Table 7. Examples of N and M Value for Different CPU Frequency Range  
Fixed Value for  
Range of N-Value Register  
for Different CPU Frequency  
Frequency Ranges  
50 MHz–129 MHz  
130 MHz–248 MHz  
Gear Constants  
48.00741  
M-Value Register  
93  
48  
97–255  
127–245  
48.00741  
Document #: 38-07259 Rev. *C  
Page 14 of 20  
W312-02  
Absolute Maximum Ratings[2]  
Stresses greater than those listed in this table may cause  
permanent damage to the device. These represent a stress  
tions above those specified in the operating sections of this  
specification is not implied. Maximum conditions for extended  
periods may affect reliability.  
rating only. Operation of the device at these or any other condi-  
.
Parameter  
DD, VIN  
TSTG  
TB  
TA  
ESDPROT  
Description  
Voltage on any pin with respect to GND  
Storage Temperature  
Ambient Temperature under Bias  
Operating Temperature  
Rating  
–0.5 to +7.0  
–65 to +150  
–55 to +125  
0 to +70  
Unit  
V
°C  
°C  
°C  
kV  
V
Input ESD Protection  
2 (min.)  
DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% and 2.5V±5%  
Parameter  
Description  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
Supply Current  
IDD  
IDD  
Logic Inputs  
3.3V Supply Current  
CPU =100 MHz  
260  
25  
mA  
mA  
Outputs Loaded[3]  
2.5V Supply Current  
CPUCS =100 MHz  
Outputs Loaded[3]  
VIL  
VIH  
IIL  
Input Low Voltage  
Input High Voltage  
Input Low Current[4]  
Input High Current[4]  
GND – 0.3  
2.0  
0.8  
VDD + 0.3  
–25  
V
V
µA  
µA  
IIH  
10  
Clock Outputs  
VOL  
VOH  
VOL  
Output Low Voltage  
Output High Voltage  
Output Low Voltage CPUT_CS,  
CPUC_CS,  
IOL = 1 mA  
IOH = –1 mA  
Termination to V pull-up  
(external)  
50  
mV  
V
V
3.1  
0
0.3  
CPUT0, CPUC0  
VOH  
Output High Voltage CPUT_CS,  
CPUC_CS,  
Termination to V pull-up  
(external)  
1.0  
1.2  
V
CPUT0, CPUC0  
IOL  
Output Low Current PCI, AGP  
VOL = 1.5V  
VOL = 1.5V  
VOL = 1.5V  
VOL = 1.5V  
VOH = 1.5V  
VOH = 1.5V  
VOH = 1.5V  
VOH = 1.5V  
70  
50  
50  
50  
70  
50  
50  
50  
110  
70  
70  
70  
110  
70  
135  
100  
100  
100  
135  
100  
100  
100  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
REF  
48 MHz  
24_48 MHz  
IOH  
Output High Current PCI, AGP  
REF  
48 MHz  
24_48 MHz  
70  
70  
Notes:  
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.  
3. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors.  
4. X1 input threshold voltage (typical) is V /2.  
DD  
Document #: 38-07259 Rev. *C  
Page 15 of 20  
W312-02  
DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% and 2.5V±5% (continued)  
Parameter  
Description  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
Crystal Oscillator  
VTH  
CLOAD  
X1 Input Threshold Voltage[4]  
VDD = 3.3V  
1.65  
18  
V
pF  
Load Capacitance, Imposed on  
External Crystal[5]  
CIN,X1  
X1 Input Capacitance[6]  
Pin X2 unconnected  
Except X1 and X2  
TBD  
pF  
Pin Capacitance/Inductance  
CIN Input Pin Capacitance  
COUT  
LIN  
5
6
7
pF  
pF  
nH  
Output Pin Capacitance  
Input Pin Inductance  
AC Electrical Characteristics  
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, fXTL = 14.31818 MHz  
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the  
clock output; Spread Spectrum is disabled.  
CPU Clock Outputs (CPUT0, CPUC0, CPU_CS)[7]  
CPU = 100 MHz  
CPU = 133 MHz  
Parameter  
tR  
tF  
tD  
tJC  
fST  
Description  
Output Rise Edge Rate CPU_CS  
Output Fall Edge Rate CPU_CS  
Duty Cycle  
Jitter, Cycle to Cycle  
Test Condition/Comments  
Min. Typ. Max. Min. Typ. Max. Unit  
1.0  
1.0  
45  
4.0  
4.0  
55  
1.0  
1.0  
45  
4.0 V/ns  
4.0 V/ns  
Measured at 50% point  
55  
%
ps  
250  
250  
Frequency Stabilization Assumes full supply voltage reached  
3
3
ms  
from Power-up (cold  
start)  
within 1 ms from power-up. Short  
cycles exist prior to frequency  
stabilization.  
Zo  
AC Output Impedance VO = VX  
50  
50  
Ω
Notes:  
5. The W312-02 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is  
18 pF; this includes typical stray capacitance of short PCB traces to crystal.  
6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).  
7. Refer to Figure 1 for K7 operation clock driver test circuit.  
Document #: 38-07259 Rev. *C  
Page 16 of 20  
W312-02  
PCI Clock Outputs (Lump Capacitance Test Load = 30 pF)  
Parameter Description Test Condition/Comments  
tP Measured on rising edge at 1.5V  
Min.  
30  
12  
12  
1
Typ.  
Max.  
Unit  
ns  
ns  
Period  
tH  
tL  
tR  
tF  
tD  
tJC  
High Time  
Low Time  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
Duration of clock cycle above 2.4V  
Duration of clock cycle below 0.4V  
Measured from 0.4V to 2.4V  
Measured from 2.4V to 0.4V  
Measured on rising and falling edge at 1.5V  
ns  
4
4
55  
250  
V/ns  
V/ns  
%
1
45  
Jitter, Cycle-to-Cycle  
Measured on rising edge at 1.5V. Maximum  
ps  
difference of cycle time between two adjacent cycles.  
tSK  
tO  
Output Skew  
Measured on rising edge at 1.5V  
500  
4
ps  
ns  
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge  
at 1.5V. CPU leads PCI output.  
1.5  
fST  
Frequency Stabilization  
Assumes full supply voltage reached within 1 ms from  
3
ms  
from Power-up (cold start) power-up. Short cycles exist prior to frequency stabi-  
lization.  
Zo  
AC Output Impedance  
Average value during switching transition. Used for  
determining series termination value.  
30  
Ω
REF Clock Outputs (Lump Capacitance Test Load = 20 pF)  
Parameter  
Description  
Frequency, Actual  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
Test Condition/Comments  
Frequency generated by crystal oscillator  
Measured from 0.4V to 2.4V  
Measured from 2.4V to 0.4V  
Measured on rising and falling edge at 1.5V  
Min.  
Typ.  
14.318  
Max. Unit  
f
MHz  
tR  
tF  
tD  
fST  
0.5  
0.5  
45  
2
2
55  
3
V/ns  
V/ns  
%
Frequency Stabilization from Assumes full supply voltage reached within 1 ms  
ms  
Power-up (cold start)  
from power-up. Short cycles exist prior to  
frequency stabilization.  
Zo  
AC Output Impedance  
Average value during switching transition. Used  
for determining series termination value.  
40  
Ω
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)  
Parameter  
Description  
Frequency, Actual  
Deviation from 48 MHz  
PLL Ratio  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
Test Condition/Comments  
Determined by PLL divider ratio (see m/n below)  
(48.008 – 48)/48  
(14.31818 MHz x 57/17 = 48.008 MHz)  
Measured from 0.4V to 2.4V  
Measured from 2.4V to 0.4V  
Measured on rising and falling edge at 1.5V  
Assumes full supply voltage reached within 1 ms  
Min.  
Typ.  
48.008  
+167  
Max. Unit  
MHz  
f
fD  
m/n  
tR  
tF  
tD  
ppm  
57/17  
0.5  
0.5  
45  
2
2
55  
3
V/ns  
V/ns  
%
fST  
Frequency Stabilization  
ms  
from Power-up (cold start) from power-up. Short cycles exist prior to  
frequency stabilization.  
Zo  
AC Output Impedance  
Average value during switching transition. Used  
for determining series termination value.  
40  
Ω
Document #: 38-07259 Rev. *C  
Page 17 of 20  
W312-02  
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)  
Parameter  
Description  
Frequency, Actual  
Deviation from 24 MHz  
PLL Ratio  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
Test Condition/Comments  
Determined by PLL divider ratio (see m/n below)  
(24.004 – 24)/24  
(14.31818 MHz x 57/34 = 24.004 MHz)  
Measured from 0.4V to 2.4V  
Measured from 2.4V to 0.4V  
Measured on rising and falling edge at 1.5V  
Assumes full supply voltage reached within 1 ms  
Min.  
Typ.  
24.004  
+167  
Max. Unit  
MHz  
f
fD  
m/n  
tR  
tF  
tD  
ppm  
57/34  
0.5  
0.5  
45  
2
2
55  
3
V/ns  
V/ns  
%
fST  
Frequency Stabilization  
ms  
from Power-up (cold start) from power-up. Short cycles exist prior to  
frequency stabilization.  
Zo  
AC Output Impedance  
Average value during switching transition. Used  
for determining series termination value.  
40  
Ω
VDD  
1.5V  
+
V1  
3.3  
-
R1  
68  
Z0 = 52Ω  
Length = 5”  
T1  
Z0 = 52Ω  
Length = 3  
T2  
”
R8  
47  
CPUCLK_T  
20p  
1.5V  
Clock Chip  
Driver  
CPU  
R3  
68  
Z0 = 52Ω  
Length = 5”  
T4  
Z0 = 52Ω  
Length = 3  
T5  
”
R9  
47  
CPUCLK_C  
20p  
Figure 1. K7 Open Drain Clock Driver Test Circuit  
Package Type  
Ordering Information  
Ordering Code  
W312-02H  
Product Flow  
48-pin SSOP  
Commercial, 0°C to 70°C  
W312-02HT  
48-pin SSOP - Tape and Reel  
Commercial, 0°C to 70°C  
Lead-free  
CYW312OXC  
CYW312OXCT  
48-pin SSOP  
48-pin SSOP - Tape and Reel  
Commercial, 0°C to 70°C  
Commercial, 0°C to 70°C  
Document #: 38-07259 Rev. *C  
Page 18 of 20  
W312-02  
Package Drawing and Dimension  
48-Lead Shrunk Small Outline Package O48  
51-85061-*C  
VIA is a trademark of VIA Technologies, Inc. All product and company names mentioned in this document may be the trademarks  
of their respective holders.  
Document #: 38-07259 Rev. *C  
Page 19 of 20  
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
W312-02  
Document History Page  
Document Title: W312-02 FTG for VIA™ K7 Series Chipset with Programmable Output Frequency  
Document Number: 38-07259  
Issue  
Date  
01/07/02  
Orig. of  
Change  
SZV  
REV.  
**  
*A  
ECN NO.  
110524  
118014  
Description of Change  
Change from Spec number: 38-01087 to 38-07259  
09/13/02  
RGL  
Changed the KT266 word to K7 Series in the title and features in page 1.  
Filled up all the missing Byte # and Byte heading description on all the serial  
configuration tables on pages 6-12.  
Replaced the package drawing and dimension as per CY standard.  
Removed the word “PRELIMINARY”  
*B  
*C  
122860  
358435  
12/19/02  
See ECN  
RBI  
RGL  
Added power-up requirements to maximum ratings information.  
Added Lead-free devices  
Document #: 38-07259 Rev. *C  
Page 20 of 20  
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