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CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Single-channel HOTLink II™ Transceiver

• Optional Phase Align Buffer in Transmit Path

• Compatible with

— Fiber-optic modules

— Copper cables

—Circuit board traces

Features

• Second-generation HOTLink^®technology

• Compliant to multiple standards

—ESCON^®, DVB-ASI, Fibre Channel and Gigabit

Ethernet (IEEE802.3z)

—CPRI™ compliant

— CYW15G0101DXB compliant to OBSAI-RP3

— CYV15G0101DXB compliant to SMPTE 259M and

SMPTE 292M

• JTAG boundary scan

• Built-In Self-Test (BIST) for at-speed link testing

• Per-channel Link Quality Indicator

— Analog signal detect

— Digital signal detect

• Low power 1.25W @ 3.3V typical

• Single 3.3V supply

• 100-ball BGA

• Pb-Free package option available

• 0.25µ BiCMOS technology

—8B/10B encoded or 10-bit unencoded data

• Single-channel transceiver operates from 195 to

1500 MBaud serial data rate

— CYW15G0101DXB operates from 195 to 1540 MBaud

• Selectable parity check/generate

• Selectable input clocking options

• Selectable output clocking options

• MultiFrame™ Receive Framer

— Bit and Byte alignment

—Comma or full K28.5 detect

—Single- or Multi-Byte framer for byte alignment

— Low-latency option

Functional Description

The CYP(V)15G0101DXB^[1]single-channel HOTLink II™

transceiver is a point-to-point communications building block

allowing the transfer of data over a high-speed serial link

(optical fiber, balanced, and unbalanced copper transmission

lines) at signaling speeds ranging from 195 to 1500 MBaud.

The transmit channel accepts parallel characters in an Input

Register, encodes each character for transport, and converts

it to serial data. The receive channel accepts serial data and

converts it to parallel data, frames the data to character bound-

aries, decodes the framed characters into data and special

characters, and presents these characters to an Output

Register. Figure 1 illustrates typical connections between

• Synchronous LVTTL parallel input and parallel output

interface

• Internal phase-locked loops (PLLs) with no external

PLL components

• Dual differential PECL-compatible serial inputs

— Internal DC-restoration

independent

host

systems

and

corresponding

• Dual differential PECL-compatible serial outputs

— Source matched for driving 50Ω transmission lines

— No external bias resistors required

— Signaling-rate controlled edge-rates

• Optional Elasticity Buffer in Receive Path

CYP(V)(W)15G0101DXB parts. As a second-generation

HOTLink device, the CYP(V)(W)15G0101DXB extends the

HOTLink II family with enhanced levels of integration and

faster data rates, while maintaining serial-link compatibility

(data, command, and BIST) with other HOTLink devices.

10

Serial Link

10

Backplane or Cabled

Connections

Figure 1. HOTLink II System Connections

Note:

1. CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0101DXB refers to OBSAI RP3 compliant devices (maximum

operating data rate is 1540 MBaud). CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and

also OBSAI RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0101DXB refers to all three devices.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-02031 Rev. *J

Revised March 24, 2005

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

The CYW15G0101DXB^[1]operates from 195 to 1540 MBaud,

which includes operation at the OBSAI RP3 datarate of both

1536 MBaud and 768 MBaud.

The parallel I/O interface may be configured for numerous

forms of clocking to provide the highest flexibility in system

architecture. In addition to clocking the transmit path interfaces

from one or multiple sources, the receive interface may be

configured to present data relative to a recovered clock or to a

local reference clock.

The transmit and the receive channels contain BIST pattern

generators and checkers, respectively. This BIST hardware

allows at-speed testing of the high-speed serial data paths in

both transmit and receive sections, as well as across the inter-

connecting links.

The CYV15G0101DXB satisfies the SMPTE 259M and

SMPTE 292M compliance as per the EG34-1999 Pathological

Test Requirements. The transmit (TX) section of the

CYP(V)(W)15G0101DXB single-channel HOTLink II consists

of a byte-wide channel. The channel can accept either eight-bit

data characters or pre-encoded 10-bit transmission

characters. Data characters are passed from the Transmit

Input Register to an embedded 8B/10B Encoder to improve

their serial transmission characteristics. These encoded

characters are then serialized and output from dual Positive

ECL (PECL)-compatible differential transmission-line drivers

at a bit-rate of either 10 or 20 times the input reference clock.

The receive (RX) section of the CYP(V)(W)15G0101DXB

Single-channel HOTLink II consists of a byte-wide channel.

The channel accepts a serial bit-stream from one of two

PECL-compatible differential Line Receivers and, using a

completely integrated PLL Clock Synchronizer, recovers the

timing information necessary for data reconstruction. The

recovered bit-stream is deserialized and framed into

characters, 8B/10B decoded, and checked for transmission

errors. Recovered decoded characters are then written to an

internal Elasticity Buffer, and presented to the destination host

system. The integrated 8B/10B Encoder/Decoder may be

bypassed for systems that present externally encoded or

scrambled data at the parallel interface.

HOTLink II devices are ideal for a variety of applications where

parallel interfaces can be replaced with high-speed,

point-to-point serial links. Some applications include

interconnecting

backplanes

on

switches,

routers,

base-stations, servers and video transmission systems.

The CYV15G0101DXB is verified by testing to be compliant to

all the pathological test patterns documented in SMPTE

EG34-1999, for both the SMPTE 259M and 292M signaling

rates. The tests ensure that the receiver recovers data with no

errors for the following patterns:

1. Repetitions of 20 ones and 20 zeros.

2. Single burst of 44 ones or 44 zeros.

3. Repetitions of 19 ones followed by 1 zero or 19 zeros fol-

lowed by 1 one.

Transceiver Logic Block Diagram

x10

x11

Phase

Align

Elasticity

Buffer

Decoder

8B/10B

Encoder

8B/10B

Framer

Serializer

Deserializer

RX

TX

Document #: 38-02031 Rev. *J

Page 2 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

= Internal Signal

TRSTZ

Logic Block Diagram

REFCLK+

Character-Rate Clock

REFCLK–

Transmit PLL

Bit-Rate Clock

TXRATE

SPDSEL

Clock Multiplier

Character-Rate Clock

TXCLKO+

TXCLKO–

2

Transmit

Mode

TXMODE[1:0]

TXPER

SCSEL

12

10

12

OUT1+

OUT1–

OUT2+

OUT2–

TXD[7:0]

8

TXOP

TXCT[1:0]

2

TXLB

TXCKSEL

H M L

2

TXCLK

TXRST

PARCTL

BOE[1:0]

4

Output

Enable

Latch

OELE

BIST Enable

Latch

RX PLL Enable

Latch

BISTLE

RXLE

Character-Rate Clock

SDASEL

LPEN

Receive

INSEL

Signal

LFI

Monitor

IN1+

IN1–

8

RXD[7:0]

IN2+

IN2–

Clock &

Data

RXOP

RXST[2:0]

3

Recovery

PLL

TXLB

FRAMCHAR

RFEN

RXCLK+

RXCLK–

Clock

Select

÷2

RFMODE

Delay

DECMODE

RXRATE

RXCLKC+

RXMODE

RXCKSEL

TMS

TCLK

TDI

JTAG

Boundary

Scan

Controller

TDO

Document #: 38-02031 Rev. *J

Page 3 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Pin Configuration

Top View

5

1

2

3

4

6

7

8

9

10

V_CC

IN2+

V_CC

OUT2– RXMODE TXMODE[1]

IN1+

V_CC

OUT1–

V_CC

A

V_CC

IN2–

TDO

OUT2+ TXRATE TXMODE[0]

IN1–

#NC^[2]

OUT1+

V_CC

B

RFEN

LPEN

RXLE RXCLKC+ RXRATE SDASEL SPDSEL PARCTL RFMODE INSEL

C

BOE[0]

BOE[1] FRAMCHA

R

GND

TMS

TRSTZ

TDI

D

BISTLE DECMOD

OELE

TCLK RXCKSEL TXCKSEL

E

RXST[2] RXST[1] RXST[0]

GND

LFI

GND

TXPER REFCLK– REFCLK+

TXOP TXCLKO+ TXCLKO–

F

G

H

J

RXOP

RXD[0]

V_CC

RXD[1]

RXD[2]

RXD[3]

RXD[4]

RXD[5]

RXD[6]

RXD[7]

V_CC

TXCT[1]

TXD[6]

TXD[5]

TXD[4]

TXD[3]

TXD[2]

TXD[1]

TXCLK

TXD[0]

V_CC

TXRST

#NC^[2]

SCSEL

#NC^[2]

V_CC

RXCLK– TXCT[0]

V_CC

RXCLK+

TXD[7]

Bottom View

5

V_CC

K

10

9

8

7

6

4

3

2

1

V_CC

OUT1–

V_CC

IN1+

TXMODE[1] RXMODE OUT2–

V_CC

IN2+

V_CC

A

B

C

V_CC

OUT1+

#NC^[2]

IN1–

TXMODE[0] TXRATE OUT2+

TDO

IN2–

V_CC

INSEL RFMODE PARCTL SPDSEL SDASEL RXRATE RXCLKC+ RXLE

LPEN

RFEN

BOE[0]

TDI

TRSTZ

TMS

GND

FRAMCHA BOE[1]

R

D

TXCKSEL RXCKSEL TCLK

OELE

DECMOD BISTLE

E

F

REFCLK+ REFCLK– TXPER

TXCLKO– TXCLKO+ TXOP

GND

LFI

RXST[0] RXST[1] RXST[2]

RXD[5]

RXD[6]

RXD[7]

V_CC

RXD[1]

RXD[2]

RXD[3]

RXD[4]

RXOP

RXD[0]

V_CC

G

H

J

#NC^[2]

V_CC

TXRST

#NC^[2]

SCSEL

TXCLK

TXD[0]

V_CC

TXD[3]

TXD[2]

TXD[1]

TXD[6]

TXD[5]

TXD[4]

TXCT[1]

TXCT[0] RXCLK–

TXD[7] RXCLK+

V_CC

K

Note:

2. #NC = Do Not Connect.

Document #: 38-02031 Rev. *J

Page 4 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Pin Descriptions CYP(V)(W)15G0101DXB Single-channel HOTLink II

Pin Name I/O Characteristics Signal Description

Transmit Path Data Signals

TXPER

LVTTL Output,

Transmit Path Parity Error. Active HIGH. Asserted (HIGH) if parity checking is enabled

changes relative to (PARCTL ≠ LOW) and a parity error is detected at the Encoder. This output is HIGH for one

REFCLK↑^[3]

transmit character-clock period to indicate detection of a parity error in the character

presented to the Encoder.

If a parity error is detected, the character in error is replaced with a C0.7 character to force

a corresponding bad-character detection at the remote end of the link. This replacement

takes place regardless of the encoded/un-encoded state of the interface.

When BIST is enabled for the specific transmit channel, BIST progress is presented on this

output. Once every 511 character times (plus a 16-character Word Sync Sequence when

the receive channel is clocked by REFCLK, i.e., RXCKSEL = LOW), the TXPER signal

pulses HIGH for one transmit-character clock period (if RXCKSEL = MID) or seventeen

transmit-character clock periods (if RXCKSEL = LOW or HIGH) to indicate a complete pass

through the BIST sequence. For RXCKSEL = LOW or HIGH, If TXMODE[1:0] = LL, then no

Word Sync Sequence is sent in BIST, and TXPER pulses HIGH for one transmit-character

clock period.

This output also provides an indication of a Phase-Align Buffer underflow/overflow

condition. When the Phase-Align Buffer is enabled (TXCKSEL ≠ LOW, or TXCKSEL = LOW

and TXRATE = HIGH), and an underflow/overflow condition is detected, TXPER is asserted

and remains asserted until either an atomic Word Sync Sequence is transmitted or TXRST is

sampled LOW to recenter the Phase-Align Buffer.

TXCT[1:0]

LVTTL Input,

synchronous,

Transmit Control. These inputs are captured on the rising edge of the transmit interface

clock as selected by TXCKSEL, and are passed to the Encoder or Transmit Shifter. They

sampled by TXCLK↑ identify how the TXD[7:0] characters are interpreted. When the Encoder is enabled, these

or REFCLK↑^[3]

inputs determine if the TXD[7:0] character is encoded as Data, a Special Character code,

a K28.5 fill character or a Word Sync Sequence. When the Encoder is bypassed, these

inputs are interpreted as data bits. See Table 1 for details.

TXD[7:0]

TXOP

LVTTL Input,

Transmit Data Inputs. These inputs are captured on the rising edge of the transmit

synchronous,

interface clock as selected by TXCKSEL, and passed to the Encoder or Transmit Shifter.

sampled by TXCLK↑

When the Encoder is enabled (TXMODE[1] ≠ LOW), TXD[7:0] specify the specific data or

command character to be sent. When the Encoder is bypassed, these inputs are interpreted

as data bits of the 10-bit input character. See Table 1 for details.

Transmit Path Odd Parity. When parity checking is enabled (PARCTL ≠ LOW), the parity

captured at this input is XORed with the data on the TXD bus (and sometimes TXCT[1:0])

to verify the integrity of the captured character. See Table 2 for details.

or REFCLK↑^[3]

LVTTL Input,

synchronous,

internal pull-up,

sampled by TXCLK↑

or REFCLK↑^[3]

SCSEL

LVTTL Input,

Special Character Select. Used in some transmit modes along with TXCTx[1:0] to encode

synchronous,

special characters or to initiate a Word Sync Sequence. When the transmit path is

internal pull-down, configured to select TXCLK to clock the input register (TXCKSEL = MID or HIGH), SCSEL

sampled by TXCLK↑ is captured relative to TXCLK↑.

or REFCLK↑^[3]

Note:

3. When REFCLK is configured for half-rate operation (TXRATE = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges

of REFCLK.

Document #: 38-02031 Rev. *J

Page 5 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Pin Descriptions CYP(V)(W)15G0101DXB Single-channel HOTLink II (continued)

Pin Name

I/O Characteristics Signal Description

TXRST

LVTTL Input,

asynchronous,

internal pull-up,

sampled by

Transmit Clock Phase Reset. Active LOW. When sampled LOW, the transmit Phase-align

Buffer is allowed to adjust its data-transfer timing (relative to the selected input clock) to

allow clean transfer of data from the Input Register to the Encoder or Transmit Shifter. When

TXRST is sampled HIGH, the internal phase relationship between the TXCLK and the

internal character-rate clock is fixed and the device operates normally.

REFCLK↑^[3]

When configured for half-rate REFCLK sampling of the transmit character stream

(TXCKSEL = LOW and TXRATE = HIGH), assertion of TXRST is only used to clear

Phase-align buffer faults caused by highly asymmetric reference clock periods or reference

clocks with excessive cycle-to-cycle jitter. During this alignment period, one or more

characters may be added to or lost from all the associated transmit paths as the transmit

Phase-align Buffers are adjusted. TXRST must be sampled LOW by a minimum of two

consecutive rising edges of REFCLK to ensure the reset operation is initiated correctly on

all channels. This input is ignored when both TXCKSEL and TXRATE are LOW, since the

phase align buffer is bypassed. In all other configurations, TXRST should be asserted during

device initialization to ensure proper operation of the Phase-align buffer. TXRST should be

asserted after the assertion and deassertion of TRSTZ, after the presence of a valid TXCLK

and after allowing enough time for the TXPLL to lock to the reference clock (as specified by

parameter t_TXLOCK).

Transmit Path Clock and Clock Control

TXCKSEL

3-Level Select static Transmit Clock Select. Selects the clock source used to write data into the Transmit Input

control input^[4]

Register of the transmit channel. When LOW, the Input Register is clocked by REFCLK↑.^[3]

When HIGH or MID, TXCLK↑ is the Input Register clock for TXD[7:0] and TXCT[1:0].

When TXRATE=HIGH, configuring TXCKSEL = HIGH or MID is an invalid mode of

operation.

TXCLKO±

LVTTL Output

LVTTL Input,

Transmit Clock Output. This true and complement output clock is synthesized by the

transmit PLL and is synchronous to the internal transmit character clock. It has the same

frequency as REFCLK (when TXRATE = LOW), or twice the frequency of REFCLK (when

TXRATE = HIGH). This output clock has no direct phase relationship to REFCLK.

TXRATE

Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multiplies

Static Control input, REFCLK by 20 to generate the serial bit-rate clock.

internal pull-down

When TXRATE = LOW, the transmit PLL multiplies REFCLK by 10 to generate the serial

bit-rate clock. See Table 9 for a list of operating serial rates.

When REFCLK is selected to clock the receive parallel interfaces (RXCKSEL = LOW), the

TXRATE input also determines if the clocks on the RXCLK± and RXCLKC+ outputs are full

or half-rate. When TXRATE = HIGH (REFCLK is half-rate), the RXCLK± and RXCLKC+

output clocks are also half-rate clocks and follow the frequency and duty cycle of the

REFCLK input. When TXRATE = LOW (REFCLK is full-rate), the RXCLK± and RXCLKC+

output clocks are also full-rate clocks and follow the frequency and duty cycle of the

REFCLK input.

When TXRATE=HIGH, configuring TXCKSEL = HIGH or MID is an invalid mode of

operation.

TXCLK

LVTTL Clock Input, Transmit Path Input Clock. This clock must be frequency-coherent to TXCLKO±, but may

internal pull-down

be offset in phase. The internal operating phase of the input clock (relative to REFLCK or

TXCLKO+) is adjusted when TXRST = LOW and locked when TXRST = HIGH.

Transmit Path Mode Control

TXMODE[1:0] 3-Level Select^[4]

Transmit Operating Mode. These inputs are interpreted to select one of nine operating

static control inputs modes of the transmit path. See Table 3 for a list of operating modes.

Note:

4. 3-Level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH.

The LOW level is usually implemented by direct connection to V (ground). The HIGH level is usually implemented by direct connection to V (power). When

SS

CC

not connected or allowed to float, a 3-Level select input will self-bias to the MID level.

Document #: 38-02031 Rev. *J

Page 6 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Pin Descriptions CYP(V)(W)15G0101DXB Single-channel HOTLink II (continued)

Pin Name I/O Characteristics Signal Description

Receive Path Data Signals

RXD[7:0]

RXST[2:0]

RXOP

LVTTL Output,

Parallel Data Output. These outputs change following the rising edge of the selected

synchronous to the receive interface clock.

RXCLK↑ output

When the Decoder is enabled (DECMODE = HIGH or MID), these outputs represent either

(orREFCLK↑input^[3]

when RXCKSEL =

LOW)

received data or a special character. The status of the received data is represented by the

values of RXST[2:0].

When the Decoder is bypassed (DECMODE = LOW), RXD[7:0] become the higher order

bits of the 10-bit received character. See Table 13 for details.

LVTTL Output,

Parallel Status Output. These outputs change following the rising edge of the selected

synchronous to the receive interface clock.

RXCLK↑ output

When the Decoder is bypassed (DECMODE = LOW), RXST[1:0] become the two low-order

(orREFCLK↑input^[3]

when RXCKSEL =

LOW)

bits of the 10-bit received character, while RXST[2] = HIGH indicates the presence of a

Comma character in the Output Register.

When the Decoder is enabled (DECMODE = HIGH or MID), RXST[2:0] provide status of

the received signal. See Table 16 for a list of Receive Character status.

3-state, LVTTL

Receive Path Odd Parity. When parity generation is enabled (PARCTL ≠ LOW), the parity

Output,synchronous output is valid for the data on the RXD bus bits.

to the RXCLK↑

When parity generation is disabled (PARCTL = LOW), this output driver is disabled

output (or REFCLK↑

(High-Z).

input^[3]when

RXCKSEL = LOW)

Receive Path Clock and Clock Control

RXCLK±

3-state, LVTTL

Receive Character Clock Output. When configured such that the output data path is

clocked by the recovered clock (RXCKSEL = MID), these true and complement clocks are

the receive interface clocks which are used to control timing of output data (RXD[7:0],

RXST[2:0] and RXOP). This clock is output continuously at either the dual-character rate

(1/20^ththe serial bit-rate) or character rate (1/10^ththe serial bit-rate) of the data being

received, as selected by RXRATE.

Output clock

When configured such that the output data path is clocked by REFCLK instead of recovered

clock (RXCKSEL = LOW), the RXCLK± output drivers present a buffered and delayed form

of REFCLK. In this mode, RXCLK± and RXCLKC+ are buffered forms of REFCLK that are

slightly different in phase, but follow the frequency and duty cycle of REFCLK. This phase

difference allows the user to select the optimal set-up/hold timing for their specific interface.

RXCLKC+

RXRATE

3-state, LVTTL

Output

Delayed REFCLK+ when RXCKSEL = LOW. Delayed form of REFCLK+, used for transfer

of output data to a host system. This output is only enabled when the receive parallel

interface is configured to present data relative to REFCLK (RXCKSEL = LOW). When

RXCKSEL = LOW, the RXCLKC+ follows the frequency and duty cycle of REFCLK+.

LVTTL Input

Receive Clock Rate Select. When LOW, the RXCLK± recovered clock outputs are comple-

Static Control Input, mentary clocks operating at the recovered character rate. Data for the receive channel

internal pull-down

should be latched on either the rising edge of RXCLK+ or falling edge of RXCLK–.

When HIGH, the RXCLK± recovered clock outputs are complementary clocks operating at

half the character rate. Data for the receive channel should be latched alternately on the

rising edge of RXCLK+ and RXCLK–.

When the output register is operated with REFCLK clocking (RXCKSEL = LOW), RXRATE

is not interpreted and RXCLK± follows the frequency and duty cycle of REFCLK.

RFEN

LVTTL input,

Reframe Enable. Active HIGH. When HIGH, the Framer in the receive channel is enabled

asynchronous,

internal pull-down

to frame per the presently enabled framing mode and selected framing character.

RXMODE

3-Level Select^[4]

Receive Operating Mode. This input selects one of two RXST channel status reporting

modes and is only interpreted when the Decoder is enabled (DECMODE ≠ LOW). See

Table 12 for details.

static control input

Document #: 38-02031 Rev. *J

Page 7 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Pin Descriptions CYP(V)(W)15G0101DXB Single-channel HOTLink II (continued)

Pin Name

I/O Characteristics Signal Description

FRAMCHAR 3-Level Select^[4]

static control input

Framing Character Select. Used to select the character or portion of a character used for

character framing of the received data streams.

When MID, the Framer looks for both positive and negative disparity versions of the eight-bit

Comma character.

When HIGH, the Framer looks for both positive and negative disparity versions of the K28.5

character.

Configuring FRAMCHAR = LOW is reserved for component test.

RFMODE

3-Level Select

Reframe Mode Select. Used to select the type of character framing used to adjust the

static control input^[4]character boundaries (based on detection of one or more framing characters in the data

stream. This signal operates in conjunction with the type of framing character selected.

When LOW, the Low-Latency Framer is selected. This will frame on each occurrence of the

selected framing character(s) in the received data stream. This mode of framing stretches

the recovered character-rate clock for one or multiple cycles to align that clock with the

recovered data.

When MID, the Cypress-mode Multi-Byte parallel Framer is selected. This requires a pair

of the selected framing character(s), on identical 10-bit boundaries, within a span of 50 bits

(five characters), before the character boundaries are adjusted. The recovered character

clock remains in the same phase regardless of character offset.

When HIGH, the Alternate-mode Multi-Byte parallel Framer is selected. This requires

detection of the selected framing character(s) in the received data stream, on identical 10-bit

boundaries, on four directly adjacent characters. The recovered character clock remains in

the same phase regardless of character offset.

PARCTL

3-Level Select

Parity Check/Generate Control. Used to control the parity check and generate functions.

When LOW, parity checking is disabled, and the RXOP output is disabled (High-Z).

static control input^[4]

When MID, and the 8B/10B Encoder and Decoder are enabled (TXMODE[1] ≠ LOW,

DECMODE ≠ LOW), TXD[7:0] inputs are checked (along with TXOP) for valid ODD parity,

and ODD parity is generated for the RXD[7:0] outputs and presented on RXOP. When the

8B/10B Encoder and Decoder are disabled (TXMODE[1] = LOW, DECMODE = LOW), the

TXD[7:0] and TXCT[1:0] inputs are checked (along with TXOP) for valid ODD parity, and

ODD parity is generated for the RXD[7:0] and RXST[1:0] outputs and presented on RXOP.

When HIGH, parity generation and checking are enabled. The TXD[7:0] and TXCT[1:0]

inputs are checked (along with TXOP) for valid ODD parity, and ODD parity is generated for

the RXD[7:0] and RXST[2:0] outputs and presented on RXOP.

See Table 2 and Table 15 for details.

DECMODE 3-Level Select

Decoder Mode Select. When LOW, the Decoder is bypassed and raw 10-bit characters

static control input^[4]are passed to the Output Register. When the Decoder is bypassed, RXCKSEL must be MID.

When MID, the Cypress Decoder table for Special Code Characters is used. When HIGH,

the alternate Decoder table for Special Code Characters is used. See Table 21 for a list of

the Special Codes supported in both encoded modes.

RXCKSEL

3-Level Select^[4]

Receive Clock Mode. Selects the receive clock source used to transfer data to the Output

static control input

Registers and configures the Elasticity Buffer in the receive path.

When LOW, the Output Register is clocked by REFCLK. RXCLK± and RXCLKC+ present

buffered and delayed forms of REFCLK.

When MID, the RXCLK± output follows the recovered clock as selected by RXRATE and

the Elasticity Buffer is bypassed. When the 10B/8B Decoder and Elasticity Buffer are

bypassed (DECMODE=LOW), RXCKSEL must be MID.

Configuring RXCKSEL = HIGH is an invalid mode of operation.

Device Control Signals

SPDSEL

3-Level Select,^[4]

static control input

Serial Rate Select. This input specifies the operating bit-rate range of both transmit and

receive PLLs. LOW = 195–400 MBaud, MID = 400–800 MBaud, HIGH = 800–1500 MBaud

(800–1540 MBaud for CYW15G0101DXB). When SPDSEL=LOW, setting TXRATE=HIGH

(Half-rate Reference Clock) is invalid.

Document #: 38-02031 Rev. *J

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CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Pin Descriptions CYP(V)(W)15G0101DXB Single-channel HOTLink II (continued)

Pin Name

I/O Characteristics Signal Description

REFCLK±

Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit PLL. It

or single-ended

is also used as the centering frequency of the Range Controller block of the Receive CDR

PLLs. This input clock may also be selected to clock the transmit and receive parallel inter-

faces.

LVTTL input clock

When driven by a single-ended LVCMOS or LVTTL clock source, the clock source may be

connected to either the true or complement REFCLK input, with the alternate REFCLK input

left open (floating). When driven by an LVPECL clock source, the clock must be a differential

clock, using both inputs. When TXCKSEL = LOW, REFCLK is also used as the clock for the

parallel transmit data (input) interface. When RXCKSEL = LOW and Decoder is enabled,

the Elasticity buffer is enabled and REFCLK is used as the clock source for the parallel

receive data (output) interface.

If the Elasticity Buffer is used, framing characters will be inserted or deleted to/from the data

stream to compensate for frequency differences between the reference clock and recovered

clock. When addition happens, a K28.5 will be appended immediately after a framing

character is detected in the Elasticity Buffer. When deletion happens, a framing character

will be removed from the data stream when detected in the Elasticity Buffer.

LVTTL Input,

Device Reset. Active LOW. Initializes all state machines and counters in the device.

internal pull-up

TRSTZ

When sampled LOW by the rising edge of REFLCK, this input resets the internal state

machines and sets the Elasticity Buffer pointers to a nominal offset. When the reset is

removed (TRSTZ sampled HIGH by REFCLK↑), the status and data outputs will become

deterministic in less than 16 REFCLK cycles. The BISTLE, OELE, and RXLE latches are

reset by TRSTZ. If the Elasticity Buffer or the Phase-Align Buffer are used, TRSTZ should

be applied after power up to initialize the internal pointers into these memory arrays.

Analog I/O and Control

OUT1±

OUT2±

IN1±

CML Differential

Primary Differential Serial Data Outputs. These PECL-compatible CML outputs (+3.3V

referenced) are capable of driving terminated transmission lines or standard fiber-optic

transmitter modules.

Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs

(+3.3V referenced) are capable of driving terminated transmission lines or standard

fiber-optic transmitter modules.

Output

CML Differential

Output

LVPECL Differential Primary Differential Serial Data Inputs. These inputs accept the serial data stream for

Input, with internal deserialization and decoding. The IN1± serial stream is passed to the receiver Clock and

DC restoration

Data Recovery (CDR) circuit to extract the data content when INSEL = HIGH.

IN2±

LVPECL Differential Secondary Differential Serial Data Inputs. These inputs accept the serial data stream for

Input, with internal deserialization and decoding. The IN2± serial stream is passed to the receiver CDR circuit

DC restoration

to extract the data content when INSEL = LOW.

INSEL

SDASEL

LPEN

LVTTL Input,

Receive Input Selector. Determines which external serial bit stream is passed to the receiver

asynchronous

CDR. When HIGH, the IN1± input is selected. When LOW, the IN2± input is selected.

3-Level Select,^[4]

static control input

Signal Detect Amplitude Level Select. Allows selection of one of three predefined

amplitude trip points for a valid signal indication, as listed in Table 10.

Loop-Back-Enable. Active HIGH. When asserted (HIGH), the transmit serial data is

internally routed to the receiver CDR circuit.All enabled serial drivers are forced to differ-

ential logic “1.” All serial data inputs are ignored.

LVTTL Input,

asynchronous,

internal pull-down

OELE

LVTTL Input,

asynchronous,

internal pull-up

Serial Driver Output Enable Latch Enable. Active HIGH. When OELE = HIGH, the signals

on the BOE[1:0] inputs directly control the OUTx± differential drivers. When the BOE[x] input

is HIGH, the associated OUTx± differential driver is enabled. When the BOE[x] input is LOW,

the associated OUTx± differential driver is powered down. When OELE returns LOW, the

last values present on BOE[1:0] are captured in the internal Output Enable Latch. The

specific mapping of BOE[1:0] signals to transmit output enables is listed in Table 8. If the

device is reset (TRSTZ is sampled LOW), the latch is reset to disable both outputs.

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CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Pin Descriptions CYP(V)(W)15G0101DXB Single-channel HOTLink II (continued)

Pin Name

I/O Characteristics Signal Description

BISTLE

LVTTL Input,

asynchronous,

internal pull-up

Transmit and Receive BIST Latch Enable. Active HIGH. When BISTLE = HIGH, the

signals on the BOE[1:0] inputs directly control the transmit and receive BIST enables. When

the BOE[x] input is LOW, the associated transmit or receive channel is configured to

generate or compare the BIST sequence. When the BOE[x] input is HIGH, the associated

transmit or receive channel is configured for normal data transmission or reception. When

BISTLE returns LOW, the last values present on BOE[1:0] are captured in the internal BIST

Enable latch. The specific mapping of BOE[1:0] signals to transmit and receive BIST

enables is listed in Table 8. When the latch is closed, if the device is reset (TRSTZ is

sampled LOW), the latch is reset to disable BIST on both the transmit and receive channels.

RXLE

LVTTL Input,

asynchronous,

internal pull-up

Receive Channel Power-Control Latch Enable. Active HIGH. When RXLE = HIGH, the

signal on the BOE[0] input directly controls the power enable for the receive PLL and analog

logic. When the BOE[0] input is HIGH, the receive channel PLL and analog logic are active.

When the BOE[0] input is LOW, the receive channel PLL and analog logic are placed in a

non-functional power saving mode. When RXLE returns LOW, the last value present on

BOE[0] is captured in the internal RX PLL Enable latch. The specific mapping of BOE[1:0]

signals to the receive channel enable is listed in Table 8. When the latch is closed, if the

device is reset (TRSTZ is sampled LOW), the latch is reset to disable the receive channel.

BOE[1:0]

LFI

LVTTL Input,

asynchronous,

internal pull-up

BIST, Serial Output, and Receive Channel Enables. These inputs are passed to and

through the output enable latch when OELE = HIGH, and captured in this latch when OELE

returns LOW. These inputs are passed to and through the BIST enable latch when

BISTLE = HIGH, and captured in this latch when BISTLE returns LOW. These inputs are

passed to and through the Receive Channel enable latch when RXLE = HIGH, and captured

in this latch when RXLE returns LOW.

Link Fault Indication Output. Active LOW. LFI is the logical OR of four internal conditions:

1. Received serial data frequency outside expected range

2. Analog amplitude below expected levels

LVTTL Output,

Asynchronous

3. Transition density lower than expected

4. Receive Channel disabled.

JTAG Interface

TMS

LVTTL Input,

Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high for

> 5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset automat-

ically upon application of power to the device.

internal pull-up

TCLK

TDO

TDI

LVTTL Input,

JTAG Test Clock.

internal pull-down

Three-State

Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not

LVTTL Output

selected.

LVTTL Input,

Test Data In. JTAG data input port.

internal pull-up

Power

V_CC

+3.3V power

GND

Signal and power ground for all internal circuits

Document #: 38-02031 Rev. *J

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CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

operated synchronous to REFCLK↑ (TXCKSEL = LOW and

TXRATE = LOW), the Phase-Align Buffer is bypassed and

data is passed directly to the Parity Check and Encoder block

to reduce latency.

When an Input Register clock with an uncontrolled phase

relationship to REFCLK is selected (TXCKSEL ≠ LOW) or if

data is captured on both edges of REFCLK

(TXRATE = HIGH), the Phase-Align Buffer is enabled. This

buffer is used to absorb clock phase differences between the

presently selected input clock and the internal character clock.

Initialization of the Phase-Align Buffer takes place when the

TXRST input is sampled LOW by two consecutive rising edges

of REFCLK. When TXRST is returned HIGH, the present input

clock phase relative to REFCLK↑ is set. TXRST is an

asynchronous input, but is sampled internally to synchronize

it to the internal transmit path state machine.

Once set, the input clock is allowed to skew in time up to half

a character period in either direction relative to REFCLK↑;

i.e., ±180°. This time shift allows the delay path of the

character clock (relative to REFLCK↑) to change due to

operating voltage and temperature, while not affecting the

design operation.

If the phase offset, between the initialized location of the input

clock and REFCLK↑, exceeds the skew handling capabilities

of the Phase-Align Buffer, an error is reported on the TXPER

output. This output indicates a continuous error until the

Phase-Align Buffer is reset. While the error remains active, the

transmitter outputs a continuous C0.7 character to indicate to

the remote receiver that an error condition is present in the

link.

In specific transmit modes, it is also possible to reset the

Phase-Align Buffer with minimal disruption of the serial data

stream. When the transmit interface is configured for gener-

ation of atomic Word Sync Sequences (TXMODE[1] = MID)

and a Phase-Align Buffer error is present, the transmission of

a Word Sync Sequence will recenter the Phase-Align Buffer

and clear the error condition.^[6]

CYP(V)(W)15G0101DXB HOTLink II Operation

The CYP(V)(W)15G0101DXB is a highly configurable device

designed to support reliable transfer of large quantities of data

using high-speed serial links from a single source to one or

more destinations.

CYP(V)(W)15G0101DXB Transmit Data Path

Operating Modes

The transmit path of the CYP(V)(W)15G0101DXB supports a

single character-wide data path. This data path is used in

multiple operating modes as controlled by the TXMODE[1:0]

inputs.

Input Register

The bits in the Input Register support different assignments,

based on if the character is unencoded, encoded with two

control bits, or encoded with three control bits. These assign-

ments are shown in Table 1.

Table 1. Input Register Bit Assignments^[5]

Encoded

(Encoder Enabled)

Unencoded

(Encoder

Two-bit

Control

Three-bit

Control

Signal Name

TXD[0] (LSB)

TXD[1]

Bypassed)

DIN[0]

DIN[1]

DIN[2]

DIN[3]

DIN[4]

DIN[5]

DIN[6]

DIN[7]

DIN[8]

DIN[9]

N/A

TXD[0]

TXD[1]

TXD[2]

TXD[3]

TXD[4]

TXD[5]

TXD[6]

TXD[7]

TXCT[0]

TXCT[1]

N/A

TXD[0]

TXD[1]

TXD[2]

TXD[3]

TXD[4]

TXD[5]

TXD[6]

TXD[7]

TXCT[0]

TXCT[1]

SCSEL

TXD[2]

TXD[3]

TXD[4]

TXD5]

TXD[6]

TXD[7]

TXCT[0]

TXCT[1] (MSB)

SCSEL

Parity Support

In addition to the ten data and control bits that are captured at

the transmit Input Register, a TXOP input is also available.

This allows the CYP(V)(W)15G0101DXB to support ODD

parity checking. Parity checking is available for all operating

modes (including Encoder Bypass). The specific mode of

parity checking is controlled by the PARCTL input, and

operates per Table 2.

When PARCTL = MID (open) and the Encoder is enabled

(TXMODE[1] ≠ LOW), only the TXD[7:0] data bits are checked

for ODD parity along with the TXOP bit. When

PARCTL = HIGH with the Encoder enabled (or MID with the

Encoder bypassed), the TXD[7:0] and TXCT[1:0] inputs are

checked for ODD parity along with the TXOP bit. When

PARCTL = LOW, parity checking is disabled.

The Input Register captures a minimum of eight data bits and

two control bits on each input clock cycle. When the Encoder

is bypassed, the TXCT[1:0] control bits are part of the

pre-encoded 10-bit data character.

When the Encoder is enabled (TXMODE[1] ≠ LOW), the

TXCT[1:0] bits are interpreted along with the TXD[7:0]

character to generate the specific 10-bit transmission

character. When TXMODE[0] ≠ HIGH, an additional special

character select (SCSEL) input is also captured and inter-

preted. This SCSEL input is used to modify the encoding of the

characters.

Phase-Align Buffer

Data from the Input Register is passed either to the Encoder

or to the Phase-Align buffer. When the transmit path is

Notes:

5. The TXOP input is also captured in the Input Register, but its interpretation is under the separate control of PARCTL.

6. One or more K28.5 characters may be added or lost from the data stream during this reset operation. When used with non-Cypress devices that require a

complete 16-character Word Sync Sequence for proper receive Elasticity Buffer alignment, it is recommend that the sequence be followed by a second Word

Sync Sequence to ensure proper operation.

Document #: 38-02031 Rev. *J

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CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

When parity checking and the Encoder are both enabled

(TXMODE[1] ≠ LOW), the detection of a parity error causes a

C0.7 character of proper disparity to be passed to the Transmit

Shifter. When the Encoder is bypassed (TXMODE[1] = LOW),

detection of a parity error causes a positive disparity version

of a C0.7 transmission character to be passed to the Transmit

Shifter.

a serial link. The characters must usually be processed or

transformed to guarantee

• aminimumtransition density (toallow the serial receive PLL

to extract a clock from the data stream)

• a DC-balance in the signaling (to prevent baseline wander)

• run-length limits in the serial data (to limit the bandwidth of

the link)

Table 2. Input Register Bits Checked for Parity^[8]

• the remote receiver a way of determining the correct

character boundaries (framing).

Transmit Parity Check Mode (PARCTL)

MID

When the Encoder is enabled (TXMODE[1] ≠ LOW), the

characters to be transmitted are converted from Data or

Special Character codes to 10-bit transmission characters (as

selected by the TXCT[1:0] and SCSEL inputs), using an

integrated 8B/10B Encoder. When directed to encode the

character as a Special Character code, it is encoded using the

special character encoding rules listed in Table 21. When

directed to encode the character as a Data character, it is

encoded using the Data Character encoding rules in Table 20.

The 8B/10B Encoder is standards compliant with ANSI/NCITS

ASC X3.230-1994 (Fibre Channel), IEEE 802.3z (Gigabit

Ethernet), the IBM^ESCON^and FICON™, and Digital Video

Broadcast (DVB-ASI) standards for data transport.

Many of the Special Character codes listed in Table 21 may be

generated by more than one input character. The

CYP(V)(W)15G0101DXB is designed to support two

independent (but non-overlapping) Special Character code

tables. This allows the CYP(V)(W)15G0101DXB to operate in

mixed environments with other Cypress HOTLink devices

using the enhanced Cypress command code set, and the

reduced command sets of other non-Cypress devices. Even

when used in an environment that normally uses non-Cypress

Special Character codes, the selective use of Cypress

command codes can permit operation where running disparity

and error handling must be managed.

Signal

Name

TXMODE[1] TXMODE[1]

LOW

= LOW

≠ LOW

HIGH

X

TXD[0]

TXD[1]

TXD[2]

TXD[3]

TXD[4]

TXD[5]

TXD[6]

TXD[7]

TXCT[0]

TXCT[1]

TXOP

X^[7]

X

Encoder

The character, received from the Input Register or

Phase-Align Buffer and Parity Check Logic, is then passed to

the Encoder logic. This block interprets each character and

any control bits, and outputs a 10-bit transmission character.

Following conversion of each input character from eight bits to

a 10-bit transmission character, it is passed to the Transmit

Shifter and is shifted out LSB first, as required by ANSI and

IEEE standards for 8B/10B coded serial data streams.

Depending on the configured operating mode, the generated

transmission character may be

• the 10-bit pre-encoded character accepted in the Input

Register

• the10-bitequivalentoftheeight-bitdatacharacteraccepted

Transmit Modes

in the Input Register

The operating mode of the transmit path is set through the

TXMODE[1:0] inputs. These 3-level select inputs allow one of

nine transmit modes to be selected. The transmit modes are

listed in Table 3.

• the 10-bit equivalent of the eight -bit special character code

accepted in the Input Register

• the 10-bit equivalent of the C0.7 SVS character if parity

checking was enabled and a parity error was detected

The encoded modes (TX Modes 3 through 8) support multiple

encoding tables. These encoding tables vary by the specific

combinations of SCSEL, TXCT[1], and TXCT[0] that are used

to control the generation of data and control characters. These

multiple encoding forms allow maximum flexibility in inter-

facing to legacy applications, while also supporting numerous

extensions in capabilities.TX Mode 0—Encoder Bypass

When the Encoder is bypassed, the character captured from

the TXD[7:0] and TXCT[1:0] inputs is passed directly to the

Transmit Shifter without modification. If parity checking is

enabled (PARCTL ≠ LOW) and a parity error is detected, the

10-bit character is replaced with the 1001111000 pattern

(+C0.7 character) regardless of the running disparity of the

previous character.

• the 10-bit equivalent of the C0.7 SVS character if a

Phase-Align Buffer overflow or underflow error is present

• a character that is part of the 511-character BIST sequence

• a K28.5 character generated as an individual character or

as part of the 16-character Word Sync Sequence.

The selection of the specific characters generated are

controlled by the TXMODE[1:0], SCSEL, TXCT[1:0], and

TXD[7:0] inputs for each character.

Data Encoding

Raw data, as received directly from the Transmit Input

Register, is seldom in a form suitable for transmission across

Notes:

7. Bits marked as X are XORed together. Result must be a logic-1 for parity to be valid.

8. Transmit path parity errors are reported on the TXPER output.

Document #: 38-02031 Rev. *J

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CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

With the Encoder bypassed, the TXCT[1:0] inputs are

considered part of the data character and do not perform a

control function that would otherwise modify the interpretation

of the TXD[7:0] bits. The bit usage and mapping of these

control bits when the Encoder is bypassed is shown in Table 4.

Table 5. TX Modes 3 and 6 Encoding

Characters Generated

Encoded data character

K28.5 fill character

Special character code

16-character Word Sync Sequence

In Encoder Bypass mode, the SCSEL input is ignored. All

X

0

1

X

0

1

0

1

clocking modes interpret the data in the same way.

Table 4. Encoder Bypass Mode (TXMODE[1:0 = LL)

Signal Name

TXD[0] (LSB)

Bus Weight

10B Name

2⁰

2¹

2²

2³

2⁴

2⁵

2⁶

2⁷

2⁸

2⁹

a

b

c

d

e

i

[9]

When TXCKSEL = MID or HIGH, the transmit channel

captures data into its Input Register using the TXCLK clock.

TXD[1]

TXD[2]

TXD[3]

TXD[4]

TXD[5]

Word Sync Sequence

When TXCT[1:0] = 11, a 16-character sequence of K28.5

characters, known as a Word Sync Sequence, is generated on

the transmit channel. This sequence of K28.5 characters may

start with either a positive or negative disparity K28.5 (as

determined by the current running disparity and the 8B/10B

coding rules). The disparity of the second and third K28.5

characters in this sequence are reversed from what normal

8B/10B coding rules would generate. The remaining K28.5

characters in the sequence follow all 8B/10B coding rules. The

disparity of the generated K28.5 characters in this sequence

follow a pattern of either + + – – + – + – + – + – + – + – or

– – + + – + – + – + – + – + – +.

TXD[6]

TXD[7]

f

g

h

j

TXCT[0]

TXCT[1] (MSB)

Table 3. Transmit Operating Modes

TX Mode Operating Mode

When TXMODE[1] = MID (open, TX modes 3, 4 and 5), the

generation of this character sequence is an atomic (non-inter-

ruptible) operation. Once it has been successfully started, it

cannot be stopped until all 16 characters have been

generated. The content of the Input Register is ignored for the

duration of this 16-character sequence. At the end of this

sequence, if the TXCT[1:0] = 11 condition is sampled again,

the sequence restarts and remains uninterrupted for the

following 15 character clocks.

If parity checking is enabled, the character used to start the

Word Sync Sequence must also have correct ODD parity. This

is true even though the contents of the TXD[7:0] bits do not

directly control the generation of characters during the Word

Sync Sequence. Once the sequence is started, parity is not

checked on the following 15 characters in the Word Sync

Sequence.

When TXMODE[1] = HIGH (TX modes 6, 7, and 8), the gener-

ation of the Word Sync Sequence becomes an interruptible

operation. In TX Mode 6, this sequence is started as soon as

the TXCT[1:0] = 11 condition is detected on the channel.

In order for the sequence to continue, the TXCT[1:0] inputs

must be sampled as 00 for the remaining 15 characters of the

sequence. If at any time a sample period exists where

TXCT[1:0] ≠ 00, the Word Sync Sequence is terminated, and

a character representing the data and control bits is generated

by the Encoder. This resets the Word Sync Sequence state

machine such that it will start at the beginning of the sequence

at the next occurrence of TXCT[1:0] = 11.

Word Sync

Sequence

Support

SCSEL

Control

None

TXCT Function

Encoder Bypass

Reserved for test

Encoder Control

0

1

2

3

LL None

LM None

LH None

ML Atomic

Special

Character

4

5

6

MM Atomic

MH Atomic

HL Interruptible Special

Word Sync Encoder Control

None

Encoder Control

Character

7

8

HM Interruptible Word Sync Encoder Control

HH Interruptible None Encoder Control

TX Modes 1 and 2—Factory Test Modes

These modes enable specific factory test configurations. They

are not considered normal operating modes of the device.

Entry or configuration into these test modes will not damage

the device.

TX Mode 3—Atomic Word Sync and SCSEL Control of Special

Codes

When configured in TX Mode 3, the SCSEL input is captured

along with the TXCT[1:0] data control inputs. These bits

combine to control the interpretation of the TXD[7:0] bits and

the characters generated by them. These bits are interpreted

as listed in Table 5.

Note:

9. LSB is shifted out first.

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CYP15G0101DXB

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When parity checking is enabled and TXMODE[1] = HIGH, all

characters (including those in the middle of a Word Sync

Sequence) must have correct parity. The detection of a

character with incorrect parity during a Word Sync Sequence

(regardless of the state of TXCT[1:0]) will interrupt that

sequence and force generation of a C0.7 SVS character. Any

interruption of the Word Sync Sequence causes the sequence

to terminate.

When TXCKSEL = LOW, the Input Register for the transmit

channel is clocked by REFCLK.^[3]When TXCKSEL = HIGH or

MID, the Input Register for the transmit channel is clocked with

TXCLK↑.

Transmit BIST

The transmit channel contains an internal pattern generator

that can be used to validate both device and link operation.

This generator is enabled by the BOE[1] signal, as listed in

Table 8 (when the BISTLE latch enable input is HIGH). When

enabled, a register in the transmit channel becomes a

signature pattern generator by logically converting to a Linear

Feedback Shift Register (LFSR). This LFSR generates a

511-character sequence that includes all Data and Special

Character codes, including the explicit violation symbols. This

provides a predictable yet pseudo-random sequence that can

be matched to an identical LFSR in the attached Receiver. If

the receive channel is configured for REFCLK clocking

(RXCKSEL = LOW), each pass is preceded by a 16-character

Word Sync Sequence to allow Elasticity Buffer alignment and

management of clock-frequency variations.

When the BISTLE signal is HIGH, if the BOE[1] input is LOW,

the BIST generator in the transmit channel is enabled (and if

BOE[0] = LOW the BIST checker in the receive channel is

enabled). When BISTLE returns LOW, the values of the

BOE[1:0] signals are captured in the BIST Enable Latch.

These values remain in the BIST Enable Latch until BISTLE is

returned high to open the latch again. A device reset (TRSTZ

sampled LOW), also presets the BIST Enable Latch to disable

BIST on both the transmit and receive channels.

TX Mode 4—Atomic Word Sync and SCSEL Control of

Word Sync Sequence Generation

When configured in TX Mode 4, the SCSEL input is captured

along with the TXCT[1:0] data control inputs. These bits

combine to control the interpretation of the TXD[7:0] bits and

the characters generated by them. These bits are interpreted

as listed in Table 6.

Table 6. TX Modes 4 and 7 Encoding

Characters Generated

All data and data-control information present at the TXD[7:0]

and TXCT[1:0] inputs are ignored when BIST is active on the

transmit channel.

X

0

1

X

0

1

X

0

1

Encoded data character

K28.5 fill character

Special character code

Serial Output Drivers

16-character Word Sync Sequence

The serial interface Output Drivers use high-performance

differential Current Mode Logic (CML) to provide

source-matched drivers for the transmission lines. These

Serial Drivers accept data from the Transmit Shifter. These

outputs have signal swings equivalent to that of standard

PECL drivers, and are capable of driving AC-coupled optical

modules or AC-coupled transmission lines. To acheive OBSAI

RP3 compliancy, the serial output drivers must be AC-coupled

to the transmission medium.

When configured for local loop-back (LPEN = HIGH), the

enabled Serial Drivers are configured to drive a static differ-

ential logic-1.

Each Serial Driver can be enabled or disabled through the

BOE[1:0] inputs, as controlled by the OELE latch-enable

signal. When OELE = HIGH, the signals present on the

BOE[1:0] inputs are passed through the Serial Output Enable

latch to control the Serial Driver. The BOE[1:0] input with

OUT1± and OUT2± driver is listed in Table 8.

TX Mode 4 also supports an Atomic Word Sync Sequence.

Unlike TX Mode 3, this sequence is started when both SCSEL

and TXCT[0] are sampled HIGH. With the exception of the

combination of control bits used to initiate the sequence, the

generation and operation of this Word Sync Sequence is the

same as that documented for TX Mode 3.

TX Mode 5—Atomic Word Sync, No SCSEL

When configured in TX Mode 5, the SCSEL signal is not used.

The TXCT[1:0] inputs control the characters generated by the

channel. The specific characters generated by these bits are

listed in Table 7.

Table 7. TX Modes 5 and 8 Encoding

Characters Generated

Encoded data character

K28.5 fill character

Special character code

16-character Word Sync Sequence

Table 8. Output Enable, BIST, and Receive Channel

Enable Signal Map

X

0

1

0

1

0

1

BIST

Receive PLL

Channel

Enable

Output

Controlled

(OELE)

Channel

Enable

BOE

Input

(BISTLE)

(RXLE)

BOE[1]

OUT2±

Transmit

X

TX Mode 5 also has the capability of generating an Atomic

Word Sync Sequence. For the sequence to be started, the

TXCT[1:0] inputs must both be sampled HIGH. The generation

and operation of this Word Sync Sequence is the same as that

documented for TX Mode 3.

BOE[0]

OUT1±

Receive

When OELE = HIGH and BOE[x] = HIGH, the associated

Serial Driver is enabled to drive any attached transmission

line. When OELE = HIGH and BOE[x] = LOW, the associated

driver is disabled and internally configured for minimum power

Document #: 38-02031 Rev. *J

Page 14 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

dissipation. If both Serial Drivers for the channel are disabled,

the internal logic for the transmit channel is also configured for

lowest power operation. When OELE returns LOW, the values

present on the BOE[1:0] inputs are latched in the Output

Enable Latch, and remain there until OELE returns HIGH to

open the latch again. A device reset (TRSTZ sampled LOW)

clears this latch and disables both Serial Drivers.

Note. When both serial output drivers are disabled and a

driver is re-enabled, the data on the Serial Drivers may not

meet all timing specifications for up to 200 µs.

reference point of the REFCLK+ input for alternate logic levels.

When doing so, it is necessary to ensure that the 0V-differ-

ential crossing point remains within the parametric range

supported by the input.

CYP(V)(W)15G0101DXB Receive Data Path

Serial Line Receivers

Two differential Line Receivers, IN1± and IN2±, are available

for accepting serial data streams. The active Serial Line

Receiver is selected using the INSEL input. Both Serial Line

Receivers have differential inputs, and can accommodate wire

interconnect and filtering losses or transmission line attenu-

ation greater than 16 dB. For normal operation, these inputs

should receive a signal of at least V_DIFFS> 100 mV, or 200-mV

peak-to-peak differential. Each Line Receiver can be DC- or

AC-coupled to +3.3V powered fiber-optic interface modules

(any ECL/PECL logic family, not limited to 100K PECL) or

AC-coupled to +5V-powered optical modules. The common-

mode tolerance of the receivers accommodates a wide range

of signal termination voltages. Each receiver provides internal

DC-restoration, to the center of the receiver’s common mode

range, for AC-coupled signals.

The local loop-back input (LPEN) allows the serial transmit

data to be routed internally back to the Clock and Data

Recovery circuit. When configured for local loop-back, the

transmit Serial Driver outputs are forced to output a differential

logic-1. This prevents local diagnostic patterns from being

broadcast to attached remote receivers.

Transmit PLL Clock Multiplier

The Transmit PLL Clock Multiplier accepts a character-rate or

half-character-rate external clock at the REFCLK input, and

multiples that clock by 10 or 20 (as selected by TXRATE) to

generate a bit-rate clock for use by the Transmit Shifter. It also

provides a character-rate clock used by the transmit path.

This clock multiplier PLL can accept a REFCLK input between

19.5 MHz and 150 MHz (19.5 MHz and 154 MHz for

CYW15G0101DXB), however, this clock range is limited by

the operating mode of the CYP(V)(W)15G0101DXB clock

multiplier (controlled by TXRATE) and by the level on the

SPDSEL input.

When TXRATE=HIGH, configuring TXCKSEL = HIGH or MID

is an invalid mode of operation.

SPDSEL is a 3-level select^[4](ternary) input that selects one

of three operating ranges for the serial data outputs and inputs.

The operating serial signaling-rate and allowable range of

REFCLK frequencies are listed in Table 9.

Signal Detect/Link Fault

Table 9. Operating Speed Settings

REFCLK

Each selected Line Receiver (i.e., that routed to the Clock and

Data Recovery PLL) is simultaneously monitored for

Frequency

(MHz)

Signaling

• analog amplitude above limit specified by SDASEL

• transition density greater than specified limit

SPDSEL

TXRATE

Rate (MBaud)

LOW

1

0

1

0

1

0

reserved

19.5–40

20–40

40–80

40–75

195–400

• range controller reports the received data stream within

normal frequency range (±1500 ppm)^[10]

• receive channel enabled.

MID (Open)

HIGH

400–800

All of these conditions must be valid for the Signal Detect block

to indicate a valid signal is present. This status is presented on

the LFI (Link Fault Indicator) output.

800–1500

(800–1540 for

CYW15G0101

DXB)

80–150

Analog Amplitude

While most signal monitors are based on fixed constants, the

analog amplitude level detection is adjustable to allow

operation with highly attenuated signals, or in high-noise

environments. This adjustment is made through the SDASEL

signal, a 3-level select^[4](ternary) input, which sets the trip

point for the detection of a valid signal at one of three levels,

as listed in Table 10.

The Analog Signal Detect monitor is active for the present Line

Receiver, as selected by the INSEL input. When configured for

local loop-back (LPEN = HIGH), the Analog Signal Detect

Monitor is disabled.

The REFCLK± input is a differential input with each input inter-

nally biased to 1.4V. If the REFCLK+ input is connected to a

TTL, LVTTL, or LVCMOS clock source, the input signal is

recognized when it passes through the internally biased

reference point.

When both the REFCLK+ and REFCLK− inputs are

connected, the clock source must be a differential clock. This

can be either a differential LVPECL clock that is DC- or

AC-coupled, or a differential LVTTL or LVCMOS clock.

By connecting the REFCLK− input to an external voltage

source or resistive voltage divider, it is possible to adjust the

Note:

10. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. REFCLK

must be within ±1500 PPM (±0.15%) of the remote transmitter’s PLL reference (REFCLK) frequency. Although transmitting to a HOTLink II receiver necessitates

the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be within the limits

specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z Gigabit Ethernet

compliant, the frequency stability of the crystal needs to be within ±100 PPM.

Document #: 38-02031 Rev. *J

Page 15 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Transition Density

When RXLE = HIGH and BOE[0] = HIGH, the receive channel

is enabled to receive and recover a serial stream from the Line

Receiver. When RXLE = HIGH and BOE[0] = LOW, the

receive channel is disabled and internally configured for

minimum power dissipation. When disabled, the channel

indicates a constant LFI output. When RXLE returns LOW, the

values present on the BOE[1:0] inputs are latched in the

Receive Channel Enable Latch, and remain there until RXLE

returns HIGH to open the latch again.^[12]

The Transition Detection logic checks for the absence of any

transitions spanning greater than six transmission characters

(60 bits). If no transitions are present in the data received

(within the referenced period), the Transition Detection logic

asserts LFI. The LFI output remains asserted until at least one

transition is detected in each of three adjacent received

characters.

Table 10. Analog Amplitude Detect Valid Signal Levels^[11]

Clock/Data Recovery

Typical Signal with Peak Amplitudes

The extraction of a bit-rate clock and recovery of bits from a

received serial stream is performed by a CDR block within the

receive channel. The clock extraction function is performed by

a high-performance embedded PLL that tracks the frequency

of the transitions in the incoming bit stream and aligns the

phase of the internal bit-rate clock to the transitions in the

serial data stream.

SDASEL

Above

LOW

140-mV p-p differential

MID (Open) 280-mV p-p differential

HIGH

420-mV p-p differential

Range Control

The CDR accepts

a

character-rate (bit-rate ÷ 10) or

The Clock/Data Recovery (CDR) circuit includes logic to

monitor the frequency of the phase-locked loop (PLL) Voltage

Controlled Oscillator (VCO) used to sample the incoming data

stream. This logic ensures that the VCO operates at, or near

the rate of the incoming data stream for two primary cases:

half-character-rate (bit-rate ÷ 20) reference clock from the

REFCLK input. This REFCLK input is used to

• ensure that the VCO (within the CDR) is operating at the

correct frequency

• reduce PLL acquisition time

• when the incoming data stream resumes after a time in

which it has been “missing.”

• limit unlocked frequency excursions of the CDR VCO when

there is no input data present at the selected Serial Line

Receiver.

• when the incoming data stream is outside the acceptable

frequency range.

Regardless of the type of signal present, the CDR will attempt

to recover a data stream from it. If the frequency of the

recovered data stream is outside the limits of the range control

monitor, the CDR will switch to track REFCLK instead of the

data stream. Once the CDR output (RXCLK) frequency returns

back close to REFCLK frequency, the CDR input will be

switched back to track the input data stream. In case no data

is present at the input, this switching behavior may result in

brief RXCLK frequency excursions from REFCLK. However,

the validity of the input data stream is indicated by the LFIx

output. The frequency of REFCLK is required to be within

± 1500 ppm^[10]of the frequency of the clock that drives the

REFCLK input of the remote transmitter to ensure a lock to the

incoming data stream.

For systems using multiple or redundant connections, the LFI

output can be used to select an alternate data stream. When

an LFI indication is detected, external logic can toggle

selection of the IN1± and IN2± inputs through the INSEL input.

When a port switch takes place, it is necessary for the receive

PLL to reacquire the new serial stream and frame to the

incoming character boundaries.

To perform this function, the frequency of the VCO is periodi-

cally sampled and compared to the frequency of the REFCLK

input. If the VCO is running at a frequency beyond

+1500ppm^[10]as defined by the reference clock frequency, it

is periodically forced to the correct frequency (as defined by

REFCLK, SPDSEL, and TXRATE) and then released in an

attempt to lock to the input data stream. The sampling and

relock period of the Range Control is calculated as follows:

RANGE CONTROL SAMPLING PERIOD

= (REFCLK-

PERIOD) * (16000).

During the time that the Range Control forces the PLL VCO to

run at REFCLK*10 (or REFCLK*20 when TXRATE = HIGH)

rate, the LFIx output will be asserted LOW. While the PLL is

attempting to re-lock to the incoming data stream, LFIx may be

either HIGH or LOW (depending on other factors such as

transition density and amplitude detection) and the recovered

byte clock (RXCLK) may run at an incorrect rate (depending

on the quality or existence of the input serial data stream).

After a valid serial data stream is applied, it may take up to one

RANGE CONTROL SAMPLING PERIOD before the PLL

locks to the input data stream, after which LFIx should be

HIGH.

Deserializer/Framer

Receive Channel Enabled

Each CDR circuit extracts bits from the serial data stream and

clocks these bits into the Shifter/Framer at the bit-clock rate.

When enabled, the Framer examines the data stream, looking

for one or more Comma or K28.5 characters at all possible bit

positions. The location of these characters in the data stream

are used to determine the character boundaries of all following

characters.

The CYP(V)(W)15G0101DXB receive channel can be

enabled and disabled through the BOE[0] input, as controlled

by the RXLE latch-enable signal. When RXLE = HIGH, the

signal present on the BOE[0] input is passed through the

Receive Channel Enable Latch to control the PLL and logic of

the receive channel. The BOE[1:0] input functions are listed in

Table 8.

Notes:

11. The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals

may have a sign-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase

the values in the table above by approximately 100 mV.

12. When a disabled receive channel is reenabled, the status of the LFI output and data on the parallel outputs may be indeterminate for up to 2 ms.

Document #: 38-02031 Rev. *J

Page 16 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Framing Character

adjusted if the selected framing character is detected at least

twice within a span of 50 bits, with both instances on identical

10-bit character boundaries.

The CYP(V)(W)15G0101DXB allows selection of two combi-

nations of framing characters to support requirements of

different interfaces. The selection of the framing character is

made through the FRAMCHAR input.

The specific bit combinations of these framing characters are

listed in Table 11. When the specific bit combination of the

selected framing character is detected by the Framer, the

boundaries of the characters present in the received data

stream are known.

When RFMODE = HIGH, the Alternate-mode Multi-Byte

Framer is enabled. Like the Cypress-mode Multi-Byte Framer,

multiple framing characters must be detected before the

character boundary is adjusted. In this mode, the Framer does

not adjust the character clock boundary, but instead aligns the

character to the already recovered character clock. In this

mode, the data stream must contain a minimum of four of the

selected framing characters, received as consecutive

characters, on identical 10-bit boundaries, before character

framing is adjusted.

Framing is enabled when RFEN = HIGH. If RFEN = LOW, the

Framer is disabled. When the Framer is disabled, no changes

are made to the recovered character boundary, regardless of

the presence of framing characters in the data stream.

Table 11. Framing Character Selector

Bits Detected in Framer

FRAMCHAR

LOW

MID (Open)

Character Name

Bits Detected

Reserved for test

Comma+

00111110XX^[13]

or 11000001XX

Comma–

10B/8B Decoder Block

The Decoder logic block performs three primary functions:

HIGH

–K28.5

0011111010 or

+K28.5

1100000101

• decoding the received transmission characters back into

Data and Special Character codes

Framer

• comparing generated BIST patterns with received

characters to permit at-speed link and device testing

The Framer operates in one of three different modes, as

selected by the RFMODE input. In addition, the Framer itself

may be enabled or disabled through the RFEN input. When

RFEN = LOW, the Framer is disabled, and no combination of

bits in a received data stream will alter the character bound-

aries. When RFEN = HIGH, the Framer-mode selected by

RFMODE is enabled.

When RFMODE = LOW, the Low-latency Framer is selected.

This Framer operates by stretching the recovered character

clock until it aligns with the received character boundaries. In

this mode, the Framer starts its alignment process on the first

detection of the selected framing character. To reduce the

impact on external circuits that make use of a recovered clock,

the clock period is not stretched by more than two bit-periods

in any one clock cycle. When operated with a character-rate

output clock (RXRATE = LOW), the output of properly framed

characters may be delayed by up to nine character-clock

cycles from the detection of the selected framing character.

When operated with a half-character-rate output clock

(RXRATE = HIGH), the output of properly framed characters

may be delayed by up to 14 character-clock cycles from the

detection of the selected framing character.^[14]

• generation of ODD parity on the decoded characters.

10B/8B Decoder

The framed parallel output of the Deserializer Shifter is passed

to the 10B/8B Decoder where, if the Decoder is enabled

(DECMODE ≠ LOW), it is transformed from a 10-bit trans-

mission character back to the original Data and Special

Character codes. This block uses the 10B/8B Decoder

patterns in Table 20 and Table 21 of this data sheet. Valid data

characters are indicated by a 000b bit-combination on the

RXST[2:0] status bits, and Special Character codes are

indicated by a 001b bit-combination on these same status

outputs. Framing characters, invalid patterns, disparity errors,

and synchronization status are presented as alternate combi-

nations of these status bits.

The 10B/8B Decoder operates in two normal modes, and can

also be bypassed. The operating mode for the Decoder is

controlled by the DECMODE input.

When DECMODE = LOW, the Decoder is bypassed and raw

10-bit characters are passed to the Output Register. In this

mode, the receive Elasticity Buffers are bypassed, and

RXCKSEL must be MID.

When DECMODE = MID (or open), the 10-bit transmission

characters are decoded using Table 20 and Table 21.

Received Special Code characters are decoded using the

Cypress column of Table 21.

When DECMODE = HIGH, the 10-bit transmission characters

are decoded using Table 20 and Table 21. Received Special

Code characters are decoded using the Alternate column of

Table 21.

When RFMODE = MID (open), the Cypress-mode Multi-Byte

Framer is selected. The required detection of multiple framing

characters makes the link much more robust to incorrect

framing due to aliased framing characters in the data stream.

In this mode, the Framer does not adjust the character clock

boundary, but instead aligns the character to the already

recovered character clock. This ensures that the recovered

clock does not contain any significant phase changes or hops

during normal operation or framing, and allows the recovered

clock to be replicated and distributed to other external circuits

or components using PLL-based clock distribution elements.

In this framing mode, the character boundaries are only

Notes:

13. The standard definition of a Comma contains only seven bits. However, since all valid Comma characters within the 8B/10B character set also have the 8th bit

as an inversion of the 7th bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.

14. When Receive BIST is enabled on a channel, the Low-Latency Framer must not be enabled. The BIST sequence contains an aliased K28.5 framing character,

which would cause the Receiver to update its character boundaries incorrectly.

Document #: 38-02031 Rev. *J

Page 17 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Receive BIST Operation

This is automatically generated by the transmitter when its

local RXCKSEL = LOW.

The Receiver interface contains an internal pattern generator

that can be used to validate both device and link operation.

This generator is enabled by the BOE[0] signal as listed in

Table 8 (when the BISTLE latch enable input is HIGH). When

enabled, a register in the Receive channel becomes a pattern

generator and checker by logically converting to a Linear

Feedback Shift Register (LFSR). This LFSR generates a

511-character sequence that includes all Data and Special

Character codes, including the explicit violation symbols. This

provides a predictable yet pseudo-random sequence that can

be matched to an identical LFSR in the attached Transmitter.

If the receive channels are configured for REFCLK clocking

(RXCKSEL = LOW), each pass is preceded by a 16-character

Word Sync Sequence.

When synchronized with the received data stream, the

Receiver checks each character in the Decoder with each

character generated by the LFSR and indicates compare

errors and BIST status at the RXST[2:0] bits of the Output

Register.

When the BISTLE signal is HIGH, if the BOE[0] input is LOW

the BIST generator/checker in the Receive channel is enabled

(and if BOE[1] = LOW the BIST generator in the transmit

channel is enabled). When BISTLE returns LOW, the values

of the BOE[1:0] signals are captured in the BIST Enable Latch.

These values remain in the BIST Enable Latch until BISTLE is

returned high to open the latch again. All captured signals in

the BIST Enable Latch are set HIGH (i.e., BIST is disabled)

following a device reset (TRSTZ is sampled LOW).

When BIST is first recognized as being enabled in the

Receiver, the LFSR is preset to the BIST-loop start-code of

D0.0. This D0.0 character is sent only once per BIST loop. The

status of the BIST progress and any character mismatches is

presented on the RXST[2:0] status outputs.

Code rule violations or running disparity errors that occur as

part of the BIST loop do not cause an error indication.

RXST[2:0] indicates 010b or 100b for one character period per

BIST loop to indicate loop completion. This status can be used

to check test pattern progress. These same status values are

presented when the Decoder is bypassed and BIST is enabled

on the Receive channel.

The BIST state machine requires the characters to be correctly

framed for it to detect the BIST sequence. If the Low-Latency

Framer is enabled (RFMODE = LOW), the Framer will

misalign to an aliased framing character within the BIST

sequence. If the Alternate-mode Multi-Byte Framer is enabled

(RFMODE = HIGH) and the Receiver outputs are clocked

relative to a recovered clock (RXCKSEL = MID), it is

necessary to frame the Receiver before BIST is enabled. If the

Receiver outputs are clocked relative to REFCLK

(RXCKSEL = LOW), the transmitter precedes every 511

character BIST sequence with a 16-character Word Sync

Sequence.

Receive Elasticity Buffer

The receive channel contains an Elasticity Buffer that is

designed to support multiple clocking modes. This buffer

allows data to be read using an Elasticity Buffer read-clock that

is asynchronous in both frequency and phase from the

Elasticity Buffer write clock, or to use a read clock that is

frequency coherent but with uncontrolled phase relative to the

Elasticity Buffer write clock.

The Elasticity Buffer is 10 characters deep, and supports a

12-bit-wide data path. It is capable of supporting a decoded

character, three status bits, and a parity bit for each character

present in the buffer. The write clock for this buffer is always

the recovered clock for the read channel.

The read clock for the Elasticity Buffer can be set to

character-rate REFCLK (RXCKSEL = LOW and DECMODE ≠

LOW). The write clock for the Elasticity Buffer is always

recovered clock.

When RXCKSEL = LOW, the Receive channel is clocked by

REFCLK. The RXCLK± and RXCLKC+ outputs present

buffered and delayed forms of REFCLK. In this mode, the

receive Elasticity Buffer is enabled. For REFCLK clocking, the

Elasticity Buffer must be able to insert K28.5 characters and

delete framing characters as appropriate. The Elasticity Buffer

is bypassed whenever the Decoder is bypassed (DECMODE

= LOW). When the Decoder and Elasticity Buffer are

bypassed, RXCKSELx must be set to MID. When

RXCKSEL = MID (or open), the receive channel Output

Register is clocked by the recovered clock.

The insertion of a K28.5 or deletion of a framing character can

occur at any time. However, the actual timing on these inser-

tions and deletions is controlled in part by the how the trans-

mitter sends its data. Insertion of a K28.5 character can only

occur when the receiver has a framing character in the

Elasticity Buffer. Likewise, to delete a framing character, one

must also be present in the Elasticity Buffer. To prevent an

Elasticity Buffer overflow or underflow in the receive channel,

a minimum density of framing characters must be present in

the received data stream.

The status reported on RXST[2:0] by the BIST state machine

are listed in Table 16. When Receive BIST is enabled, the

same status is reported on the receive status outputs

regardless of the state of DECMODE.

The specific patterns checked by each receiver are described

in detail in the Cypress application note “HOTLink Built-In

Self-test.”

The

sequence

compared

by

the

CYP(V)(W)15G0101DXB is identical to that in the CY7B933

and CY7C924DX, allowing interoperable systems to be built

when used at compatible serial signaling rates.

If the number of invalid characters received ever exceeds the

number of valid characters by 16, the receive BIST state

machine aborts the compare operations and resets the LFSR

to the D0.0 state to look for the start of the BIST sequence

again.

When the receive paths are configured for REFCLK clocking

(RXCKSEL = LOW), each pass must be preceded by a

16-character Word Sync Sequence to allow output buffer

alignment and management of clock frequency variations.

Prior to reception of valid data, at least one Word Sync

Sequence (or at least four framing characters) must be

received to allow the receive Elasticity Buffer to be centered.

The Elasticity Buffer may also be centered by a device reset

operation initiated through the TRSTZ input. However,

following such an event, the CYP(V)(W)15G0101DXB will

normally require a framing event before it will correctly decode

characters.

Document #: 38-02031 Rev. *J

Page 18 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Receive Modes

by sequencing the appropriate values on the BOE[1:0] inputs

while the OELE and RXLE signals are raised and lowered. For

systems that do not require dynamic control of power, or want

the part to power up in a fixed configuration, it is also possible

to strap the RXLE and OELE control signals HIGH to perma-

nently enable their associated latches. Connection of the

associated BOE[1:0] signals to a stable HIGH will then enable

the Transmit and Receive channels as soon as the TRSTZ

signal is deasserted.

The operating mode of the receive path is set through the

RXMODE input. The ‘Reserved for test’ setting (RXMODE =

M) is not allowed, even if the receiver is not being used, as it

will stop normal function of the device. When the decoder is

disabled, the RXMODE setting is ignored as long as it is not a

test mode. These modes determine the RXST status

reporting. The different receive modes are listed in Table 12.

Table 12. Receive Operating Modes

RX Mode

Output Bus

The receive channel presents a 12-signal output bus

Mode

RXST Status Reporting

consisting of

Number

RXMODE

• an eight-bit data bus

• a three-bit status bus

• a parity bit.

0

1

2

L

M

H

Status A

Reserved for test

Status B

The bit assignments of the Data and Status are dependent on

Power Control

the setting of DECMODE. This mapping is shown in Table 13.

Table 13. Output Register Bit Assignments^[15]

The CYP(V)(W)15G0101DXB supports user control of the

powered up or down state of the Transmit and Receive

channel. The Receive channel is controlled by the RXLE

signal and the values present on the BOE[1:0] bus.

The Transmit channel is controlled by the OELE signal and the

values present on the BOE[1:0] bus. If either the Transmit or

the Receive channel is not used, then powering down the

unused channel will save power and reduce system heat

generation. Controlling system power dissipation will improve

the system performance.

DECMODE = MID

Signal Name

RXST[2] (LSB)

RXST[1]

RXST[0]

RXD[0]

DECMODE = LOW

COMDET

DOUT[0]

or HIGH

RXST[2]

RXST[1]

RXST[0]

RXD[0]

RXD[1]

RXD[2]

RXD[3]

RXD[4]

RXD[5]

RXD[6]

RXD[7]

DOUT[1]

DOUT[2]

RXD[1]

DOUT[3]

RXD[2]

DOUT[4]

Receive Channel

RXD[3]

DOUT[5]

When RXLE = HIGH, the signal on the BOE[0] input directly

controls the power enable for the receive PLL and the analog

circuit. When BOE[0] = HIGH, the Receive channel and its

analog circuits are active. When BOE[0] = LOW, the Receive

channel and its analog circuits are powered down. When

RXLE returns LOW, the values present on the BOE[1:0] inputs

are latched in the Receive Channel Enable Latch. When a

disabled receive channel is re-enabled, the status of the LFI

output and data on the parallel outputs for the Receive channel

may be indeterminate for up to 2 ms.

RXD[4]

DOUT[6]

RXD[5]

DOUT[7]

RXD[6]

DOUT[8]

RXD[7] (MSB)

DOUT[9]

When the 10B/8B Decoder is bypassed (DECMODE = LOW),

the framed 10-bit character is presented to the receiver Output

Register, along with a status output (COMDET) indicating if the

character in the Output Register is one of the selected framing

characters. The bit usage and mapping of the external signals

to the raw 10B transmission character is shown in Table 14.

Transmit Channel

Table 14. Decoder Bypass Mode (DECMODE = LOW)

When OELE = HIGH, the signals on the BOE[1:0] inputs

directly control the power enables for the Serial Drivers. When

a BOE[1:0] input is HIGH, the associated Serial Driver is

enabled. When a BOE[1:0] input is LOW, the associated Serial

Driver is disabled. When both Serial Drivers are powered

down, the logic in the entire transmit channel is also powered

down. When OELE returns LOW, the values present on the

BOE[1:0] inputs are latched in the Output Enable Latch.

Signal Name

RXST[2] (LSB)

RXST[1]

RXST[0]

RXD[0]

Bus Weight

COMDET

10B Name

2⁰

2¹

2²

2³

2⁴

2⁵

2⁶

2⁷

2⁸

2⁹

a

b

c

d

e

i

RXD[1]

RXD[2]

RXD[3]

RXD[4]

RXD[5]

RXD[6]

Device Reset State

When the CYP(V)(W)15G0101DXB is reset by assertion of

TRSTZ, both the Transmit Enable and Receive Enable

Latches are cleared, and the BIST Enable Latch is preset. In

this state, the Transmit and Receive channels are disabled,

and BIST is disabled.

f

g

h

j

Following a device reset, it is necessary to enable the transmit

RXD[7] (MSB)

and receive channels for normal operation. This can be done

Note:

15. The RXOP output is also driven from the Output Register, but its interpretation is under the separate control of PARCTL.

Document #: 38-02031 Rev. *J

Page 19 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

The COMDET output is HIGH when the character in the

Output Register contains the selected framing character at the

proper character boundary, and LOW for all other bit combina-

tions.

Table 15. Output Register Parity Generation

Receive Parity Generate Mode (PARCTL)

MID

When the Low-Latency Framer and half-rate receive port

clocking is also enabled (RFMODE = LOW, RXRATE = HIGH,

and RXCKSEL = MID), the Framer will stretch the recovered

clock to the nearest 20-bit boundary such that the rising edge

of RXCLK+ occurs when COMDET = HIGH in the Output

Register.

When the Cypress or Alternate-mode Framer is enabled and

half-rate receive port clocking is also enabled (RFMODE ≠

LOW and RXRATE = HIGH), the output clock is not modified

when framing is detected, but a single pipeline stage may be

added or subtracted from the data stream by the Framer logic

such that the rising edge of RXCLK+ occurs when

COMDET = HIGH in the Output Register. This adjustment

only occurs when the Framer is enabled (RFEN = HIGH).

When the Framer is disabled, the clock boundaries are not

adjusted, and COMDET may be asserted during the rising

edge of RXCLK– (if an odd number of characters were

received following the initial framing).

Signal

Name

DECMODE

LOW^[16]

= LOW

≠ LOW

HIGH

X^[17]

X

RXST[2]

RXST[1]

RXST[0]

RXD[0]

RXD[1]

RXD[2]

RXD[3]

RXD[4]

RXD[5]

RXD[6]

RXD[7]

X

When PARCTL = HIGH, ODD parity is generated for the

TXD[7:0] and the RXST[2:0] status bits.

Parity Generation

In addition to the eleven data and status bits that are

presented, an RXOP parity output is also available. This

allows the CYP(V)(W)15G0101DXB to support ODD parity

generation. To handle a wide range of system environments,

the CYP(V)(W)15G0101DXB supports different forms of parity

generation (in addition to no parity). When the Decoder is

enabled (DECMODE ≠ LOW), parity can be generated on

Receive Status Bits

When the 10B/8B Decoder is enabled (DECMODE ≠ LOW),

each character presented at the Output Register includes

three associated status bits. These bits are used to identify

• if the contents of the data bus are valid

• the type of character present

• the state of receive BIST operations (regardless of the state

of DECMODE)

• character violations.

These conditions normally overlap; e.g., a valid data character

received with incorrect running disparity is not reported as a

valid data character. It is instead reported as a Decoder

violation of some specific type. This implies a hierarchy or

priority level to the various status bit combinations. The

hierarchy and value of each status is listed in Table 16.

Within these status decodes, there are three forms of status

reporting. The two normal or data status reporting modes

(Type A and Type B) are selectable through the RXMODE

input. These status types allow compatibility with legacy

systems, while allowing full reporting in new systems. The third

status type is used for reporting receive BIST status and

progress.

• the RXD[7:0] character

• the RXD[7:0] character and RXST[2:0] status.

When the Decoder is bypassed (DECMODE = LOW), parity

can be generated on

• the RXD[7:0] and RXST[1:0] bits

• the RXD[7:0] and RXST[2:0] bits.

These modes differ in the number of bits which are included in

the parity calculation. For all cases, only ODD parity is

provided which ensures that at least one bit of the data bus is

always a logic-1. Those bits covered by parity generation are

listed in Table 15.

Parity generation is enabled through the 3-level select

PARCTL input. When PARCTL = LOW, parity checking is

disabled, and the RXOP output is disabled (High-Z).

When PARCTL = MID (open) and the Decoder is enabled

(DECMODE ≠ LOW), ODD parity is generated for the received

and decoded character in the RXD[7:0] signals and is

presented on the RXOP output.

BIST Status State Machine

When the receive path is enabled to look for and compare the

received data stream with the BIST pattern, the RXST[2:0] bits

identify the present state of the BIST compare operation.

When PARCTL = MID (open) and the Decoder is bypassed

(DECMODE = LOW), ODD parity is generated for the received

and decoded character in the RXD[7:0] and RXST[1:0] bit

positions.

Notes:

16. Receive path parity output driver (RXOP) is disabled (High-Z) when PARCTL = LOW.

17. When the Decoder is bypassed (DECMODE = LOW) and BIST is not enabled (Receive BIST Latch output is HIGH), RXST[2] is driven to a logic-0, except when

the character in the output buffer is a framing character.

Document #: 38-02031 Rev. *J

Page 20 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

The BIST state machine has multiple states, as shown in

Figure 2 and Table 16. When the receive PLL detects an

out-of-lock condition, the BIST state is forced to the

Start-of-BIST state, regardless of the present state of the BIST

state machine. If the number of detected errors ever exceeds

the number of valid matches by greater than 16, the state

machine is forced to the WAIT_FOR_BIST state where it

monitors the interface for the first character (D0.0) of the next

BIST sequence. Also, if the Elasticity Buffer ever hits and

overflow/underflow condition, the status is forced to the

BIST_START until the buffer is re-centered (approximately

nine character periods).

JTAG Support

The CYP(V)(W)15G0101DXB contains a JTAG port to allow

system level diagnosis of device interconnect. Of the available

JTAG modes, only boundary scan is supported. This capability

is present only on the LVTTL inputs, LVTTL outputs and the

REFCLK± clock input. The high-speed serial inputs and

outputs are not part of the JTAG test chain.

JTAG ID

The JTAG device ID for the CYP(V)(W)15G0101DXB is

“1C804069”x.

To ensure compatibility between the source and destination

systems when operating in BIST, the sending and receiving

ends of the BIST sequence must use the same clock setup

(RXCKSEL = MID or RXCKSEL = LOW).

3-Level Select Inputs

Each 3-Level select input reports as two bits in the scan

register. These bits report the LOW, MID, and HIGH state of

the associated input as 00, 10, and 11, respectively.

Table 16. Receive Character Status Bits

Description

RXST[2: Priori-

Receive BIST Status

0]

ty

Type-A Status

Type-B Status

(Receive BIST = Enabled)

000

7

Normal Character Received. The valid Data character on the output bus BIST Data Compare.

meets all the formatting requirements of Data characters listed in Table 20. Character compared correctly

001

010

7

2

Special Code Detected. The valid special character on the output bus

BIST Command Compare.

meets all the formatting requirements of the Special Code characters listed Character compared correctly

in Table 21, but is not the presently selected framing character or a Decoder

violation indication.

Receive Elasticity Buffer

Underrun/Overrun Error. The

receive buffer was not able to

add/drop a K28.5 or framing

character.

RESERVED

BIST Last Good. Last

Character of BIST sequence

detected and valid.

011

100

101

5

4

1

Framing Character Detected. This indicates that a character matching the RESERVED

patterns identified as a framing character (as selected by FRAMCHAR) was

detected. The decoded value of this character is present on the output bus.

Codeword Violation. The character on the output bus is a C0.7. This

indicates that the received character cannot be decoded into any valid

character.

BIST Last Bad. Last Character

of BIST sequence detected

invalid.

PLL Out of Lock. This indicates a PLL Out of Lock condition.

BIST Start. Receive BIST is

enabled on this channel, but

character compares have not

yet commenced. This also

indicates a PLL Out of Lock

condition, and Elasticity Buffer

overflow/underflow conditions.

110

111

6

3

Running Disparity Error. The character on the output bus is a C4.7, C1.7, BIST Error. While comparing

or C2.7.

characters, a mismatch was

found in one or more of the

decoded character bits.

RESERVED

BIST Wait. The receiver is

comparing characters. but has

not yet found the start of BIST

character to enable the LFSR.

Document #: 38-02031 Rev. *J

Page 21 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Monitor Data

Received

Receive BIST

Detected LOW

RXST =

RX PLL

BIST_START (101)

Out of Lock

RXST =

BIST_START (101)

BIST_WAIT (111)

Elasticity

Buffer Error

Yes

Start of

No

BIST Detected

No

Yes, RXST = BIST_DATA_COMPARE (000)

OR BIST_COMMAND_COMPARE(001)

Compare

Next Character

RXST =

Mismatch

BIST_COMMAND_COMPARE (001)

Match

Command

Data or

Auto-Abort

Command

Condition

Yes

RXST =

BIST_DATA_COMPARE (000)

No

Data

End-of-BIST

State

End-of-BIST

State

No

Yes, RXST =

BIST_LAST_BAD (100)

BIST_LAST_GOOD (010)

No, RXST =

BIST_ERROR (110)

Figure 2. Receive BIST State Machine

Document #: 38-02031 Rev. *J

Page 22 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Static Discharge Voltage.......................................... > 2000 V

Maximum Ratings

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired. For user guide-

Latch-up Current.....................................................> 200 mA

lines, not tested.)

Power-up Requirements

Storage Temperature ..................................–65°C to +150°C

The CYP(V)(W)15G0101DXB requires one power-supply. The

voltage on any input or I/O pin cannot exceed the power pin

during power-up.

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential............... –0.5V to +3.8V

Operating Range

DC Voltage Applied to LVTTL Outputs

in High-Z State .......................................–0.5V to V_CC+ 0.5V

Range

Commercial

Industrial

Ambient Temperature

0°C to +70°C

V_CC

+3.3V ± 5%

Output Current into LVTTL Outputs (LOW)..................60 mA

DC Input Voltage....................................–0.5V to V_CC+ 0.5V

–40°C to +85°C

DC Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min.

Max.

Unit

LVTTL-compatible Outputs

V_OHT

V_OLT

I_OST

I_OZL

Output HIGH Voltage

Output LOW Voltage

Output Short Circuit Current

High-Z Output Leakage Current

I_OH= − 4 mA, V_CC= Min.

I_OL= 4 mA, V_CC= Min.

V_OUT= 0V^[18]

2.4

0

–20

V_CC

0.4

–100

20

V

mA

µA

LVTTL-compatible Inputs

V_IHT

V_ILT

I_IHT

Input HIGH Voltage

Input LOW Voltage

Input HIGH Current

2.0

–0.5

V_CC+ 0.3

0.8

V

REFCLK Input, V_IN= V_CC

Other Inputs, V_IN= V_CC

REFCLK Input, V_IN= 0.0V

Other Inputs, V_IN= 0.0V

V_IN= V_CC

1.5

+40

–1.5

-40

+200

mA

µA

mA

µA

I_ILT

Input LOW Current

I_IHPDT

I_ILPUT

Input HIGH Current with internal

pull-down

Input LOW Current with internal pull-up

V_IN= 0.0V

–200

µA

LVDIFF Inputs: REFCLK±

[19]

V_DIFF

Input Differential Voltage

400

1.2

0.0

1.0

V_CC

V_CC/ 2

V_CC– 1.2

mV

V

V_IHHP

V_ILLP

V_COMREF

Highest Input HIGH Voltage

Lowest Input LOW voltage

Common Mode Range

[20]

V

3-Level Inputs

V_IHH

V_IMM

V_ILL

I_IHH

I_IMM

I_ILL

3-Level Input HIGH Voltage

Min. ≤ V_CC≤ Max.

V_IN= V_CC

V_IN= V_CC/2

V_IN= GND

0.87 * V_CC

0.47 * V_CC0.53 * V_CC

V_CC

V

µA

3-Level Input MID Voltage

3-Level Input LOW Voltage

Input HIGH Current

Input MID Current

Input LOW Current

0.0

0.13 * V_CC

200

–50

50

–200

Differential CML Serial Outputs: OUT1±, OUT2±

V_OHC

Output HIGH Voltage

100Ω differential load

150Ω differential load

V_CC– 0.5

V

_CC− 0.2

V

(V_CCreferenced)

V_CC− 0.5

V_CC− 0.2

Notes:

18. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.

19. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when

the true (+) input is more positive than the complement (−) input. A logic-0 exists when the complement (−) input is more positive than true (+) input.

20. The common mode range defines the allowable range of REFCLK+ and REFCLK− when REFCLK+ = REFCLK−. This marks the zero-crossing between the

true and complement inputs as the signal switches between a logic-1 and a logic-0.

Document #: 38-02031 Rev. *J

Page 23 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

DC Electrical Characteristics Over the Operating Range (continued)

Parameter Description Test Conditions

V_OLC100Ω differential load

Min.

_CC− 1.4

Max.

_CC− 0.7

900

Unit

V

mV

Output LOW Voltage

V

(V_CCreferenced)

150Ω differential load

100Ω differential load

150Ω differential load

V_CC− 1.4

V_ODIF

Output Differential Voltage

450

560

|(OUT+) − (OUT−)|

1000

Differential Serial Line Receiver Inputs: IN1±, IN2±

[19]

V_DIFFS

V_IHE

V_ILE

I_IHE

Input Differential Voltage |(IN+) − (IN−)|

Highest Input HIGH Voltage

Lowest Input LOW Voltage

Input HIGH Current

100

V_CC– 2.0

–700

1200

V_CC

mV

V

µA

V

V_IN= V_IHEMax.

V_IN= V_ILEMin.

1350

I_ILE

V_COM

Input LOW Current

Common Mode Input Range

[21, 22]

V_CC− 1.95 V_CC− 0.05

Power Supply

Typ. ^[24]

390

Max. ^[23]

500

510

500

510

Unit

mA

I_CC

Power Supply Current

Commercial

Industrial

Commercial

Industrial

REFCLK= Max.

I_CC

Power Supply Current

REFCLK= 125 MHz

390

AC Test Loads and Waveforms

3.3V

R1

R2

R_L= 100Ω

R

L

R1 = 590Ω

R2 = 435Ω

C_L

(b) CML Output Test Load^[25]

C_L≤ 7 pF

(Includes fixture and

probe capacitance)

V_IHE

(a) LVTTL Output Test Load ^[25]

3.0V

V_IHE

V_ILE

80%

20%

2.0V

0.8V

2.0V

V_th= 1.4V

GND

V_th= 1.4V

V_ILE

≤ 270 ps

0.8V

(d) CML/LVPECL Input Test Waveform

≤ 1 ns

[26]

(c) LVTTL Input Test Waveform

CYP(V)(W)15G0101DXB AC Characteristics Over the Operating Range

Parameter

Description

Min.

Max.

Unit

Transmitter LVTTL Switching Characteristics

f_TS

TXCLK Clock Frequency

19.5

6.66^[28]

2.2

0.2

150^[27]

51.28

MHz

ns

t_TXCLK

t_TXCLKH

t_TXCLKL

t_TXCLKR

Notes:

TXCLK Period

[29]

TXCLK HIGH Time

TXCLK LOW Time

TXCLK Rise Time

[29]

[29, 30, 31]

1.7

21. The common mode range defines the allowable range of INPUT+ and INPUT− when INPUT+ = INPUT−. This marks the zero-crossing between the true and

complement inputs as the signal switches between a logic-1 and a logic-0.

22. Not applicable for AC-coupled interfaces. For AC-coupled interfaces, V

requirement still needs to be satisfied.

DIFFS

23. Maximum I is measured with V_CC= MAX, with all Serial Drivers enabled, parallel outputs unloaded, sending a alternating 01 pattern to the Serial Input Receiver.

CC

24. Typical I is measured under similar conditions except with V

= 3.3V, T = 25°C, parallel outputs unloaded, RXCKSEL = MID, and with one Serial Line

A

CC

Driver sending a continuous alternating 01 pattern to the Serial Input Receiver.

25. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only. 5pF differential load reflects tester capacitance,

and is recommended at low data rates only.

26. The LVTTL switching threshold is 1.4V. All timing references are made relative to the point where the signal edges crosses this threshold voltage.

27. This parameter is 154 MHz for CYW15G0101DXB.

28. This parameter is 6.49 ns for CYW15G0101DXB.

29. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.

30. The ratio of rise time to falling time must not vary by greater than 2:1.

31. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.

Document #: 38-02031 Rev. *J

Page 24 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

CYP(V)(W)15G0101DXB AC Characteristics Over the Operating Range (continued)

Parameter

Description

Min.

0.2

Max.

1.7

Unit

ns

[29, 30, 31]

t_TXCLKF

TXCLK Fall Time

t_TXDS

t_TXDH

f_TOS

t_TXCLKO

t_TXCLKOD+

t_TXCLKOD–

Transmit Data Set-Up Time to TXCLK↑ (TXCKSEL ≠ LOW)

Transmit Data Hold Time from TXCLK↑ (TXCKSEL ≠ LOW)

TXCLKO Clock Frequency = 1x or 2x REFCLK Frequency

TXCLKO Period

TXCLKO+ Duty Cycle with 60% HIGH time

TXCLKO– Duty Cycle with 40% HIGH time

1.7

0.8

19.5

6.66^[28]

–1.0

–0.5

ns

MHz

ns

150^[27]

51.28

+0.5

+1.0

ns

Receiver LVTTL Switching Characteristics

f_RS

RXCLK Clock Output Frequency

9.75

6.66^[28]

2.33 ^[29]

5.66

150^[27]

102.56

26.64

52.28

26.64

52.28

+1.0

MHz

ns

t_RXCLKP

t_RXCLKH

RXCLK Period

RXCLK HIGH Time (RXRATE = LOW)

RXCLK HIGH Time (RXRATE = HIGH)

RXCLK LOW Time (RXRATE = LOW)

RXCLK LOW Time (RXRATE = HIGH)

RXCLK Duty Cycle centered at 50%

RXCLK Rise Time

t_RXCLKL

t_RXCLKD

2.33 ^[29]

5.66

–1.0

0.3

5UI – 1.5

5UI – 1.0

5UI – 1.8

[29]

t_RXCLKR

t_RXCLKF

t_RXDV–

1.2

[29]

RXCLK Fall Time

[32]

Status and Data Valid Time to RXCLK (RXCKSEL = MID)

Status and Data Valid Time to RXCLK (HALF RATE RECOVERED CLOCK)

Status and Data Valid Time From RXCLK (RXCKSEL = MID)

[32]

t_RXDV+

Status and Data Valid Time From RXCLK (HALF RATE RECOVERED CLOCK) 5UI – 2.3

REFCLK Switching Characteristics Over the Operating Range

f_REF

REFCLK Clock Frequency

19.5

6.6^[28]

5.9

150^[27]

51.28

MHz

ns

%

ns

ppm

t_REFCLK

t_REFH

REFCLK Period

REFCLK HIGH Time (TXRATE = HIGH)

REFCLK HIGH Time (TXRATE = LOW)

2.9^[29]

5.9

t_REFL

REFCLK LOW Time (TXRATE = HIGH)

REFCLK LOW Time (TXRATE = LOW)

REFCLK Duty Cycle

REFCLK Rise Time (20% – 80%)

REFCLK Fall Time (20% – 80%)

2.9^[29]

30

[33]

t_REFD

t_REFR

t_REFF

70

2

[29, 30, 31]

t_TREFDS

t_TREFDH

t_RREFDA

t_RREFDV

t_REFDV–

t_REFDV+

Transmit Data Setup Time to REFCLK (TXCKSEL = LOW)

Transmit Data Hold Time from REFCLK (TXCKSEL = LOW)

Receive Data Access Time from REFCLK (RXCKSEL = LOW)

Receive Data Valid Time from REFCLK (RXCKSEL = LOW)

Received Data Valid Time to RXCLK (RXCKSEL = LOW)

Received Data Valid Time from RXCLK (RXCKSEL = LOW)

Received Data Valid Time to RXCLKC (RXCKSEL = LOW)

Received Data Valid Time from RXCLKC (RXCKSEL = LOW)

REFCLK Frequency Referenced to Extracted Received Clock Frequency

1.7

0.8

[34]

9.5

2.5

10UI – 4.7

0.5

10UI – 4.3

–0.2

t_REFCDV–

t_REFCDV+

[10, 29]

t_REFRX

Notes:

–1500

+1500

32. Parallel data output specifications are only valid if all inputs or outputs are loaded with similar DC and AC loads.

33. The duty cycle specification is a simultaneous condition with the t

cannot be as large as 30%–70%.

and t

parameters. This means that at faster character rates the REFCLK duty cycle

REFL

REFH

34. Since this timing parameter is greater than the minimum time period of REFCLK it sets an upper limit to the frequency in which REFCLKx can be used to clock

the receive data out of the output register. For predictable timing, users can use this parameter only if REFCLK period is greater than sum of t

and set-up

RREFDA

time of the upstream device. When this condition is not true, RXCLKC± or RXCLKA± (a buffered or delayed version of REFCLK when RXCKSELx = LOW) could

be used to clock the receive data out of the device.

Document #: 38-02031 Rev. *J

Page 25 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

CYP(V)(W)15G0101DXB AC Characteristics Over the Operating Range (continued)

Parameter

Description

Min.

Max.

Unit

Transmit Serial Outputs and TX PLL Characteristics

t_B

t_RISE

Bit Time

5100

60

100

180

60

666^[35]

270

500

1000

270

500

1000

25

ps

us

[29]

CML Output Rise Time 20%–80% (CML Test Load)

SPDSEL = HIGH

SPDSEL = MID

SPDSEL = LOW

SPDSEL = HIGH

SPDSEL = MID

SPDSEL = LOW

IEEE 802.3z^[39]

[29]

t_FALL

CML Output Fall Time 80%–20% (CML Test Load)

100

180

[29, 36, 38]

[29, 37, 38]

t_DJ

t_RJ

Deterministic Jitter (peak-peak)

Random Jitter (σ)

11

200

t_TXLOCK

Transmit PLL lock to REFCLK

Receive Serial Inputs and CDR PLL Characteristics

t_RXLOCK

Receive PLL lock to input data stream (cold start)

Receive PLL lock to input data stream

Receive PLL Unlock Rate

Total Jitter Tolerance

Deterministic Jitter Tolerance

376K

46

UI^[40]

UI

ps

t_RXUNLOCK

t_JTOL

IEEE 802.3z^[39]

600

370

[38]

t_DJTOL

Capacitance^[29]

Parameter

C_INTTL

Description

TTL Input Capacitance

Test Conditions

T_A= 25°C, f₀= 1 MHz, V_CC= 3.3V

Max.

7

Unit

pF

C_INPECL

PECL input Capacitance

T_A= 25°C, f₀= 1 MHz, V_CC= 3.3V

4

pF

Notes:

35. This parameter is 649 ps for CYW15G0101DXB.

36. While sending continuous K28.5s, outputs loaded to a balanced 100Ω load, measured at the cross point of the differential outputs over the operating range.

37. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating

range.

38. Total jitter is calculated at an assumed BER of 1E − 12. Hence: Total Jitter (t ) = (t * 14) + t

.

DJ

J

RJ

39. Also meets all Jitter Generation and Jitter Tolerance requirements as specified by SMPTE 259M, SMPTE 292M, OBSAI RP3, CPRI, ESCON, FICON, Fibre

Channel and DVB-ASI.

40. Receiver UI (Unit Interval) is calculated as 1/(f

* 20) (when RXRATE = HIGH) or 1/(f

* 10) (when RXRATE = LOW) if no data is being received, or

REF

1/(f

* 20)(when RXRATE = HIGH) or 1/(f

* 10) (whenRXRATE = LOW) of the remote transmitter if data is being received. In an operating link this is equivalent to t

REF

R

E

F

B

Document #: 38-02031 Rev. *J

Page 26 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Switching Waveforms for the HOTLink II Transmitter

Transmit Interface

Write Timing

t_TXCLK

TXCKSEL ≠ LOW

t_TXCLKH

t

TXCLKL

TXCLK

t

TXDS

TXD[7:0],

TXCT[1:0],

TXOP,

SCSEL

t

TXDH

Transmit Interface

Write Timing

t_REFCLK

TXCKSEL = LOW

TXRATE = LOW

t_REFH

t

REFL

REFCLK

t

TREFDS

TXD[7:0],

TXCT[1:0],

TXOP,

SCSEL

t

TREFDH

Transmit Interface

Write Timing

t_REFCLK

TXCKSEL = LOW

TXRATE = HIGH

t_REFH

t

REFL

Note 41

REFCLK

t

TREFDS

TXD[7:0],

TXCT[1:0],

TXOP,

SCSEL

t

TREFDH

t

Transmit Interface

TXCLKO Timing

TXCKSEL = LOW

TXRATE = HIGH

REFCLK

t

t_REFL

REFH

REFCLK

t

TXCLKO

Note 43

t_TXCLKOD+

t

TXCLKOD

–

Note 42

TXCLKO

Notes:

41. When REFCLK is configured for half-rate operation (TXRATE = HIGH) and data is captured using REFCLK instead of TXCLK clock (TXCKSEL = LOW), data

is captured using both the rising and falling edges of REFCLK.

42. The TXCLKO output is at twice the rate of REFCLK when TXRATE = HIGH and same rate as REFCLK when TXRATE = LOW. TXCLKO does not follow the

duty cycle of REFCLK.

43. The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input.

Document #: 38-02031 Rev. *J

Page 27 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Switching Waveforms for the HOTLink II Transmitter (continued)

Transmit Interface

t_REFCLK

TXCLKO Timing

t_REFH

t

TXCKSEL = LOW

REFL

TXRATE = LOW

Note ⁴²

REFCLK

t_TXCLKO

t_TXCLKOD+

Note ⁴³

t

TXCLKOD

–

TXCLKO

Switching Waveforms for the HOTLink II Receiver

Receive Interface

t_REFCLK

Read Timing

t_REFH

t

REFL

RXCKSEL = LOW

TXRATE = LOW

REFCLK

t

RREFDV

RREFDA

RXD[7:0],

RXST[2:0],

RXOP

t

REFDV+

t

REFDV–

REFCDV+

t

REFCDV

–

Note 44

RXCLK

RXCLKC+

Receive Interface

Read Timing

t_REFCLK

t_REFH

t

REFL

RXCKSEL = LOW

TXRATE = HIGH

REFCLK

t

RREFDA

RREFDV

RREFDA

t

RREFDV

RXD[7:0],

RXST[2:0],

RXOP

t

REFDV+

t

REFDV

–

t

REFCDV+

t

REFCDV

–

RXCLK

Note ⁴⁵

Note 44

RXCLKC+

Notes:

44. RXCLK and RXCLK+ are delayed versions of REFCLK when RXCKSEL = LOW, and are different in phase from each other.

45. When operated with a half-rate REFCLK, the setup and hold specifications for data relative to RXCLK are relative to both rising and falling edges of the clock output

Document #: 38-02031 Rev. *J

Page 28 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Switching Waveforms for the HOTLink II Receiver (continued)

Receive Interface

t_RXCLKP

Read Timing

RXCKSEL = MID

RXRATE = LOW

t_RXCLKH

t

RXCLKL

RXCLK+

RXCLK–

t

RXDV

–

RXD[7:0],

RXST[2:0],

RXOP

t

RXDV+

Receive Interface

Read Timing

t_RXCLKP

RXCKSEL = MID

RXRATE = HIGH

t_RXCLKH

t

RXCLKL

RXCLK+

RXCLK–

t

RXDV

–

RXD[7:0],

RXST[2:0],

RXOP

t

RXDV+

Document #: 38-02031 Rev. *J

Page 29 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Table 17. Package Coordinate Signal Allocation

Ball

ID

Signal Name

VCC

Signal Type

POWER

CML IN

POWER

CML OUT

3-LEVEL SEL

CML IN

POWER

CML OUT

POWER

CML IN

LVTTL 3-S OUT

CML OUT

LVTTL IN PD

3-LEVEL SEL

CML IN

NO CONNECT

CML OUT

ID

Signal Name

GND

Signal Type

GROUND

Signal Name

TXCLKO+

TXCLKO–

RXD[0]

RXD[2]

RXD[6]

LFI

Signal Type

LVTTL OUT

LVTTL IN

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

F1

F2

F3

F4

F5

F6

F7

F8

F9

G9

G10

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

IN2+

VCC

OUT2–

RXMODE

TXMODE[1]

IN1+

VCC

OUT1–

VCC

IN2–

GND

TMS

TRSTZ

TDI

BISTLE

DECMODE

OELE

GROUND

LVTTL IN PU

3-LEVEL SEL

LVTTL IN PU

GROUND

LVTTL IN PD

3-LEVEL SEL

LVTTL OUT

GROUND

LVTTL OUT

PECL IN

TXCT[1]

TXD[6]

TXD[3]

TXCLK

TXRST

#NC

LVTTL IN

GND

LVTTL IN PD

LVTTL IN PU

NO CONNECT

POWER

LVTTL OUT

LVTTL IN

TDO

VCC

OUT2+

TXRATE

TXMODE[0]

IN1–

#NC

OUT1+

VCC

TCLK

RXD[3]

RXD[7]

RXCLK–

TXCT[0]

TXD[5]

TXD[2]

TXD[0]

#NC

VCC

RXD[4]

VCC

RXCLK+

TXD[7]

TXD[4]

TXD[1]

VCC

RXCKSEL

TXCKSEL

RXST[2]

RXST[1]

RXST[0]

GND

LVTTL IN

POWER

RFEN

LPEN

RXLE

LVTTL IN PD

LVTTL IN PU

LVTTL 3-S OUT

LVTTL IN PD

3-LEVEL SEL

LVTTL IN

GND

NO CONNECT

POWER

LVTTL OUT

POWER

LVTTL OUT

LVTTL IN

POWER

RXCLKC+

RXRATE

SDASEL

SPDSEL

PARCTL

RFMODE

INSEL

BOE[0]

BOE[1]

FRAMCHAR

GND

TXPER

REFCLK–

REFCLK+

RXOP

RXD[1]

RXD[5]

GND

TXOP

F10

G1

G2

G3

G4

G5

G6

G7

G8

PECL IN

LVTTL 3-S OUT

LVTTL OUT

GROUND

LVTTL IN PU

3-LEVEL SEL

GROUND

SCSEL

VCC

LVTTL IN PD

POWER

Document #: 38-02031 Rev. *J

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CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

the binary number composed of the bits E, D, C, B, and A in

that order, and the y is the decimal value of the binary number

composed of the bits H, G, and F in that order. When c is set

to K, xx and y are derived by comparing the encoded bit

patterns of the Special Character to those patterns derived

from encoded Valid Data bytes and selecting the names of the

patterns most similar to the encoded bit patterns of the Special

Character.

Under the above conventions, the Transmission Character

used for the examples above, is referred to by the name D5.2.

The Special Character K29.7 is so named because the first six

bits (abcdei) of this character make up a bit pattern similar to

that resulting from the encoding of the unencoded 11101

pattern (29), and because the second four bits (fghj) make up

a bit pattern similar to that resulting from the encoding of the

unencoded 111 pattern (7). This definition of the 10-bit Trans-

mission Code is based on the following references.

A.X. Widmer and P.A. Franaszek. “A DC-Balanced, Parti-

tioned-Block, 8B/10B Transmission Code” IBM Journal of

Research and Development, 27, No. 5: 440-451 (September,

1983).

U.S. Patent 4,486,739. Peter A. Franaszek and Albert X.

Widmer. “Byte-Oriented DC Balanced (0.4) 8B/10B Parti-

tioned Block Transmission Code” (December 4, 1984).

X3.230 Codes and Notation Conventions

Information to be transmitted over a serial link is encoded eight

bits at a time into a 10-bit Transmission Character and then

sent serially, bit by bit. Information received over a serial link

is collected ten bits at a time, and those Transmission

Characters that are used for data characters are decoded into

the correct eight-bit codes. The 10-bit Transmission Code

supports all 256 eight-bit combinations. Some of the remaining

Transmission Characters (Special Characters) are used for

functions other than data transmission.

The primary use of a Transmission Code is to improve the

transmission characteristics of a serial link. The encoding

defined by the Transmission Code ensures that sufficient

transitions are present in the serial bit stream to make clock

recovery possible at the Receiver. Such encoding also greatly

increases the likelihood of detecting any single or multiple bit

errors that may occur during transmission and reception of

information. In addition, some Special Characters of the Trans-

mission Code selected by Fibre Channel Standard contain a

distinct and easily recognizable bit pattern that assists the

receiver in achieving character alignment on the incoming bit

stream.

Notation Conventions

The documentation for the 8B/10B Transmission Code uses

letter notation for the bits in an eight-bit byte. Fibre Channel

Standard notation uses a bit notation of A, B, C, D, E, F, G, H

for the eight-bit byte for the raw eight-bit data, and the letters

a, b, c, d, e, i, f, g, h, j for encoded 10-bit data. There is a

correspondence between bit A and bit a, B and b, C and c, D

and d, E and e, F and f, G and g, and H and h. Bits i and j are

derived, respectively, from (A,B,C,D,E) and (F,G,H).

Fibre Channel Physical and Signaling Interface (ANS

X3.230-1994 ANSI FC-PH Standard).

IBM Enterprise Systems Architecture/390 ESCON I/O

Interface (document number SA22-7202).

8B/10B Transmission Code

The following information describes how the tables are used

for both generating valid Transmission Characters (encoding)

and checking the validity of received Transmission Characters

(decoding). It also specifies the ordering rules to be followed

when transmitting the bits within a character and the

characters within any higher-level constructs specified by a

standard.

The bit labeled A in the description of the 8B/10B Transmission

Code corresponds to bit 0 in the numbering scheme of the

FC-2 specification, B corresponds to bit 1, as shown below.

FC-2 bit designation—

HOTLink D/Q designation— 7

8B/10B bit designation—

7

6

5

4

E

3

2

1

B

0

A

6

5

3

2

H

G F

D

C

Transmission Order

To clarify this correspondence, the following example shows

the conversion from an FC-2 Valid Data Byte to a Transmission

Character.

Within the definition of the 8B/10B Transmission Code, the bit

positions of the Transmission Characters are labeled a, b, c,

d, e, i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c,

d, e, i, f, g, h, and j in that order.

FC-2 45H

Bits: 7654 3210

0100 0101

Note that bit i is transmitted between bit e and bit f, rather than

in alphabetical order.

Converted to 8B/10B notation, note that the order of bits has

been reversed):

Valid and Invalid Transmission Characters

Data Byte Name D5.2

Bits: ABCDE FGH

10100 010

The following tables define the valid Data Characters and valid

Special Characters (K characters), respectively. The tables

are used for both generating valid Transmission Characters

and checking the validity of received Transmission

Characters. In the tables, each Valid-Data-byte or

Special-Character-code entry has two columns that represent

two Transmission Characters. The two columns correspond to

the current value of the running disparity. Running disparity is

a binary parameter with either a negative (–) or positive (+)

value.

After powering on, the Transmitter may assume either a

positive or negative value for its initial running disparity. Upon

transmission of any Transmission Character, the transmitter

will select the proper version of the Transmission Character

Translated to a transmission Character in the 8B/10B Trans-

mission Code:

Bits: abcdei fghj

101001 0101

Each valid Transmission Character of the 8B/10B Trans-

mission Code has been given a name using the following

convention: cxx.y, where c is used to show whether the Trans-

mission Character is a Data Character (c is set to D, and

SC/D = LOW) or a Special Character (c is set to K, and

SC/D = HIGH). When c is set to D, xx is the decimal value of

Document #: 38-02031 Rev. *J

Page 31 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

based on the current running disparity value, and the Trans-

mitter calculates a new value for its running disparity based on

the contents of the transmitted character. Special Character

codes C1.7 and C2.7 can be used to force the transmission of

a specific Special Character with a specific running disparity

as required for some special sequences in X3.230.

Transmission Character transmitted, a new value of the

running disparity is calculated. This new value is used as the

Transmitter’s current running disparity for the next Valid Data

byte or Special Character byte to be encoded and transmitted.

Table 18 shows naming notations and examples of valid trans-

mission characters.

After powering on, the Receiver may assume either a positive

or negative value for its initial running disparity. Upon reception

of any Transmission Character, the Receiver decides whether

the Transmission Character is valid or invalid according to the

following rules and tables and calculates a new value for its

Running Disparity based on the contents of the received

character.

The following rules for running disparity are used to calculate

the new running-disparity value for Transmission Characters

that have been transmitted (Transmitter’s running disparity)

and that have been received (Receiver’s running disparity).

Running disparity for a Transmission Character is calculated

from sub-blocks, where the first six bits (abcdei) form one

sub-block and the second four bits (fghj) form the other

sub-block. Running disparity at the beginning of the six-bit

sub-block is the running disparity at the end of the previous

Transmission Character. Running disparity at the beginning of

the four-bit sub-block is the running disparity at the end of the

six-bit sub-block. Running disparity at the end of the Trans-

mission Character is the running disparity at the end of the

four-bit sub-block.

Use of the Tables for Checking the Validity of Received

Transmission Characters

The column corresponding to the current value of the

Receiver’s running disparity is searched for the received

Transmission Character. If the received Transmission

Character is found in the proper column, then the Trans-

mission Character is valid and the Data byte or Special

Character code is determined (decoded). If the received

Transmission Character is not found in that column, then the

Transmission Character is invalid. This is called a code

violation. Independent of the Transmission Character’s

validity, the received Transmission Character is used to

calculate a new value of running disparity. The new value is

used as the Receiver’s current running disparity for the next

received Transmission Character.

Table 18. Valid Transmission Characters

Data

D

_INor Q_OUT

Byte Name

765

43210

Hex Value

D0.0

000

00000

00

Running disparity for the sub-blocks is calculated as follows:

D1.0

D2.0

000

00001

00010

01

02

1. Running disparity at the end of any sub-block is positive if

the sub-block contains more ones than zeros. It is also pos-

itive at the end of the six-bit sub-block if the six-bit sub-block

is 000111, and it is positive at the end of the four-bit

sub-block if the four-bit sub-block is 0011.

2. Running disparity at the end of any sub-block is negative if

the sub-block contains more zeros than ones. It is also neg-

ative at the end of the six-bit sub-block if the six-bit

sub-block is 111000, and it is negative at the end of the

four-bit sub-block if the four-bit sub-block is 1100.

.

D5.2

010

00101

45

.

D30.7

D31.7

111

11110

11111

FE

FF

3. Otherwise, running disparity at the end of the sub-block is

the same as at the beginning of the sub-block.

Detection of a code violation does not necessarily show that

the Transmission Character in which the code violation was

detected is in error. Code violations may result from a prior

error that altered the running disparity of the bit stream which

did not result in a detectable error at the Transmission

Character in which the error occurred. Table 19 shows an

example of this behavior.

Use of the Tables for Generating Transmission Characters

The appropriate entry in the table is found for the Valid Data

byte or the Special Character byte for which a Transmission

Character is to be generated (encoded). The current value of

the Transmitter’s running disparity is used to select the Trans-

mission Character from its corresponding column. For each

Table 19. Code Violations Resulting from Prior Errors

RD

–

Character

D21.1

101010 1001

101010 1011

D21.0

RD

–

+

Character

D10.2

010101 0101

D10.2

RD

–

+

Character

D23.5

111010 1010

Code Violation

RD

+

Transmitted data character

Transmitted bit stream

Bit stream after error

Decoded data character

Document #: 38-02031 Rev. *J

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CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Table 20. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000)

Data

Bits

Current RD−

abcdei fghj

Current RD+

abcdei fghj

Bits

Current RD−

abcdei fghj

Current RD+

abcdei fghj

Byte

Name HGF EDCBA

D0.0

000 00000

000 00001

000 00010

000 00011

000 00100

000 00101

000 00110

000 00111

000 01000

000 01001

000 01010

000 01011

000 01100

000 01101

000 01110

000 01111

000 10000

000 10001

000 10010

000 10011

000 10100

000 10101

000 10110

000 10111

000 11000

000 11001

000 11010

000 11011

000 11100

000 11101

000 11110

000 11111

010 00000

010 00001

010 00010

010 00011

010 00100

100111 0100 011000 1011

011101 0100 100010 1011

101101 0100 010010 1011

110001 1011 110001 0100

110101 0100 001010 1011

101001 1011 101001 0100

011001 1011 011001 0100

111000 1011 000111 0100

111001 0100 000110 1011

100101 1011 100101 0100

010101 1011 010101 0100

110100 1011 110100 0100

001101 1011 001101 0100

101100 1011 101100 0100

011100 1011 011100 0100

010111 0100 101000 1011

011011 0100 100100 1011

100011 1011 100011 0100

010011 1011 010011 0100

110010 1011 110010 0100

001011 1011 001011 0100

101010 1011 101010 0100

011010 1011 011010 0100

111010 0100 000101 1011

110011 0100 001100 1011

100110 1011 100110 0100

010110 1011 010110 0100

110110 0100 001001 1011

001110 1011 001110 0100

101110 0100 010001 1011

011110 0100 100001 1011

101011 0100 010100 1011

100111 0101 011000 0101

011101 0101 100010 0101

101101 0101 010010 0101

110001 0101 110001 0101

110101 0101 001010 0101

D0.1

001 00000

001 00001

001 00010

001 00011

001 00100

001 00101

001 00110

001 00111

001 01000

001 01001

001 01010

001 01011

001 01100

001 01101

001 01110

001 01111

001 10000

001 10001

001 10010

001 10011

001 10100

001 10101

001 10110

001 10111

001 11000

001 11001

001 11010

001 11011

001 11100

001 11101

001 11110

001 11111

011 00000

011 00001

011 00010

011 00011

011 00100

100111 1001 011000 1001

011101 1001 100010 1001

101101 1001 010010 1001

110001 1001 110001 1001

110101 1001 001010 1001

101001 1001 101001 1001

011001 1001 011001 1001

111000 1001 000111 1001

111001 1001 000110 1001

100101 1001 100101 1001

010101 1001 010101 1001

110100 1001 110100 1001

001101 1001 001101 1001

101100 1001 101100 1001

011100 1001 011100 1001

010111 1001 101000 1001

011011 1001 100100 1001

100011 1001 100011 1001

010011 1001 010011 1001

110010 1001 110010 1001

001011 1001 001011 1001

101010 1001 101010 1001

011010 1001 011010 1001

111010 1001 000101 1001

110011 1001 001100 1001

100110 1001 100110 1001

010110 1001 010110 1001

110110 1001 001001 1001

001110 1001 001110 1001

101110 1001 010001 1001

011110 1001 100001 1001

101011 1001 010100 1001

100111 0011 011000 1100

011101 0011 100010 1100

101101 0011 010010 1100

110001 1100 110001 0011

110101 0011 001010 1100

D1.0

D1.1

D2.0

D2.1

D3.0

D3.1

D4.0

D4.1

D5.0

D5.1

D6.0

D6.1

D7.0

D7.1

D8.0

D8.1

D9.0

D9.1

D10.0

D11.0

D12.0

D13.0

D14.0

D15.0

D16.0

D17.0

D18.0

D19.0

D20.0

D21.0

D22.0

D23.0

D24.0

D25.0

D26.0

D27.0

D28.0

D29.0

D30.0

D31.0

D0.2

D10.1

D11.1

D12.1

D13.1

D14.1

D15.1

D16.1

D17.1

D18.1

D19.1

D20.1

D21.1

D22.1

D23.1

D24.1

D25.1

D26.1

D27.1

D28.1

D29.1

D30.1

D31.1

D0.3

D1.2

D1.3

D2.2

D2.3

D3.2

D3.3

D4.2

D4.3

Document #: 38-02031 Rev. *J

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CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Table 20. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)

Data

Bits

Current RD−

abcdei fghj

Current RD+

abcdei fghj

Bits

Current RD−

abcdei fghj

Current RD+

abcdei fghj

Byte

Name HGF EDCBA

D5.2

010 00101

010 00110

010 00111

010 01000

010 01001

010 01010

010 01011

010 01100

010 01101

010 01110

010 01111

010 10000

010 10001

010 10010

010 10011

010 10100

010 10101

010 10110

010 10111

010 11000

010 11001

010 11010

010 11011

010 11100

010 11101

010 11110

010 11111

100 00000

100 00001

100 00010

100 00011

100 00100

100 00101

100 00110

100 00111

100 01000

100 01001

101001 0101 101001 0101

011001 0101 011001 0101

111000 0101 000111 0101

111001 0101 000110 0101

100101 0101 100101 0101

010101 0101 010101 0101

110100 0101 110100 0101

001101 0101 001101 0101

101100 0101 101100 0101

011100 0101 011100 0101

010111 0101 101000 0101

011011 0101 100100 0101

100011 0101 100011 0101

010011 0101 010011 0101

110010 0101 110010 0101

001011 0101 001011 0101

101010 0101 101010 0101

011010 0101 011010 0101

111010 0101 000101 0101

110011 0101 001100 0101

100110 0101 100110 0101

010110 0101 010110 0101

110110 0101 001001 0101

001110 0101 001110 0101

101110 0101 010001 0101

011110 0101 100001 0101

101011 0101 010100 0101

100111 0010 011000 1101

011101 0010 100010 1101

101101 0010 010010 1101

110001 1101 110001 0010

110101 0010 001010 1101

101001 1101 101001 0010

011001 1101 011001 0010

111000 1101 000111 0010

111001 0010 000110 1101

100101 1101 100101 0010

D5.3

011 00101

011 00110

011 00111

011 01000

011 01001

011 01010

011 01011

011 01100

011 01101

011 01110

011 01111

011 10000

011 10001

011 10010

011 10011

011 10100

011 10101

011 10110

011 10111

011 11000

011 11001

011 11010

011 11011

011 11100

011 11101

011 11110

011 11111

101 00000

101 00001

101 00010

101 00011

101 00100

101 00101

101 00110

101 00111

101 01000

101 01001

101001 1100 101001 0011

011001 1100 011001 0011

111000 1100 000111 0011

111001 0011 000110 1100

100101 1100 100101 0011

010101 1100 010101 0011

110100 1100 110100 0011

001101 1100 001101 0011

101100 1100 101100 0011

011100 1100 011100 0011

010111 0011 101000 1100

011011 0011 100100 1100

100011 1100 100011 0011

010011 1100 010011 0011

110010 1100 110010 0011

001011 1100 001011 0011

101010 1100 101010 0011

011010 1100 011010 0011

111010 0011 000101 1100

110011 0011 001100 1100

100110 1100 100110 0011

010110 1100 010110 0011

110110 0011 001001 1100

001110 1100 001110 0011

101110 0011 010001 1100

011110 0011 100001 1100

101011 0011 010100 1100

100111 1010 011000 1010

011101 1010 100010 1010

101101 1010 010010 1010

110001 1010 110001 1010

110101 1010 001010 1010

101001 1010 101001 1010

011001 1010 011001 1010

111000 1010 000111 1010

111001 1010 000110 1010

100101 1010 100101 1010

D6.2

D6.3

D7.2

D7.3

D8.2

D8.3

D9.2

D9.3

D10.2

D11.2

D12.2

D13.2

D14.2

D15.2

D16.2

D17.2

D18.2

D19.2

D20.2

D21.2

D22.2

D23.2

D24.2

D25.2

D26.2

D27.2

D28.2

D29.2

D30.2

D31.2

D0.4

D10.3

D11.3

D12.3

D13.3

D14.3

D15.3

D16.3

D17.3

D18.3

D19.3

D20.3

D21.3

D22.3

D23.3

D24.3

D25.3

D26.3

D27.3

D28.3

D29.3

D30.3

D31.3

D0.5

D1.4

D1.5

D2.4

D2.5

D3.4

D3.5

D4.4

D4.5

D5.4

D5.5

D6.4

D6.5

D7.4

D7.5

D8.4

D8.5

D9.4

D9.5

Document #: 38-02031 Rev. *J

Page 34 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Table 20. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)

Data

Bits

Current RD−

abcdei fghj

Current RD+

abcdei fghj

Bits

Current RD−

abcdei fghj

Current RD+

abcdei fghj

Byte

Name HGF EDCBA

D10.4

D11.4

D12.4

D13.4

D14.4

D15.4

D16.4

D17.4

D18.4

D19.4

D20.4

D21.4

D22.4

D23.4

D24.4

D25.4

D26.4

D27.4

D28.4

D29.4

D30.4

D31.4

D0.6

100 01010

100 01011

100 01100

100 01101

100 01110

100 01111

100 10000

100 10001

100 10010

100 10011

100 10100

100 10101

100 10110

100 10111

100 11000

100 11001

100 11010

100 11011

100 11100

100 11101

100 11110

100 11111

110 00000

110 00001

110 00010

110 00011

110 00100

110 00101

110 00110

110 00111

110 01000

110 01001

110 01010

110 01011

110 01100

110 01101

110 01110

010101 1101 010101 0010

110100 1101 110100 0010

001101 1101 001101 0010

101100 1101 101100 0010

011100 1101 011100 0010

010111 0010 101000 1101

011011 0010 100100 1101

100011 1101 100011 0010

010011 1101 010011 0010

110010 1101 110010 0010

001011 1101 001011 0010

101010 1101 101010 0010

011010 1101 011010 0010

111010 0010 000101 1101

110011 0010 001100 1101

100110 1101 100110 0010

010110 1101 010110 0010

110110 0010 001001 1101

001110 1101 001110 0010

101110 0010 010001 1101

011110 0010 100001 1101

101011 0010 010100 1101

100111 0110 011000 0110

011101 0110 100010 0110

101101 0110 010010 0110

110001 0110 110001 0110

110101 0110 001010 0110

101001 0110 101001 0110

011001 0110 011001 0110

111000 0110 000111 0110

111001 0110 000110 0110

100101 0110 100101 0110

010101 0110 010101 0110

110100 0110 110100 0110

001101 0110 001101 0110

101100 0110 101100 0110

011100 0110 011100 0110

D10.5

D11.5

D12.5

D13.5

D14.5

D15.5

D16.5

D17.5

D18.5

D19.5

D20.5

D21.5

D22.5

D23.5

D24.5

D25.5

D26.5

D27.5

D28.5

D29.5

D30.5

D31.5

D0.7

101 01010

101 01011

101 01100

101 01101

101 01110

101 01111

101 10000

101 10001

101 10010

101 10011

101 10100

101 10101

101 10110

101 10111

101 11000

101 11001

101 11010

101 11011

101 11100

101 11101

101 11110

101 11111

111 00000

111 00001

111 00010

111 00011

111 00100

111 00101

111 00110

111 00111

111 01000

111 01001

111 01010

111 01011

111 01100

111 01101

111 01110

010101 1010 010101 1010

110100 1010 110100 1010

001101 1010 001101 1010

101100 1010 101100 1010

011100 1010 011100 1010

010111 1010 101000 1010

011011 1010 100100 1010

100011 1010 100011 1010

010011 1010 010011 1010

110010 1010 110010 1010

001011 1010 001011 1010

101010 1010 101010 1010

011010 1010 011010 1010

111010 1010 000101 1010

110011 1010 001100 1010

100110 1010 100110 1010

010110 1010 010110 1010

110110 1010 001001 1010

001110 1010 001110 1010

101110 1010 010001 1010

011110 1010 100001 1010

101011 1010 010100 1010

100111 0001 011000 1110

011101 0001 100010 1110

101101 0001 010010 1110

110001 1110 110001 0001

110101 0001 001010 1110

101001 1110 101001 0001

011001 1110 011001 0001

111000 1110 000111 0001

111001 0001 000110 1110

100101 1110 100101 0001

010101 1110 010101 0001

110100 1110 110100 1000

001101 1110 001101 0001

101100 1110 101100 1000

011100 1110 011100 1000

D1.6

D1.7

D2.6

D2.7

D3.6

D3.7

D4.6

D4.7

D5.6

D5.7

D6.6

D6.7

D7.6

D7.7

D8.6

D8.7

D9.6

D9.7

D10.6

D11.6

D12.6

D13.6

D14.6

D10.7

D11.7

D12.7

D13.7

D14.7

Document #: 38-02031 Rev. *J

Page 35 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Table 20. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)

Data

Bits

Current RD−

abcdei fghj

Current RD+

abcdei fghj

Bits

Current RD−

abcdei fghj

Current RD+

abcdei fghj

Byte

Name HGF EDCBA

D15.6

D16.6

D17.6

D18.6

D19.6

D20.6

D21.6

D22.6

D23.6

D24.6

D25.6

D26.6

D27.6

D28.6

D29.6

D30.6

D31.6

110 01111

110 10000

110 10001

110 10010

110 10011

110 10100

110 10101

110 10110

110 10111

110 11000

110 11001

110 11010

110 11011

110 11100

110 11101

110 11110

110 11111

010111 0110 101000 0110

011011 0110 100100 0110

100011 0110 100011 0110

010011 0110 010011 0110

110010 0110 110010 0110

001011 0110 001011 0110

101010 0110 101010 0110

011010 0110 011010 0110

111010 0110 000101 0110

110011 0110 001100 0110

100110 0110 100110 0110

010110 0110 010110 0110

110110 0110 001001 0110

001110 0110 001110 0110

101110 0110 010001 0110

011110 0110 100001 0110

101011 0110 010100 0110

D15.7

D16.7

D17.7

D18.7

D19.7

D20.7

D21.7

D22.7

D23.7

D24.7

D25.7

D26.7

D27.7

D28.7

D29.7

D30.7

D31.7

111 01111

111 10000

111 10001

111 10010

111 10011

111 10100

111 10101

111 10110

111 10111

111 11000

111 11001

111 11010

111 11011

111 11100

111 11101

111 11110

111 11111

010111 0001 101000 1110

011011 0001 100100 1110

100011 0111 100011 0001

010011 0111 010011 0001

110010 1110 110010 0001

001011 0111 001011 0001

101010 1110 101010 0001

011010 1110 011010 0001

111010 0001 000101 1110

110011 0001 001100 1110

100110 1110 100110 0001

010110 1110 010110 0001

110110 0001 001001 1110

001110 1110 001110 0001

101110 0001 010001 1110

011110 0001 100001 1110

101011 0001 010100 1110

Document #: 38-02031 Rev. *J

Page 36 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Table 21. Valid Special Character Codes and Sequences (TXCTx = Special Character Code or RXSTx[2:0] = 001)^[46,47]

S.C. Byte Name

Cypress

Alternate

S.C. Byte

Bits

S.C. Byte

Bits

Current RD−

Current RD+

abcdei fghj

S.C. Code Name

K28.0

Name^[48]

HGF EDCBA

Name^[48]

HGF EDCBA

abcdei fghj

C0.0

(C00)

(C01)

(C02)

(C03)

(C04)

(C05)

(C06)

(C07)

(C08)

(C09)

000 00000 C28.0 (C1C)

000 00001 C28.1 (C3C)

000 00010 C28.2 (C5C)

000 00011 C28.3 (C7C)

000 00100 C28.4 (C9C)

000 00101 C28.5 (CBC)

000 00110 C28.6 (CDC)

000 00111 C28.7 (CFC)

000 01000 C23.7 (CF7)

000 01001 C27.7 (CFB)

000 01010 C29.7 (CFD)

000 01011 C30.7 (CFE)

000 11100

001 11100

010 11100

011 11100

100 11100

101 11100

110 11100

111 11100

111 10111

111 11011

111 11101

111 11110

001111 0100

001111 1001

001111 0101

001111 0011

001111 0010

001111 1010

001111 0110

001111 1000

111010 1000

110110 1000

101110 1000

011110 1000

110000 1011

110000 0110

110000 1010

110000 1100

110000 1101

110000 0101

110000 1001

110000 0111

000101 0111

001001 0111

010001 0111

100001 0111

K28.1^[49]

K28.2^[49]

K28.3

C1.0

C2.0

C3.0

C4.0

C5.0

C6.0

C7.0

C8.0

C9.0

K28.4^[49]

K28.5^{[49, 50]}

K28.6^[49]

K28.7^{[49, 51]}

K23.7

K27.7

K29.7

K30.7

C10.0 (C0A)

C11.0 (C0B)

End of Frame Sequence

EOFxx^[52]

C2.1 (C22)

Code Rule Violation and SVS Tx Pattern

001 00010 C2.1

(C22)

001 00010 −K28.5,Dn.xxx0

+K28.5,Dn.xxx1

Exception^{[51, 53]}C0.7

(CE0)

(CE1)

(CE2)

111 00000 C0.7

111 00001 C1.7

111 00010 C2.7

(CE0)

(CE1)

(CE2)

111 00000^[57]

111 00001^[57]

111 00010^[57]

100111 1000

001111 1010

110000 0101

011000 0111

001111 1010

110000 0101

−K28.5^[54]

C1.7

C2.7

+K28.5^[55]

Running Disparity Violation Pattern

Exception^[56]

C4.7

(CE4)

111 00100 C4.7

(CE4)

111 00100^[57]

110111 0101

001000 1010

Notes:

46. All codes not shown are reserved.

47. Notation for Special Character Code Name is consistent with Fibre Channel and ESCON naming conventions. Special Character Code Name is intended to

describe binary information present on I/O pins. Common usage for the name can either be in the form used for describing Data patterns (i.e., C0.0 through

C31.7), or in hex notation (i.e., Cnn where nn = the specified value between 00 and FF).

48. Both the Cypress and alternate encodings may be used for data transmission to generate specific Special Character Codes. The decoding process for received

characters generates Cypress codes or Alternate codes as selected by the DECMODE configuration input.

49. These characters are used for control of ESCON interfaces. They can be sent as embedded commands or other markers when not operating using ESCON protocols.

50. The K28.5 characterisused forframingoperations by the receiver. It is also the pad or fill character transmitted to maintain the serial link when no user data is available.

51. Care must be taken when using this Special Character code. When a K28.7(C7.0) or SVS(C0.7) is followed by a D11.x or D20.x,an alias K28.5 sync character

is created. These sequences can cause erroneous framing and should be avoided while RFEN = HIGH.

52. C2.1 = Transmit either −K28.5+ or +K28.5− as determined by Current RD and modify the Transmission Character that follows, by setting its least significant

bit to 1 or 0. If Current RD at the start of the following character is plus (+) the LSB is set to 0, and if Current RD is minus (−) the LSB becomes 1. This modification

allows construction of X3.230 “EOF” frame delimiters wherein the second data byte is determined by the Current RD.

For example, to send “EOFdt” the controller could issue the sequence C2.1−D21.4− D21.4−D21.4, and the HOTLink Transmitter will send either

K28.5−D21.4−D21.4−D21.4 or K28.5−D21.5− D21.4−D21.4 based on Current RD. Likewise to send “EOFdti” the controller could issue the sequence

C2.1−D10.4−D21.4−D21.4, and the HOTLink Transmitter will send either K28.5−D10.4−D21.4− D21.4 or K28.5−D10.5−D21.4− D21.4 based on Current RD.

The receiver will never output this Special Character, since K28.5 is decoded as C5.0, C1.7, or C2.7, and the subsequent bytes are decoded as data.

53. C0.7 = Transmit a deliberate code rule violation. The code chosen for this function follows the normal Running Disparity rules. The receiver will only output this

Special Character if the Transmission Character being decoded is not found in the tables.

54. C1.7 = Transmit Negative K28.5 (−K28.5+) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong

running disparity. The receiver will output C1.7 if −K28.5 is received with RD+, otherwise K28.5 is decoded as C5.0 or C2.7.

55. C2.7 = Transmit Positive K28.5 (+K28.5−) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong

running disparity. The receiver will output C2.7 if +K28.5 is received with RD−, otherwise K28.5 is decoded as C5.0 or C1.7.

56. C4.7 = Transmit a deliberate code rule violation to indicate a Running Disparity violation. The receiver will only output this Special Character if the Transmission

Character being decoded is found in the tables, but Running Disparity does not match. This might indicate that an error occurred in a prior byte.

57. Supported only for data transmission. The receive status for these conditions will be reported by specific combinations of receive status bits.

Document #: 38-02031 Rev. *J

Page 37 of 39

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Ordering Information

Speed

Ordering Code

Package Name

BB100

Package Type

Operating Range

Commercial

Industrial

Standard CYP15G0101DXB-BBC

Standard CYP15G0101DXB-BBI

Standard CYV15G0101DXB-BBC

Standard CYV15G0101DXB-BBI

100-ball Grid Array

BB100

Commercial

Industrial

Commercial

Industrial

OBSAI

CYW15G0101DXB-BBC

CYW15G0101DXB-BBI

BB100

Standard CYP15G0101DXB-BBXC

Standard CYP15G0101DXB-BBXI

Standard CYV15G0101DXB-BBXC

Standard CYV15G0101DXB-BBXI

BB100

Pb-Free 100-ball Grid Array

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

OBSAI

CYW15G0101DXB-BBXC

CYW15G0101DXB-BBXI

Package Diagram

100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100

TOP VIEW

BOTTOM VIEW

Ø0.05 M C

PIN 1 CORNER

Ø0.25 M C A B

Ø0.45 0.05(100X)

PIN 1 CORNER

1

2

3

4

5

6

7

8

9

10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

A

B

C

D

E

F

G

H

J

G

H

J

K

4.50

1.00

A

9.00

11.00 0.10

B

0.15(4X)

SEATING PLANE

C

51-85107-*B

HOTLink is a registered trademark, and HOTLink II and MultiFrame are trademarks, of Cypress Semiconductor Corporation.

CPRI is a trademark of Siemens AG. IBM and ESCON are registered trademarks, and FICON is a trademark, of International

Business Machines. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-02031 Rev. *J

Page 38 of 39

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CYP15G0101DXB

CYV15G0101DXB

CYW15G0101DXB

Document History Page

Document Title: CYP(V)(W)15G0101DXB Single-channel HOTLink II™ Transceiver

Document Number: 38-02031

Orig. of

REV.

**

ECN NO. Issue Date Change

Description of Change

113123

05/20/02

TPS

New Data Sheet

*A

119704

10/30/02

LNM

Changed TXPER description

Changed TXCLKO description

Changed RXCKSEL to include RXCLKC+

Removed disparity reference from RFMODE

Removed the LOW setting for FRAMCHAR and related references

Removed references to ATM transport

Changed the I_OSTboundary values

Changed V_ODIFand V_OLCfor CML output

Changed the t_TXCLKRand t_TXCLKFmin. values

Changed t_TXDS, t_TXDH, t_TREFDS, and t_TREFDH

Changed t_REFDV–, t_REFCDV–, and t_REFCDV+

Changed the JTAG ID from 0C804069 to 1C804069

Added a section for characterization and standards compliance

Changed I/O type of RXCLKC in I/O coordinates table

*B

*C

122209

122546

12/28/02

02/13/03

RBI

CGX

Minor Change Document Control corrected Document History Page

Changed Minimum tRISE/tFALL for CML

Changed tRXLOCK

Changed tDJ, tRJ

Changed tJTOL

Changed tTXLOCK

Changed tRXCLKH, tRXCLKL

Changed tTXCLKOD+, tTXCLKOD-

Changed Power Specs

Changed verbiage...Paragraph: Clock/Data Recovery

Changed verbiage...Paragraph: Range Control

Added Power-up Requirements

*D

124994

04/15/03

POT

Changed CYP15G0101DXB to CYP(V)15G0101DXB type corresponding to

the Video-compliant parts

Reduced the lower limit of the serial signaling rate from 200 Mbaud to

195 Mbaud and changed the associated specifications accordingly

*E

*F

128366

128835

7/3/03

7/31/03

PDS

KKV

Revised the value of t_RREFDV,t_{REFADV+ and}t_REFCDV+

Minor change: corrections due to editorial error - old file used for *E revision

(reestablishing *D changes)

*G

131898

12/10/03

PDS

When TXCKSEL = MID or HIGH, TXRATE = HIGH is an invalid mode. Made

appropriate changes to reflect this invalid condition

Removed requirement of AC coupling for Serial I/Os for interfacing with

LVPECL I/Os

Changed LFI to Asynchronous output

Expanded the CDR Range Controller’s permissible frequency offset

between incoming serial signaling rate and Reference clock from ±200-PPM

to ±1500-PPM (changed parameter t_REFRX

)

*H

*I

*J

211461

230621

338721

See ECN

KKV

LAR

SUA

Minor change: Package diagram isn’t legible in pdf

Updated package information in features list to reflect correct package

Added CYW15G0101DXB part number for OBSAI RP3 compliance to

support operating data rate upto 1540 MBaud. Made changes to reflect

OBSAI RP3 and CPR compliance. Added Pb-Free Package option for all

parts listed in the datasheet.

Changed MBd to MBaud in SPDSEL pin description

Document #: 38-02031 Rev. *J

Page 39 of 39

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