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CYV270M0104EQ

型号：

CYV270M0104EQ

描述：

自适应视频电缆均衡器[ Adaptive Video Cable Equalizer ]

品牌：

CYPRESS[ CYPRESS ]

页数：

9 页

PDF大小：

245 K

下载PDF手册
CYV270M0104EQ  
Adaptive Video Cable Equalizer  
Features  
Functional Description  
■ Adaptive cable equalization  
The CYV270M0104EQ is an adaptive video cable equalizer  
designed to equalize and restore signals received over 75Ω  
coaxial cable. The equalizer is designed to meet SMPTE 259M  
data rates and is optimized for performance at 270 Mbps. The  
CYV270M0104EQ is optimized to equalize up to 350m of Belden  
1694A and Canare L-5CFB coaxial cable at 270 Mbps. The  
CYV270M0104EQ connects seamlessly to the HOTLink II family  
of transceiver devices and HOTLink receiver devices.  
■ SMPTE 259M Compliant  
■ Supports DVB-ASI at 270 Mbps  
■ Multi standard operation from 143 Mbps to 360 Mbps  
■ Maximum cable length adjustment  
■ Carrier detect and mute functionality  
■ Equalizer bypass mode  
The CYV270M0104EQ has DC restoration to compensate for  
the DC content of the SMPTE pathological patterns. The  
maximum cable length adjust (MCLADJ) sets the approximate  
maximum cable length to equalize. The CYV270M0104EQ’s  
differential serial outputs (SDO, SDO) mute, when the approx-  
imate cable length set by MCLADJ is reached and carrier detect  
(CD) is tied to MUTE. The MUTE pin controls muting of the  
equalizer outputs.  
■ Seamless connection with HOTLink II™ Family and HOTLink®  
Receiver  
■ Equalizes up to 350m of Belden 1694A and Canare L-5CFB  
coaxial cable at 270 Mbps  
■ Low power: 160 mW at 3.3V  
Power consumption is typically 160 mW at 3.3V.  
■ Single 3.3V supply  
■ 16-pin Quad Flat Pb-free (QFN) package  
■ 0.18 μm CMOS technology  
■ Pb-free and RoHS compliant  
■ Pin compatible to existing QFN equalizer devices  
■ Uses Cypress CLEANLink™ technology  
Equalizer System Connection Diagram  
CYV270M0104EQ  
Adaptive  
Serial Links  
HOTLink II  
Serializer  
Cable  
Driver  
HOTLink II  
Deserializer  
Copper Cable  
Connections  
Cable  
Equalizer  
Cypress Semiconductor Corporation  
Document Number: 001-12875 Rev. **  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised October 25, 2007  
[+] Feedback  
CYV270M0104EQ  
Equalizer Block Diagram  
CYV270M0104EQ Adaptive Video Cable Equalizer Block Diagram  
CYV270M0104EQ Adaptive Video Cable Equalizer Block Diagram  
Cable Length Analog  
Carrier Detect and  
Adjustor and Mute  
Mute Control Block  
Threshold Block  
MUTE  
CD  
MCLADJ  
DC Restore  
BYPASS  
SDI, SDI  
Equalizer  
Differential Output  
SDO, SDO  
Pinouts  
Figure 1. Pin Diagram - 16 Pin QFN (Top View)  
16  
15  
14  
13  
1
2
3
4
12  
11  
10  
9
GND  
GND  
SDI  
SDO  
SDO  
GND  
CYV270M0104EQ  
(Marked CY01EQ  
On Package)  
SDI  
GND  
5
6
7
8
Center Pad  
(bottom of package)  
Document Number: 001-12875 Rev. **  
Page 2 of 9  
[+] Feedback  
CYV270M0104EQ  
Table 1. Pin Descriptions - CYV270M0104EQ Adaptive Video Cable Equalizer  
Name  
IO Characteristics Signal Description  
Control Signals  
MUTE  
LVTTL Input  
Mute. When the MUTE pin is set LOW, the equalizer’s differential serial outputs are not  
muted.  
When the MUTE pin is set HIGH, the equalizer’s differential serial outputs are muted. The  
BYPASS setting is ignored when MUTE is HIGH.  
Connecting CD to the MUTE pin enables automatic muting of the equalizer when the signal  
is lost.  
Do not leave an unused MUTE pin floating. Always drive it to a known state.  
CD  
LVTTL Output  
Carrier Detect. When the incoming data stream is present and maximum cable length set  
by MCLADJ is not exceeded, CD outputs a voltage less than 0.8V.  
When the incoming data stream is not present or maximum cable length set by MCLADJ  
is exceeded, CD outputs a voltage greater than 2.8V.  
Connecting CD to the MUTE pin enables automatic muting of the equalizer when the signal  
is lost.  
MCLADJ  
BYPASS  
Analog Input  
LVTTL Input  
Maximum Cable Length Adjust. The maximum cable length to equalize is set by the  
voltage applied to the MCLADJ input. When the maximum cable length set by MCLADJ is  
reached, the CD indicator deasserts.  
If MCLADJ functionality is not required, then this pin should be left floating or tied to ground  
to allow maximum equalized cable length.  
Equalizer Bypass. When BYPASS is set HIGH, the signal presented at the equalizer’s  
differential serial inputs (SDI, SDI) is routed to the equalizer’s differential serial outputs  
(SDO, SDO) without performing equalization.  
When BYPASS is set LOW, the incoming video data stream is equalized and presented  
at the equalizer‘s serial differential outputs (SDO, SDO).  
When MUTE is set HIGH, the BYPASS setting is ignored and the serial outputs are muted.  
AGC, AGC  
SDO, SDO  
Analog  
Automatic Gain Control. Place a 1 μF capacitor between the AGC and AGC pins.  
Differential  
Output  
Differential Serial Outputs. The equalized serial video data stream is presented at the  
SDO/SDO differential serial CML output.  
SDI, SDI  
Differential  
Input  
Differential Serial Inputs. SDI/SDI accepts either a single-ended or differential serial  
video data stream over 75Ω coaxial cable.  
Power  
VCC  
Power  
Gnd  
–
Power Supply for Device. Connect to +3.3V DC.  
Connect to Ground.  
GND  
Center Pad  
Connect to PCB Ground for Maximum Thermal Dissipation.  
Document Number: 001-12875 Rev. **  
Page 3 of 9  
[+] Feedback  
CYV270M0104EQ  
Equalizer Operation  
MUTE  
The CYV270M0104EQ is an adaptive video cable equalizer that  
equalizes standard definition (SD) serial digital interface (SDI)  
video data streams. The CYV270M0104EQ equalizer is  
optimized to equalize up to 350m of Belden 1694A and Canare  
L-5CFB cable at 270 Mbps. The device contains one power  
supply and typically consumes 160 mW power at 3.3V. The  
adaptive equalizer meets the SMPTE 259M and DVB-ASI video  
standards. It meets all pathological requirements for SMPTE  
259M as defined by RP178. The CYV270M0104EQ Video Cable  
Equalizer is auto adaptive from 143 Mbps to 360 Mbps.  
MUTE is an input pin that controls the muting of the equalizer’s  
output.  
If MUTE is set LOW, then the equalizer serial outputs are not  
muted. If MUTE is set HIGH, then the equalizer serial outputs are  
muted. When MUTE is active, the BYPASS setting is also  
ignored.  
Connecting CD to MUTE enables automatic muting of the  
equalizer when the signal is lost.  
Do not leave the MUTE pin floating. Always drive it to a known  
state.  
The CYV270M0104EQ equalizer has multiple variable gain  
equalization stages that reverse the effects of the cable. This  
equalization is achieved by separate regulation of the lower and  
higher frequency components in the signal to give a clean output  
eye diagram. The CYV270M0104EQ has DC restoration for  
compensating the DC content of the SMPTE pathological  
patterns.  
Carrier Detect (CD)  
Carrier Detect is an active LOW output pin that indicates the  
presence of a valid incoming data signal. When the incoming  
data signal is present and maximum cable length does not  
exceed the length that is set by MCLADJ, CD outputs a voltage  
less than 0.8V.  
SDI, SDI  
When the incoming data stream is not present or maximum cable  
length exceeds the length that is set by MCLADJ, CD outputs a  
voltage greater than 2.8V.  
CYV270M0104EQ accepts single-ended or differential serial  
video data streams over 75Ω coaxial cable. It is recommended  
to AC couple the SDI and SDI inputs because they are internally  
biased to 1.2V.  
Connecting CD to MUTE enables automatic muting of the  
equalizer when the signal is lost.  
SDO, SDO  
BYPASS  
The CYV270M0104EQ has differential serial output interface  
drivers that use Current Mode Logic (CML) drivers to provide  
source matching for the transmission line. These outputs are  
either AC coupled or DC coupled to HOTLink II receivers.  
The CYV270M0104EQ has a bypass mode that enables the user  
to bypass the equalizer’s equalization and DC restoration  
functions. When BYPASS is set HIGH, the signal presented at  
the equalizer’s differential serial inputs (SDI, SDI) is routed to the  
equalizer’s differential serial outputs (SDO, SDO) without equal-  
izing.  
MCLADJ  
Maximum Cable Length Adjust (MCLADJ) sets the approximate  
maximum amount of cable to equalize. When the maximum  
cable length set by MCLADJ is reached, the CD pin deasserts.  
To enable automatic muting of the device when the signal is lost,  
tie CD directly to MUTE.  
When BYPASS is set LOW, the incoming video data stream is  
equalized and presented at the equalizer‘s differential serial  
outputs (SDO, SDO).  
AGC  
The graph in Figure 2 on page 7 illustrates the voltage required  
at MCLADJ input to equalize various Belden 1694A cables. The  
same graph applies for Canare L-5CFB cables. If MCLADJ  
functionality is not required, this pin should be left floating or tied  
to ground to allow maximum equalized cable length.  
Place a 1 μF capacitor between the AGC and AGC pins of the  
CYV270M0104EQ equalizer.  
Document Number: 001-12875 Rev. **  
Page 4 of 9  
[+] Feedback  
CYV270M0104EQ  
Power Up Requirements  
Maximum Ratings  
The CYV270M0104EQ contains one power supply. The voltage  
on any input or IO pin must not exceed the power pin during  
power up.  
Exceeding maximum ratings may shorten the useful life of the  
device. These user guidelines are not tested.  
Storage Temperature.................................. –65°C to +150°C  
Ambient Temperature with  
Power Applied ............................................ –55°C to +125°C  
Operating Range  
Ambient  
Temperature  
Range  
VCC  
Supply Voltage to Ground Potential................–0.5V to +3.8V  
DC Voltage Applied to Outputs  
in High Z State....................................... –0.5V to VCC + 0.5V  
Commercial  
0°C to +70°C  
+3.3V ±5%  
DC Input Voltage ................................... –0.5V to VCC + 0.5V  
Electro Static Discharge (ESD) HBM........................> 2000V  
(JEDEC EIA/JESD-A114A)  
Latch Up Current ....................................................> 200 mA  
DC Electrical Characteristics  
Parameter  
Description  
Supply Voltage[1]  
Power Consumption[2]  
Supply Current[1]  
Test Conditions  
Min  
3.135  
125  
38  
Typ  
3.3  
160  
48  
Max  
3.465  
190  
60  
Unit  
V
VCC  
PD  
–
–
–
mW  
mA  
V
IS  
VCMOUT  
Output Common Mode Voltage[1]  
Load = 50Ω  
–
VCC – ΔVSDO/2 =  
–
2.9  
VCMIN  
Input Common Mode Voltage[1]  
(Bypass = High)  
Input Common Mode Voltage[1]  
(Bypass = Low)  
–
–
1
0
1.4  
2.9  
V
V
–
Floating MCLADJ DC Voltage[1]  
MCLADJ Range[3]  
CD Output Voltage[1]  
–
–
1.3  
0.72  
–
V
V
V
V
V
–
0.4  
2.8  
–
1.02  
–
VCD(OH)  
VCD(OL)  
VMUTE  
Carrier Not Present  
Carrier Present  
Min to Mute  
–
0.8  
–
MUTE Input Voltage Required to  
Force Outputs to Mute[1]  
2.5  
VMUTE  
MUTE Input Voltage Required to  
Force Active[1]  
Max to Activate  
–
–
1
V
Notes  
1. Production test.  
2. Calculated results from production test.  
3. Not tested. Based on characterization.  
Document Number: 001-12875 Rev. **  
Page 5 of 9  
[+] Feedback  
CYV270M0104EQ  
AC Electrical Characteristics  
Parameter  
Description  
Serial Input Data Rate[1]  
Input Voltage Swing  
Test Conditions  
Min  
143  
500[5]  
Typ  
Max  
360  
Unit  
Mbps  
mV  
–
–
–
VSDI  
Single-ended, at the transmitter,  
SD data rate  
1200  
ΔVSDO  
Output Voltage Swing[1]  
Differentialp-p, 50Ω load  
450  
–
700  
0.2[1]  
950  
–
mV  
UI  
–
Output Jitter for Various Cable  
Lengths and Data Rates  
270 Mbps  
Belden 1694A: 0-350m  
Canare L-5CFB: 0-350m  
800 mV transmit amplitude  
Equalizer pathological pattern  
–
–
–
–
–
–
–
–
Output Rise/Fall Time[3, 4]  
Mismatch in Rise/Fall Time[3, 4]  
Duty Cycle Distortion[3, 4]  
Overshoot[3, 4]  
20% - 80%  
80  
–
120  
–
350  
30  
–
ps  
ps  
UI  
%
–
SD color bar pattern  
–
–
0.03  
–
–
10  
–
Input Return Loss[3]  
–
-15  
–
–
dB  
kΩ  
pF  
Ω
Input Resistance[3, 4]  
Input Capacitance[3, 4]  
Output Resistance[3, 4]  
Single-ended  
Single-ended  
Single-ended  
2.5  
1
–
–
–
–
50  
–
Notes  
4. Not tested. Guaranteed by design simulations.  
5. Based on characterization across temperature and voltage with 350m of Belden 1694A and Canare L-5CFB cable, transmitting SMPTE Equalizer Pathological Test  
Pattern.  
Document Number: 001-12875 Rev. **  
Page 6 of 9  
[+] Feedback  
CYV270M0104EQ  
Typical Performance Graphs  
(Unless otherwise stated, VCC = 3.3V, TA = 25°C)  
Figure 2. MCLADJ Input Voltage vs Belden 1694A Cable Length at SD-SDI Data Rate  
2.7  
2.6  
2.5  
2.4  
2.3  
2.2  
2.1  
2
1.9  
1.8  
1.7  
0
50  
100  
150  
200  
250  
300  
350  
CABLE LENGTH (m)  
Typical Application Circuit  
Figure 3. Interfacing CYV270M0104EQ to the HOTLink II SerDes  
+3.3V  
+3.3V  
C10  
C12  
13 14 15 16  
0.01μF  
0.01μF  
LFI  
RXLE  
SDASEL  
LPEN  
1μF  
1μF  
BNC JACK  
R16  
RXD7  
12  
11  
10  
C15  
GND  
SDO  
RXD6  
75Ω  
1
2
RXD5  
INSEL  
GND  
SDI  
Z0  
Z0  
RXD4  
75Ω  
IN1+  
SDO  
GND  
RXD3  
L2  
2 Z0  
R18  
3
4
C16  
RXD2  
SDI  
GND  
9
RXD1  
IN1-  
6.4nH  
RXD0  
FRAMCHAR  
RFEN  
RFMODE  
DECMODE  
RXCKSEL  
RXMODE  
RXRATE  
RXOP  
37.4Ω  
RXST2  
RXST1  
RXST0  
RXCLK+  
RXCLK-  
RXCLKC+  
75Ω  
R15  
R14  
6
8
7
5
CYV270M0104EQ  
C11  
1μF  
MCLADJ  
C YV15G0101DXB  
Document Number: 001-12875 Rev. **  
Page 7 of 9  
[+] Feedback  
CYV270M0104EQ  
Ordering Information  
Package  
Marking  
Operating  
Range  
Ordering Code  
Package Name  
Package Type  
Pb-free 16-Pin QFN  
CYV270M0104EQ-LXC  
CY01EQ  
LY16A  
0 to 70°C  
Package Dimension  
Figure 4. 16-Pin QFN (4x4 mm) Package LY16A  
0.05  
C
3.90  
4.10  
2.50  
REF.  
1.00 MAX.  
0.80 MAX.  
0.05 MAX.  
0.20 REF.  
3.70  
3.80  
PIN1 ID  
0.20 R.  
0.35 0.05  
REF.  
N
N
2.50  
0.45  
1
1
2
2
E-PAD  
1.90  
2.00  
0.30-0.50  
0.65  
0.42 0.18  
(4X)  
0°-12°  
C
1.90  
2.00  
SEATING  
PLANE  
TOP VIEW  
BOTTOM VIEW  
SIDE VIEW  
DIMENSION IN mm  
MIN.  
MAX.  
PART #  
001-04468-*A  
LF16A STANDARD PKG.  
LY16A LEAD FREE PKG.  
REFERENCE JEDEC MO-220  
PKG.WEIGHT 0.04gms  
Document Number: 001-12875 Rev. **  
Page 8 of 9  
[+] Feedback  
CYV270M0104EQ  
Document History Page  
Document Title: CYV270M0104EQ Adaptive Video Cable Equalizer  
Document Number: 001-12875  
ISSUE  
DATE  
ORIG. OF  
CHANGE  
REV.  
ECN NO.  
DESCRIPTION OF CHANGE  
**  
1396423  
SEE ECN  
UKK/AESA  
New datasheet  
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any  
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,  
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical  
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-12875 Rev. **  
Revised October 25, 2007  
Page 9 of 9  
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered  
2
trademarks referenced herein are property of the respective corporations. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the  
2
2
2
Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. HOTLink is a registered trademark and  
HOTLink II and CLEANLink are trademarks of Cypress Semiconductor. All other trademarks or registered trademarks referenced herein are property of the respective corporations. All products and  
company names mentioned in this document may be the trademarks of their respective holders.  
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