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CYV270M0101EQ

型号:

CYV270M0101EQ

描述:

自适应视频电缆均衡器( SOIC )[ Adaptive Video Cable Equalizer (SOIC) ]

品牌:

CYPRESS[ CYPRESS ]

页数:

10 页

PDF大小:

329 K

CYV270M0101EQ  
Adaptive Video Cable Equalizer (SOIC)  
Features  
Functional Description  
• Adaptive Cable Equalization  
The CYV270M0101EQ is an adaptive video cable equalizer  
designed to equalize and restore signals received over 75Ω  
coaxial cable. The equalizer is designed to meet SMPTE  
259M data rates and is optimized for performance at 270  
• SMPTE 259M Compliant  
• Supports DVB-ASI at 270 Mbps  
Mbps. The CYV270M0101EQ is optimized to equalize up to  
350m of Belden 1694A coaxial cable at 270 Mbps. The  
CYV270M0101EQ connects seamlessly to the HOTLink II  
family of transceiver devices and HOTLink(R) receiver  
devices.  
• Multi-standard operation from 143 Mbps to 360 Mbps  
• Cable Length Indicator for SD-SDI data rates  
• Maximum Cable Length Adjustment for SD-SDI data rates  
• Carrier detect and Mute functionality for SD-SDI data rates  
• Equalizer Bypass Mode  
The CYV270M0101EQ has DC restoration for compensation  
of the DC content of the SMPTE pathological patterns. A cable  
length indicator (CLI) provides an indication of the cable length  
being equalized at SD-SDI data rates. The Maximum cable  
length adjust (MCLADJ) sets the approximate maximum cable  
length to be equalized. The CYV270M0101EQ’s differential  
serial outputs (SDO, SDO) mute, when the approximate cable  
length set by MCLADJ is reached. CD/MUTE is a bidirectional  
pin that provides an indication of the signal being present at  
the equalizer inputs. It also controls muting the outputs of the  
equalizer.  
• Seamless connection with HOTLink II™ Family, HOTLink  
(R)™ Receiver  
• Equalizes up to 350m of Belden 1694A coaxial cable at 270  
Mbps  
• Low Power 160 mW @ 3.3V  
• Single 3.3V supply  
• 16-pin SOIC  
• 0.18-µm CMOS technology  
• Pb-free and RoHS compliant  
• Pin-compatible to existing equalizer devices  
Power consumption is typically 160 mW at 3.3V.  
Equalizer System Connection Diagram  
CYV270M0101EQ  
HOTLink IITM  
Multi-Rate  
HOTLink IITM  
Serializer  
Serial Links  
Cable  
Driver  
Deserializer  
Cable  
Equalizer  
Copper Cable  
Connections  
Cypress Semiconductor Corporation  
Document #: 001-06830 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 8, 2007  
[+] Feedback  
CYV270M0101EQ  
Equalizer Block Diagram  
CYV270M0101EQ Adaptive Video Cable Equalizer Block Diagram  
CYV270M0101EQ Adaptive Video Cable Equalizer Block Diagram  
Cable Length Analog  
Carrier Detect and Mute  
Indicator and Mute  
Control Block  
CLI  
CD / MUTE  
MCLADJ  
Threshold Block  
DC Restore  
BYPASS  
SDI, SDI  
Equalizer  
Differential Output  
SDO, SDO  
Pin Configuration (Top View)  
16-PIN SOIC Top View  
16  
15  
CD/MUTE  
VCC  
CLI  
2
VCC  
GND  
3
4
14  
13  
GND  
SDO  
SDI  
SDI  
CYV270M0101EQ  
5
6
12  
11  
SDO  
GND  
GND  
AGC+  
AGC-  
7
8
10  
9
MCLADJ  
BYPASS  
Document #: 001-06830 Rev. *A  
Page 2 of 10  
[+] Feedback  
CYV270M0101EQ  
Pin Descriptions  
CYV270M0101EQ Single Channel Cable Equalizer  
Name  
I/O Characteristics Signal Description  
Control Signals  
CLI  
Analog Output  
LVTTL I/O  
Cable Length Indicator: CLI provides an analog voltage proportional to the cable  
length being equalized.  
CD/MUTE  
Carrier Detect/Mute Indicator:  
Output:  
When the incoming data stream is present, the CD/MUTE outputs a voltage less than  
0.8V.  
When the incoming data stream is not present, the CD/MUTE outputs a voltage  
greater than 2.9V.  
Input:  
When the CD/MUTE pin is tied to ground, the equalizer’s differential serial outputs  
are not muted and the MCLADJ setting is overwritten.  
When the CD/MUTE pin is tied to V , the equalizer’s differential serial outputs are  
CC  
muted and the MCLADJ setting is overwritten.  
MCLADJ  
BYPASS  
Analog Input  
LVTTL Input  
Maximum Cable Length Adjust: The maximum cable length to be equalized is set  
by the voltage applied to the MCLADJ input. When the maximum cable length set by  
MCLADJ is reached, the differential output is muted.  
Equalizer Bypass: When BYPASS is tied to V , the signal presented at the  
CC  
equalizer’s differential serial inputs (SDI, SDI) is routed to the equalizer’s differential  
serial outputs (SDO, SDO) without performing equalization.  
When BYPASS is tied to GND, the incoming video data stream is equalized and  
presented at the equalizer‘s serial differential outputs (SDO, SDO).  
In equalizer bypass mode, CD/MUTE is not functional.  
AGC±  
Analog  
Automatic Gain Control: A capacitor of 1 µF should be placed between the AGC±  
pins.  
SDO, SDO  
SDI, SDI  
Differential  
Output  
Differential Serial Outputs: The equalized serial video data stream is presented at  
the SDO/SDO differential serial CML output.  
Differential  
Input  
Differential Serial Inputs: SDI/SDI can accept either a single ended or differential  
serial video data stream over 75coaxial cable.  
Power  
VCC  
Power  
Gnd  
+3.3V Power.  
GND  
Connect to Ground.  
The CYV270M0101EQ equalizer has variable gain and  
multiple equalization stages that reverse the effects of the  
Equalizer Operation  
The CYV270M0101EQ is an adaptive video cable equalizer  
designed to equalize standard definition (SD) serial digital  
interface (SDI) video data streams. The CYV270M0101EQ  
equalizer is optimized to equalize up to 350m of Belden 1694A  
cable at 270 Mbps. The CYV270M0101EQ equalizer contains  
one power supply and typically consumes 160 mW power at  
3.3V. The adaptive equalizer is designed to meet the SMPTE  
259M and DVB-ASI video standards. The equalizer meets all  
pathological requirements for SMPTE 259M as defined by  
RP178. The CYV270M0101EQ Video Cable Equalizer is  
auto-adaptive from 143 Mbps to 360 Mbps.  
cable. This equalization is achieved by separate regulation of  
the lower and higher frequency components in the signal to  
give a clean eye. The CYV270M0101EQ has DC restoration  
for compensating the DC content of the SMPTE pathological  
patterns.  
SDI, SDI  
The CYV270M0101EQ accepts single-ended or differential  
serial video data streams over 75coaxial cable. It is recom-  
mended to AC-couple the SDI, SDI inputs as they are inter-  
nally biased to 1.2V.  
Document #: 001-06830 Rev. *A  
Page 3 of 10  
[+] Feedback  
CYV270M0101EQ  
equalizer’s input, or it controls the muting of the equalizer’s  
output.  
SDO, SDO  
The CYV270M0101EQ has differential serial output interface  
drivers that use current mode logic [CML] drivers to provide  
source matching for the transmission line. These outputs can  
be either AC coupled or DC coupled to the HOTLink II SerDes  
device.  
If CD/MUTE is used as an output, and the incoming data  
stream is not present, the voltage at the CD/MUTE output will  
be greater than 2.9V. If CD/MUTE is used as an output, and  
the incoming data stream is present, then the voltage at the  
CD/MUTE output will be less than 0.8V.  
If CD/MUTE is used as an input, and tied to ground, the  
equalizer serial outputs are not muted and the MCLADJ  
setting is overwritten. If the CD/MUTE is used as an input and  
CLI  
Cable Length Indicator (CLI) is an analog output that gives an  
output voltage proportional to the cable length being  
equalized. CLI gives an approximation of the length of cable  
at the differential serial inputs (SDI, SDI). CLI works at  
standard definition (SD) data rates. The graph in Figure 2 illus-  
trates the CLI output voltage at various Belden 1694A cable  
lengths. With an increase in cable length, CLI output voltage  
decreases.  
is tied to V , then the equalizer serial outputs are muted and  
CC  
the MCLADJ setting is overwritten.  
When an invalid signal or a signal transmitted with a launch  
amplitude of less than 500mV at SD data-rates is received, the  
equalizer’s serial outputs are muted and the MCLADJ setting  
is overwritten.  
BYPASS  
MCLADJ  
The CYV270M0101EQ has a bypass mode that allows the  
user to bypass the equalizer’s equalization and DC restoration  
Maximum Cable Length Adjust (MCLADJ) sets the approx-  
imate maximum amount of cable to be equalized. When the  
maximum cable length set by MCLADJ is reached, the outputs  
are muted.  
functions. When the Bypass mode is tied to V , the signal  
CC  
presented at the equalizer’s differential serial inputs (SDI, SDI)  
is routed to the equalizer’s differential serial outputs (SDO,  
SDO) without performing equalization.  
If the MCLADJ voltage is greater than the CLI output voltage,  
the equalizer serial differential outputs (SDO, SDO) are muted.  
If the MCLADJ voltage is less than CLI voltage, then the  
equalizer’s differential serial outputs (SDO, SDO) are not  
muted and the incoming data stream is equalized. The graph  
in Figure 1 illustrates the voltage needed at MCLADJ input, to  
equalize various Belden 1694A cable lengths for SD data  
rates. The MCLADJ pin can be left unconnected in applica-  
tions that do not require muting of the outputs.  
When BYPASS is tied to GND, the incoming video data stream  
is equalized and presented at the equalizer‘s differential serial  
outputs (SDO, SDO).  
In equalizer bypass mode, CD/MUTE is not functional.  
AGC  
A capacitor of 1 µF should be placed between the AGC± pins  
of the CYV270M0101EQ equalizer.  
CD/MUTE  
Carrier Detect/MUTE (CD/MUTE) is a bidirectional pin that  
provides an indication of the signal being present at the  
Document #: 001-06830 Rev. *A  
Page 4 of 10  
[+] Feedback  
CYV270M0101EQ  
Power-up Requirements  
Maximum Ratings  
The CYV270M0101EQ contains one power supply. The  
voltage on any input or I/O pin cannot exceed the power pin  
during power-up.  
Above which the useful life may be impaired. User guidelines  
only, not tested  
Storage Temperature ..................................65°C to +150°C  
Operating Range  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Ambient  
Range  
Temperature  
VCC  
Supply Voltage to Ground Potential............... –0.5V to +3.8V  
DC Voltage Applied to Outputs  
Commercial  
0°C to +70°C  
+3.3V ±5%  
in High-Z State .......................................–0.5V to V + 0.5V  
CC  
DC Input Voltage......................................–0.5V to V +0.5V  
CC  
Electro Static Discharge (ESD) HBM.......................> 2000 V  
(per JEDEC EIA/JESD-A114A)  
Latch-Up Current ....................................................> 200 mA  
DC Electrical Characteristics  
Parameter  
Description  
Test Conditions  
Min.  
Typ.  
Max.  
3.465  
190  
58  
Unit  
V
[1]  
V
P
Supply Voltage  
3.135  
125  
38  
3.3  
160  
48  
CC  
D
[2]  
Power Consumption  
mW  
mA  
V
[1]  
I
Supply Current  
S
[1]  
V
V
Output Common Mode Voltage  
Load = 50Ω  
V
V /2  
SDO  
CMOUT  
CC  
[1]  
Input Common Mode Voltage  
[Bypass = High]  
1
1.24  
1.4  
V
CMIN  
[1]  
Input Common Mode Voltage  
[Bypass = Low]  
0
1.24  
2.9  
V
[1]  
V
V
V
CLI DC Voltage (0m)  
2.3  
1.5  
1.1  
0.4  
2.9  
2.65  
1.9  
1.3  
0.72  
2.95  
2.3  
1.6  
1.02  
V
V
V
V
V
V
V
[1]  
CLI DC Voltage (no signal)  
[1]  
Floating MCLADJ DC Voltage  
[3]  
MCLADJ Range  
[1]  
CD/MUTE Output Voltage  
Carrier Not Present  
Carrier Present  
Min. to Mute  
CD/MUTE(OH)  
CD/MUTE(OL)  
CD/MUTE  
0.8  
CD/MUTE Input Voltage Required to  
2.5  
[1]  
Force Outputs to Mute  
V
CD/MUTE Input Voltage Required to  
Force Active  
Max. to Activate  
1
V
CD/MUTE  
[1]  
Notes  
1. Production test.  
2. Calculated results from production test.  
3. Not tested. Based on characterization.  
Document #: 001-06830 Rev. *A  
Page 5 of 10  
[+] Feedback  
CYV270M0101EQ  
AC Electrical Characteristics  
Parameter  
Description  
Test Conditions  
Min.  
Typ.  
Max.  
360  
Unit  
Mbps  
mV  
[1]  
Serial Input Data Rate  
143  
[5]  
[1]  
V
Input Voltage Swing  
Singleended, atthetransmitter,  
SD data rate  
500  
800  
1200  
SDI  
[1]  
V  
Output Voltage Swing  
Differential , 50load  
500  
700  
950  
mV  
m
SDO  
p-p  
Maximum Equalized Cable  
270 Mbps, Belden 1694A,  
800 mV transmit amplitude,  
equalizer pathological pattern,  
0.2 UI equalizer output jitter  
350  
[1]  
Length  
[3, 4]  
Output Rise/Fall Time  
20% - 80%  
80  
120  
270  
30  
ps  
ps  
UI  
%
[3, 4]  
Mismatch in Rise/Fall time  
SD Color Bar Pattern  
[3, 4]  
Duty cycle distortion  
0.03  
[3, 4]  
Overshoot  
10  
[3, 4]  
Input Return Loss  
15  
dB  
kΩ  
pF  
[3]  
Input Resistance  
Single ended  
Single ended  
Single ended  
2.5  
1
[3]  
Input Capacitance  
[3]  
Output Resistance  
50  
Notes  
4. Not tested. Guaranteed by design simulations.  
5. Based on characterization across temperature and voltage with 350m of Belden 1694A cable, transmitting SMPTE Equalizer Pathological Test Pattern.  
Document #: 001-06830 Rev. *A  
Page 6 of 10  
[+] Feedback  
CYV270M0101EQ  
Typical Performance Graphs  
(Unless Otherwise mentioned, V = 3.3V, T = 25°C)  
CC  
A
Figure 1. MCLADJ Input Voltage vs. Belden 1694A Cable Length at SD-SDI Data Rate  
2.7  
2.6  
2.5  
2.4  
2.3  
2.2  
2.1  
2
1.9  
1.8  
1.7  
0
50  
100  
150  
200  
250  
300  
350  
CABLE LENGTH (m)  
Figure 2. CLI Output Voltage vs. Belden 1694A Cable Length at SD-SDI Data Rate  
2.7  
2.6  
2.5  
2.4  
2.3  
2.2  
2.1  
2
1.9  
1.8  
1.7  
0
50  
100  
150  
200  
250  
300  
350  
CABLE LENGTH (m)  
Document #: 001-06830 Rev. *A  
Page 7 of 10  
[+] Feedback  
CYV270M0101EQ  
Typical Application Circuit  
Figure 3. Interfacing CYV270M0101EQ to the HOTLink II SerDes  
C D / M U T E  
C L I  
C12  
+3.3V  
+3.3V  
C10  
0.01 µF  
0. 01 µF  
LFI  
RXLE  
SDASEL  
LPEN  
BNC JACK  
RXD7  
RXD6  
RXD5  
RXD4  
RXD3  
RXD2  
RXD1  
RXD0  
RXOP  
RXST2  
R16  
1 µF  
C15  
C16  
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
C D / M U T E  
V C C  
75Ω  
C L I  
V C C  
V E E  
S D I  
INSEL  
75 Ω  
L2  
Z0  
Z0  
IN1+  
V E E  
S D O  
S D O  
V E E  
1 µF  
2 Z0  
R18  
S D I  
6.4 n H  
IN1  
V E E  
M C L A D J  
B Y P A S S  
A G C +  
FRAMCHAR  
RFEN  
A G C  
+
37.4 Ω  
75 Ω  
1 µF  
C11  
RFMODE  
DECMODE  
RXCKSEL  
RXMODE  
RXRATE  
RXST1  
RXST0  
RXCLK+  
R15  
R14  
CYV270M0101EQ  
RXCLK  
RXCLKC+  
M C L A D J  
CYV15G0101DXB  
Ordering Information  
Operating  
Range  
Ordering Code  
Package Name  
Package Type  
CYV270M0101EQ-SXC  
SZ16.15  
Pb-Free16-lead 150-mil SOIC  
0 to 70°C  
Document #: 001-06830 Rev. *A  
Page 8 of 10  
[+] Feedback  
CYV270M0101EQ  
Package Dimensions  
Figure 4. 16-Lead (150-Mil) SOIC S16.15  
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51-85068-*B  
HOTLink II is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the  
trademarks of their respective holders.  
Document #: 001-06830 Rev. *A  
Page 9 of 10  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
[+] Feedback  
CYV270M0101EQ  
Document History Page  
Document Title: CYV270M0101EQ Adaptive Video Cable Equalizer (SOIC)  
Document Number: 001-06830  
ISSUE  
DATE  
ORIG. OF  
CHANGE  
REV.  
**  
ECN NO.  
427547  
663916  
DESCRIPTION OF CHANGE  
New Preliminary Data Sheet  
SEE ECN  
SEE ECN  
BCD  
FRE  
*A  
Updated AC and DC Parameters. Changed Data Sheet status from  
preliminary to final  
Document #: 001-06830 Rev. *A  
Page 10 of 10  
[+] Feedback  
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