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CYV15G0204TRB-BGC

型号：

CYV15G0204TRB-BGC

描述：

独立时钟的HOTLink II⑩双串行器和双时钟恢复器和解串器[ Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer ]

品牌：

CYPRESS[ CYPRESS ]

页数：

31 页

PDF大小：

814 K

下载PDF手册
CYV15G0204TRB  
Independent Clock HOTLink II™ Dual  
Serializer and Dual Reclocking Deserializer  
• Thermally enhanced BGA  
Features  
• Pb-Free package option available  
• Second-generation HOTLink® technology  
• 0.25μ BiCMOS technology  
• Compliant to SMPTE 292M and SMPTE 259M video  
standards  
Functional Description  
• Dual-channel video serializer plus dual channel video  
reclocking deserializer  
The CYV15G0204TRB Independent Clock HOTLink II™ Dual  
Serializer and Dual Reclocking Deserializer is a point-to-point  
or point-to-multipoint communications building block enabling  
transfer of data over a variety of high-speed serial links  
including SMPTE 292M and SMPTE 259M video applications.  
It supports signaling rates in the range of 195 to 1500 Mbps  
per serial link. All transmit and receive channels are  
independent and can operate simultaneously at different  
rates. Each transmit channel accepts 10-bit parallel characters  
in an Input Register and converts them to serial data. Each  
receive channel accepts serial data and converts it to 10-bit  
parallel characters and presents these characters to an Output  
Register. The received serial data can also be reclocked and  
retransmitted through the reclocker serial outputs. Figure 1  
illustrates typical connections between independent video  
co-processors and corresponding CYV15G0204TRB chips.  
— 195- to 1500-Mbps serial data signaling rate  
— Simultaneous operation at different signaling rates  
• Supportsreceptionofeither1.485or1.485/1.001Gbpsdata  
rate with the same training clock  
• Supports half-rate and full-rate clocking  
• Internal phase-locked loops (PLLs) with no external PLL  
components  
• Selectable differential PECL-compatible serial inputs  
— Internal DC-restoration  
• Redundant differential PECL-compatible serial outputs  
— No external bias resistors required  
— Signaling-rate controlled edge-rates  
— Internal source termination  
The CYV15G0204TRB satisfies the SMPTE 259M and  
SMPTE 292M compliance as per SMPTE EG34-1999 Patho-  
logical Test Requirements.  
• Synchronous LVTTL parallel interface  
• JTAG boundary scan  
As  
a
second-generation  
HOTLink  
device,  
the  
CYV15G0204TRB extends the HOTLink family with enhanced  
levels of integration and faster data rates, while maintaining  
serial-link compatibility (data and BIST) with other HOTLink  
devices. Each transmit (TX) channel of the CYV15G0204TRB  
HOTLink II device accepts scrambled 10-bit transmission  
characters. These characters are serialized and output from  
dual Positive ECL (PECL) compatible differential trans-  
mission-line drivers at a bit-rate of either 10- or 20-times the  
input reference clock for that channel.  
• Built-In Self-Test (BIST) for at-speed link testing  
• Link Quality Indicator  
— Analog signal detect  
— Digital signal detect  
• Low-power 2.5W @ 3.3V typical  
• Single 3.3V supply  
Figure 1. HOTLink II™ System Connections  
Independent  
Channel  
CYV15G0204TRB  
Independent  
Reclocked  
Outputs  
Channel  
CYV15G0204TRB  
Device  
Device  
10  
10  
10  
Serial Links  
10  
10  
10  
10  
Reclocked  
Outputs  
Cypress Semiconductor Corporation  
Document #: 38-02101 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 2, 2007  
[+] Feedback  
CYV15G0204TRB  
Each receive (RX) channel of the CYV15G0204TRB HOTLink  
II device accepts a serial bit-stream from one of two selectable  
PECL-compatible differential line receivers, and using a  
completely integrated Clock and Data Recovery PLL, recovers  
the timing information necessary for data reconstruction. The  
recovered bit-stream is reclocked and retransmitted through  
the reclocker serial outputs. Also, the recovered serial data is  
deserialized and presented to the destination host system.  
hardware allows at-speed testing of the high-speed serial data  
paths in each transmit and receive section, and across the  
interconnecting links.  
The CYV15G0204TRB is ideal for SMPTE applications where  
different data rates and serial interface standards are  
necessary for each channel. Some applications include  
multi-format routers, switchers, format converters, SDI  
monitors, cameras, and camera control units.  
Each transmit and receive channel contains an independent  
BIST pattern generator and checker, respectively. This BIST  
CYV15G0204TRB Logic Block Diagram  
x10  
x10  
x10  
x10  
Phase  
Align  
Buffer  
Phase  
Align  
Buffer  
Deserializer  
Deserializer  
Serializer  
Serializer  
TX  
RX  
RX  
TX  
Reclocker  
Reclocker  
Document #: 38-02101 Rev. *C  
Page 2 of 31  
[+] Feedback  
CYV15G0204TRB  
Serializer Path Block Diagram  
Bit-Rate Clock A  
OEA[2..1]  
= Internal Signal  
REFCLKA+  
REFCLKA–  
TXRATEA  
Transmit PLL  
Clock Multiplier A  
RESET  
SPDSELA  
TXCLKOA  
Character-Rate Clock A  
PABRSTA  
TXERRA  
TXCLKA  
OEA[2..1]  
TXBISTA  
0
1
TXCKSELA  
OUTA1+  
OUTA1–  
10  
10  
10  
TXDA[9:0]  
10  
OUTA2+  
OUTA2–  
Bit-Rate Clock B  
OEB[2..1]  
REFCLKB+  
REFCLKB–  
Transmit PLL  
TXRATEB  
Clock Multiplier B  
SPDSELB  
TXCLKOB  
Character-Rate Clock B  
PABRSTB  
TXERRB  
TXCLKB  
OEB[2..1]  
TXBISTB  
0
1
TXCKSELB  
OUTB1+  
OUTB1–  
10  
10  
10  
TXDB[9:0]  
10  
OUTB2+  
OUTB2–  
Document #: 38-02101 Rev. *C  
Page 3 of 31  
[+] Feedback  
CYV15G0204TRB  
= Internal Signal  
RESET  
Reclocking Deserializer Path Block Diagram  
TRST  
TRGRATEC  
JTAG  
Boundary  
Scan  
TMS  
TCLK  
TDI  
x2  
TRGCLKC  
Controller  
TDO  
SDASEL[2..1]C[1:0]  
LDTDEN  
INSELC  
LFIC  
Receive  
Signal  
Monitor  
10  
RXDC[9:0]  
BISTSTC  
10  
10  
INC1+  
INC1–  
Clock &  
Data  
Recovery  
PLL  
INC2+  
INC2–  
RXCLKC+  
RXCLKC–  
÷2  
ULCC  
SPDSELC  
RXBISTC[1:0]  
RXRATEC  
RXPLLPDC  
Recovered Serial Data  
Recovered Character Clock  
ROE[2..1]C  
Reclocker  
Output PLL  
Clock Multiplier C  
ROUTC1+  
ROUTC1–  
ROE[2..1]C  
ROUTC2+  
ROUTC2–  
RECLKOC  
REPDOC  
Character-Rate Clock C  
TRGRATED  
x2  
TRGCLKD  
SDASEL[2..1]D[1:0]  
LDTDEN  
INSELD  
LFID  
Receive  
Signal  
Monitor  
10  
RXDD[9:0]  
BISTSTD  
10  
10  
IND1+  
IND1–  
Clock &  
Data  
Recovery  
PLL  
IND2+  
IND2–  
RXCLKD+  
RXCLKD–  
÷2  
ULCD  
SPDSELD  
RXBISTD[1:0]  
RXRATED  
RXPLLPDD  
Recovered Serial Data  
Recovered Character Clock  
ROE[2..1]D  
Reclocker  
Output PLL  
Clock Multiplier D  
ROUTD1+  
ROUTD1–  
ROE[2..1]D  
ROUTD2+  
ROUTD2–  
RECLKOD  
REPDOD  
Character-Rate Clock D  
Document #: 38-02101 Rev. *C  
Page 4 of 31  
[+] Feedback  
CYV15G0204TRB  
Device Configuration and Control Block Diagram  
= Internal Signal  
TXRATE[A..B]  
TXCKSEL[A..B]  
PABRST[A..B]  
TOE[2..1][A..B]  
TXBIST[A..B]  
RXRATE[C..D]  
SDASEL[2..1][C..D][1:0]  
TRGRATE[C..D]  
RXPLLPD[C..D]  
WREN  
Device Configuration  
ADDR[3:0]  
and Control Interface  
DATA[6:0]  
RXBIST[C..D][1:0]  
ROE[2..1][C..D]  
Document #: 38-02101 Rev. *C  
Page 5 of 31  
[+] Feedback  
CYV15G0204TRB  
Pin Configuration (Top View)[1]  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
A
B
C
D
E
IN  
C1–  
ROUT  
C1–  
IN  
C2–  
ROUT  
C2–  
IN  
D1–  
ROUT  
D1–  
IN  
D2–  
ROUT  
D2–  
TOUT  
A1–  
TOUT  
A2–  
TOUT  
B1–  
TOUT  
B2–  
V
GND  
GND  
GND GND  
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
IN  
C1+  
ROUT  
C1+  
IN  
C2+  
ROUT  
C2+  
IN  
D1+  
ROUT  
D1+  
IN  
D2+  
ROUT  
D2+  
TOUT  
A1+  
TOUT  
A2+  
TOUT  
B1+  
TOUT  
B2+  
V
V
V
GND  
GND  
GND  
NC  
GND  
GND  
NC  
NC  
V
V
V
NC  
NC  
TDI  
TMS INSELC  
ULCD ULCC  
DATA  
[6]  
DATA  
[4]  
DATA  
[2]  
DATA  
[0]  
SPD  
SELD  
LDTD TRST  
EN  
TDO  
V
V
V
GND  
CC  
CC  
CC  
TCLK RESET INSELD  
SPD  
SELC  
DATA  
[5]  
DATA  
[3]  
DATA  
[1]  
SCAN TMEN3  
EN2  
V
GND GND GND  
NC  
NC  
V
CC  
CC  
CC  
V
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
F
G
H
RX  
RX  
TX  
CLKOB  
V
NC  
NC  
NC  
NC  
NC  
CC  
DC[8] DC[9]  
WREN  
GND  
SPD  
SELB  
SPD  
SELA  
GND GND  
GND GND GND GND  
GND GND GND GND  
GND GND GND GND  
J
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
K
L
RX  
TRG  
GND GND  
DC[4] CLKC–  
RX  
TRG  
LFIC  
TX  
DB[6]  
GND  
NC  
NC  
NC  
TX  
DC[5] CLKC+  
M
N
RX  
RX  
RE  
PDOC  
REF  
REF  
TX  
V
CC  
DC[6] DC[7]  
CLKB+ CLKB– ERRB CLKB  
GND GND GND GND  
GND GND GND GND  
P
R
T
RX  
RX  
RX  
RX  
TX  
DB[5]  
TX  
DB[4]  
TX  
DB[3]  
TX  
DB[2]  
DC[3] DC[2] DC[1] DC[0]  
BIST  
RE  
RX  
RX  
TX  
DB[1]  
TX  
DB[0]  
TX  
DB[9]  
TX  
DB[7]  
STC CLKOC CLKC+ CLKC–  
V
V
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
U
V
RX  
RX  
TX  
DA[9]  
ADDR  
[0]  
TRG  
CLKD– DA[1]  
TX  
TX  
DA[4]  
TX  
DA[8]  
TX  
DB[8]  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
V
V
V
V
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
DD[4] DD[3]  
RX  
DD[8]  
RX  
RX  
BIST ADDR  
STD [2]  
TRG TX  
CLKD+ CLKOA  
TX  
DA[3]  
TX  
DA[7]  
NC  
DD[5] DD[1]  
W
Y
LFID  
RX  
CLKD–  
RX  
RX  
ADDR ADDR  
[3]  
TX  
ERRA  
TX  
DA[2]  
TX  
DA[6]  
REF  
CLKA+  
NC  
NC  
RE  
DD[6] DD[0]  
[1]  
RX  
RX  
RX  
RX  
RE  
CLKOD  
TX  
CLKA  
TX  
DA[0]  
TX  
DA[5]  
REF  
NC  
NC  
DD[9] CLKD+  
DD[7] DD[2]  
PDOD CLKA–  
Note  
1. NC = Do not connect.  
Document #: 38-02101 Rev. *C  
Page 6 of 31  
[+] Feedback  
CYV15G0204TRB  
Pin Configuration (Bottom View)[1]  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
TOUT  
B2–  
TOUT  
B1–  
TOUT  
A2–  
TOUT  
A1–  
ROUT  
D2–  
IN  
D2–  
ROUT  
D1–  
IN  
D1–  
ROUT  
C2–  
IN  
C2–  
ROUT  
C1–  
IN  
C1–  
V
V
V
GND GND  
GND  
GND  
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
A
B
C
D
E
F
TOUT  
B2+  
TOUT  
B1+  
TOUT  
A2+  
TOUT  
A1+  
ROUT  
D2+  
IN  
D2+  
ROUT  
D1+  
IN  
D1+  
ROUT  
C2+  
IN  
C2+  
ROUT  
C1+  
IN  
C1+  
NC  
NC  
V
V
V
NC  
NC  
GND  
GND  
NC  
GND  
GND  
GND  
V
V
V
TDO  
TRST LDTD  
EN  
SPD  
SELD  
DATA  
[0]  
DATA  
[2]  
DATA  
[4]  
DATA  
[6]  
ULCC ULCD  
INSELC TMS  
TDI  
GND  
V
V
V
V
CC  
CC  
CC  
CC  
TMEN3 SCAN  
EN2  
DATA  
[1]  
DATA  
[3]  
DATA  
[5]  
SPD  
SELC  
INSELD RESET TCLK  
V
V
NC  
NC  
GND GND GND  
V
CC  
CC  
CC  
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
TX  
CLKOB  
RX  
RX  
NC  
NC  
NC  
NC  
NC  
CC  
DC[9] DC[8]  
SPD  
SELA  
SPD  
SELB  
WREN  
GND  
GND GND  
G
H
J
GND GND GND GND  
GND GND GND GND  
GND GND GND GND  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
TRG  
CLKC– DC[4]  
RX  
GND GND  
K
L
TX  
DB[6]  
LFIC  
TRG  
CLKC+ DC[5]  
RX  
NC  
TX  
NC  
NC  
GND  
TX  
REF  
REF  
RE  
PDOC  
RX  
RX  
V
CC  
M
N
P
R
T
CLKB ERRB CLKB– CLKB+  
DC[7] DC[6]  
GND GND GND GND  
GND GND GND GND  
TX  
DB[2]  
TX  
DB[3]  
TX  
DB[4]  
TX  
DB[5]  
RX  
RX  
RX  
RX  
DC[0] DC[1] DC[2] DC[3]  
TX  
DB[7]  
TX  
DB[9]  
TX  
DB[0]  
TX  
DB[1]  
RX  
RX  
RE  
BIST  
CLKC– CLKC+ CLKOC STC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
TX  
DB[8]  
TX  
DA[8]  
TX  
DA[4]  
TX  
TRG  
ADDR  
[0]  
TX  
DA[9]  
RX  
RX  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
V
V
V
V
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
U
V
W
Y
DA[1] CLKD–  
DD[3] DD[4]  
TX  
DA[7]  
TX  
DA[3]  
TX  
TRG  
ADDR BIST  
[2] STD  
RX  
RX  
RX  
DD[8]  
NC  
CLKOA CLKD+  
DD[1] DD[5]  
REF  
CLKA+  
TX  
DA[6]  
TX  
DA[2]  
TX  
ERRA  
ADDR ADDR  
[1]  
RX  
RX  
RX  
CLKD–  
LFID  
NC  
RE  
NC  
[3]  
DD[0] DD[6]  
REF  
CLKA– PDOD  
TX  
DA[5]  
TX  
DA[0]  
TX  
CLKA  
RE  
CLKOD  
RX  
RX  
RX  
RX  
NC  
NC  
DD[2] DD[7]  
CLKD+ DD[9]  
Document #: 38-02101 Rev. *C  
Page 7 of 31  
[+] Feedback  
CYV15G0204TRB  
Pin Definitions  
CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer  
Name  
I/O Characteristics Signal Description  
Transmit Path Data and Status Signals  
TXDA[7:0]  
TXDB[7:0]  
LVTTL Input,  
synchronous,  
sampled by the  
associated  
Transmit Data Inputs. TXDx[9:0] data inputs are captured on the rising edge of the  
transmit interface clock. The transmit interface clock is selected by the TXCKSELx  
latch via the device configuration interface.  
TXCLKx↑ or  
REFCLKx↑[2]  
TXERRA  
TXERRB  
LVTTL Output,  
synchronous to  
Transmit Path Error. TXERRx is asserted HIGH to indicate detection of a transmit  
Phase-Align Buffer underflow or overflow. If an underflow or overflow condition is  
detected, TXERRx, for the channel in error, is asserted HIGH and remains asserted  
until the transmit Phase-Align Buffer is re-centered with the PABRSTx latch via the  
device configuration interface. When TXBISTx = 0, the BIST progress is presented  
on the associated TXERRx output. The TXERRx signal pulses HIGH for one  
REFCLKx↑ [3]  
,
asynchronous to  
transmit channel  
enable / disable,  
asynchronoustoloss transmit-character clock period to indicate a pass through the BIST sequence once  
or return of  
every 511 character times.  
REFCLKx±  
TXERRx is also asserted HIGH, when any of the following conditions is true:  
• The TXPLL for the associated channel is powered down. This occurs when OE2x  
and OE1x for a given channel are both disabled by setting OE2x = 0 and OE1x = 0.  
• The absence of the REFCLKx± signal.  
Transmit Path Clock Signals  
REFCLKA±  
REFCLKB±  
Differential LVPECL Reference Clock. REFCLKx± clock inputs are used as the timing references for the  
or single-ended  
transmit PLL. These input clocks may also be selected to clock the transmit parallel  
interface. When driven by a single-ended LVCMOS or LVTTL clock source, connect  
the clock source to either the true or complement REFCLKx input, and leave the  
alternate REFCLKx input open (floating). When driven by an LVPECL clock source,  
the clock must be a differential clock, using both inputs.  
LVTTL input clock  
TXCLKA  
TXCLKB  
LVTTL Clock Input, Transmit Path Input Clock. When configuration latch TXCKSELx = 0, the  
internal pull-down  
associated TXCLKx input is selected as the character-rate input clock for the  
TXDx[9:0] input. In this mode, the TXCLKx input must be frequency-coherent to its  
associated TXCLKOx output clock, but may be offset in phase by any amount. Once  
initialized, TXCLKx is allowed to drift in phase as much as ±180 degrees. If the input  
phase of TXCLKx drifts beyond the handling capacity of the Phase Align Buffer,  
TXERRx is asserted to indicate the loss of data, and remains asserted until the  
Phase Align Buffer is initialized. The phase of the TXCLKx input clock relative to its  
associated REFCLKx± is initialized when the configuration latch PABRSTx is written  
as 0. When the associated TXERRx is deasserted, the Phase Align Buffer is  
initialized and input characters are correctly captured.  
TXCLKOA  
TXCLKOB  
LVTTL Output  
Transmit Clock Output. TXCLKOx output clock is synthesized by each channel’s  
transmit PLL and operates synchronous to the internal transmit character clock.  
TXCLKOx operates at either the same frequency as REFCLKx± (TXRATEx = 0), or  
at twice the frequency of REFCLKx± (TXRATEx = 1). The transmit clock outputs  
have no fixed phase relationship to REFCLKx±.  
Notes  
2. When REFCLKx± is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKx±.  
3. When REFCLKx± is configured for half-rate operation, these outputs are presented relative to both the rising and falling edges of the associated REFCLKx±.  
Document #: 38-02101 Rev. *C  
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CYV15G0204TRB  
Pin Definitions (continued)  
CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer  
Name  
I/O Characteristics Signal Description  
Receive Path Data and Status Signals  
RXDC[9:0]  
RXDD[9:0]  
LVTTL Output,  
Parallel Data Output. RXDx[9:0] parallel data outputs change relative to the receive  
synchronous to the interface clock. If RXCLKx± is a full-rate clock, the RXCLKx± clock outputs are  
RXCLK± output  
complementary clocks operating at the character rate. The RXDx[9:0] outputs for the  
associated receive channels follow rising edge of RXCLKx+ or falling edge of  
RXCLKx–. If RXCLKx± is a half-rate clock, the RXCLKx± clock outputs are comple-  
mentary clocks operating at half the character rate. The RXDx[9:0] outputs for the  
associated receive channels follow both the falling and rising edges of the associated  
RXCLKx± clock outputs.  
When BIST is enabled on the receive channel, the BIST status is presented on the  
RXDx[1:0] and BISTSTx outputs. See Table 6 on page 19 for each status reported  
by the BIST state machine. Also, while BIST is enabled, the RXDx[9:2] outputs  
should be ignored.  
BISTSTC  
BISTSTD  
LVTTL Output,  
BIST Status Output. When RXBISTx[1:0] = 10, BISTSTx (along with RXDx[1:0])  
synchronous to the displays the status of the BIST reception. See Table 6 on page 19 for the BIST status  
RXCLKx ± output  
reported for each combination of BISTSTx and RXDx[1:0].  
When RXBISTx[1:0] ≠ 10, BISTSTx should be ignored.  
REPDOC  
REPDOD  
Asynchronous to  
reclocker output  
channel  
Reclocker Powered Down Status Output. REPDOx is asserted HIGH, when the  
associated channel’s reclocker output logic is powered down. This occurs when  
ROE2x and ROE1x are both disabled by setting ROE2x = 0 and ROE1x = 0.  
enable / disable  
Receive Path Clock Signals  
TRGCLKC±  
TRGCLKD±  
Differential LVPECL CDR PLL Training Clock. TRGCLKx± clock inputs are used as the reference source  
or single-ended  
for the frequency detector (Range Controller) of the associated receive PLL to  
reduce PLL acquisition time.  
LVTTL input clock  
In the presence of valid serial data, the recovered clock output of the receive CDR  
PLL (RXCLKx±) has no frequency or phase relationship with TRGCLKx±.  
When driven by a single-ended LVCMOS or LVTTL clock source, connect the clock  
source to either the true or complement TRGCLKx input, and leave the alternate  
TRGCLKx input open (floating). When driven by an LVPECL clock source, the clock  
must be a differential clock, using both inputs.  
RXCLKC±  
RXCLKD±  
LVTTL Output Clock Receive Clock Output. RXCLKx± is the receive interface clock used to control  
timing of the RXDx[9:0] parallel outputs. These true and complement clocks are used  
to control timing of data output transfers. These clocks are output continuously at  
either the half-character rate (1/20th the serial bit-rate) or character rate (1/10th the  
serial bit-rate) of the data being received, as selected by RXRATEx.  
RECLKOC  
RECLKOD  
LVTTL Output  
Reclocker Clock Output. RECLKOx output clock is synthesized by the associated  
reclocker output PLL and operates synchronous to the internal recovered character  
clock. RECLKOx operates at either the same frequency as RXCLKx± (RXRATEx =  
0), or at twice the frequency of RXCLKx± (RXRATEx = 1).The reclocker clock outputs  
have no fixed phase relationship to RXCLKx±.  
Device Control Signals  
RESET LVTTL Input,  
Asynchronous Device Reset. RESET initializes all state machines, counters, and  
configuration latches in the device to a known state. RESET must be asserted LOW  
for a minimum pulse width. When the reset is removed, all state machines, counters  
and configuration latches are at an initial state. As per the JTAG specifications the  
device RESET cannot reset the JTAG controller. Therefore, the JTAG controller has  
to be reset separately. Refer to “JTAG Support” on page 19 for the methods to reset  
the JTAG state machine. See Table 4 on page 16 for the initialize values of the device  
configuration latches.  
asynchronous,  
internal pull-up  
Document #: 38-02101 Rev. *C  
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CYV15G0204TRB  
Pin Definitions (continued)  
CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer  
Name  
I/O Characteristics Signal Description  
LDTDEN  
LVTTL Input,  
internal pull-up  
Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal Level  
Detector, Range Controller, and Transition Density Detector are all enabled to  
determine if the RXPLL tracks TRGCLKx± or the selected input serial data stream.  
If the Signal Level Detector, Range Controller, or Transition Density Detector are out  
of their respective limits while LDTDEN is HIGH, the RXPLL locks to TRGCLKx± until  
such a time they become valid. The SDASEL[A..D][1:0] inputs are used to configure  
the trip level of the Signal Level Detector. The Transition Density Detector limit is one  
transition in every 60 consecutive bits. When LDTDEN is LOW, only the Range  
Controller is used to determine if the RXPLL tracks TRGCLKx± or the selected input  
serial data stream. It is recommended to set LDTDEN = HIGH.  
ULCC  
ULCD  
LVTTL Input,  
internal pull-up  
Use Local Clock. When ULCx is LOW, the RXPLL is forced to lock to TRGCLKx±  
instead of the received serial data stream. While ULCx is LOW, the LFIx for the  
associated channel is LOW indicating a link fault.  
When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on  
the input data streams. This function is used in applications in which a stable  
RXCLKx± is needed. In cases when there is an absence of valid data transitions for  
a long period of time, or the high-gain differential serial inputs (INx±) are left floating,  
there may be brief frequency excursions of the RXCLKx± outputs from TRGCLKx±.  
SPDSELA  
SPDSELB  
SPDSELC  
SPDSELD  
3-Level Select[4]  
static control input  
Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate range  
of each channel’s transmit (channels A and B) or receive PLL (channels C and D).  
LOW = 195 – 400 MBd  
MID = 400 – 800 MBd  
HIGH = 800 – 1500 MBd.  
INSELC  
INSELD  
LVTTL Input,  
asynchronous  
Receive Input Selector. The INSELx input determines which external serial bit  
stream is passed to the receiver’s Clock and Data Recovery circuit. When INSELx  
is HIGH, the Primary Differential Serial Data Input, INx1±, is selected for the  
associated receive channel. When INSELx is LOW, the Secondary Differential Serial  
Data Input, INx2±, is selected for the associated receive channel.  
LFIC  
LFID  
LVTTL Output,  
asynchronous  
Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the  
logical OR of six internal conditions. LFIx is asserted LOW when any of the following  
conditions is true:  
• Received serial data rate outside expected range  
• Analog amplitude below expected levels  
• Transition density lower than expected  
• Receive channel disabled  
• ULCx is LOW  
• Absence of TRGCLKx±.  
Device Configuration and Control Bus Signals  
WREN  
LVTTL input,  
asynchronous,  
Control Write Enable. The WREN input writes the values of the DATA[6:0] bus into  
the latch specified by the address location on the ADDR[3:0] bus.[5]  
internal pull-up  
ADDR[3:0]  
LVTTL input  
asynchronous,  
internal pull-up  
Control Addressing Bus. The ADDR[3:0] bus is the input address bus used to  
configure the device. The WREN input writes the values of the DATA[6:0] bus into  
the latch specified by the address location on the ADDR[3:0] bus.[5] Table 4 on page  
16 lists the configuration latches within the device, and the initialization value of the  
latches upon the assertion of RESET. Table 5 on page 18 shows how the latches are  
mapped in the device.  
Notes  
4. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually  
implemented by direct connection to V (ground). The HIGH level is usually implemented by direct connection to V (power). The MID level is usually  
SS  
CC  
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.  
5. See Device Configuration and Control Interface for detailed information on the operation of the Configuration Interface.  
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CYV15G0204TRB  
Pin Definitions (continued)  
CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer  
Name  
I/O Characteristics Signal Description  
DATA[6:0]  
LVTTL input  
asynchronous,  
internal pull-up  
Control Data Bus. The DATA[6:0] bus is the input data bus used to configure the  
device. The WREN input writes the values of the DATA[6:0] bus into the latch  
specified by address location on the ADDR[3:0] bus.[5] Table 4 on page 16 lists the  
configuration latches within the device, and the initialization value of the latches upon  
the assertion of RESET. Table 5 on page 18 shows how the latches are mapped in  
the device.  
Internal Device Configuration Latches  
RXRATE[C..D]  
Internal Latch[6]  
Receive Clock Rate Select.  
SDASEL[2..1][C..D] Internal Latch[6]  
[1:0]  
Signal Detect Amplitude Select.  
TXCKSEL[A..B]  
TXRATE[A..B]  
TRGRATE[C..D]  
RXPLLPD[C..D]  
Internal Latch[6]  
Internal Latch[6]  
Internal Latch[6]  
Internal Latch[6]  
Transmit Clock Select.  
Transmit PLL Clock Rate Select.  
Reclocker Output PLL Clock Rate Select.  
Receive Channel Power Control.  
RXBIST[C..D][1:0] Internal Latch[6]  
Receive Bist Disabled.  
TXBIST[A..B]  
TOE2[A..B]  
Internal Latch[6]  
Internal Latch[6]  
Internal Latch[6]  
Internal Latch[6]  
Internal Latch[6]  
Internal Latch[6]  
Transmit Bist Disabled.  
Transmitter Differential Serial Output Driver 2 Enable.  
Transmitter Differential Serial Output Driver 1 Enable.  
Reclocker Differential Serial Output Driver 2 Enable.  
Reclocker Differential Serial Output Driver 1 Enable.  
Transmit Clock Phase Alignment Buffer Reset.  
TOE1[A..B]  
ROE2[C..D]  
ROE1[C..D]  
PABRSTB[A..B]  
Factory Test Modes  
SCANEN2  
LVTTL input,  
internal pull-down  
Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as  
a NO CONNECT, or GND only.  
TMEN3  
LVTTL input,  
internal pull-down  
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a  
NO CONNECT, or GND only.  
Analog I/O  
TOUTA1±  
TOUTB1±  
CML Differential  
Output  
Transmitter Primary Differential Serial Data Output. The transmitter TOUTx1±  
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated  
transmission lines or standard fiber-optic transmitter modules, and must be  
AC-coupled for PECL-compatible connections.  
TOUTA2±  
TOUTB2±  
CML Differential  
Output  
Transmitter Secondary Differential Serial Data Output. The transmitter TOUTx2±  
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-  
mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for  
PECL-compatible connections.  
ROUTC1±  
ROUTD1±  
CML Differential  
Output  
Reclocker Primary Differential Serial Data Output. The reclocker ROUTx1±  
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated  
transmission lines or standard fiber-optic transmitter modules, and must be  
AC-coupled for PECL-compatible connections.  
ROUTC2±  
ROUTD2±  
CML Differential  
Output  
Reclocker Secondary Differential Serial Data Output. The reclocker ROUTx2±  
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-  
mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for  
PECL-compatible connections.  
INC1±  
IND1±  
Differential Input  
Primary Differential Serial Data Input. The INx1± input accepts the serial data  
stream for deserialization. The INx1± serial stream is passed to the receive CDR  
circuit to extract the data content when INSELx = HIGH.  
Note  
6. See Device Configuration and Control Interface for detailed information on the internal latches.  
Document #: 38-02101 Rev. *C  
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CYV15G0204TRB  
Pin Definitions (continued)  
CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer  
Name  
I/O Characteristics Signal Description  
INC2±  
IND2±  
Differential Input  
Secondary Differential Serial Data Input. The INx2± input accepts the serial data  
stream for deserialization. The INx2± serial stream is passed to the receiver CDR  
circuit to extract the data content when INSELx = LOW.  
JTAG Interface  
TMS  
LVTTL Input,  
internal pull-up  
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained  
high for ≥5 TCLK cycles, the JTAG test controller is reset.  
TCLK  
TDO  
TDI  
LVTTL Input,  
internal pull-down  
JTAG Test Clock.  
3-State LVTTL  
Output  
Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not  
selected.  
LVTTL Input,  
internal pull-up  
Test Data In. JTAG data input port.  
TRST  
LVTTL Input,  
internal pull-up  
JTAG reset signal. When asserted (LOW), this input asynchronously resets the  
JTAG test access port controller.  
Power  
VCC  
+3.3V Power.  
GND  
Signal and Power Ground for all internal circuits.  
of the Phase-Align Buffer, an error is reported on that  
CYV15G0204TRB HOTLink II Operation  
channel’s TXERRx output. This output indicates an error  
continuously until the Phase-Align Buffer for that channel is  
reset. While the error remains active, the transmitter for that  
channel outputs a continuous “1001111000” character to  
indicate to the remote receiver that an error condition is  
present in the link.  
The CYV15G0204TRB is a highly configurable, independent  
clocking, device designed to support reliable transfer of large  
quantities of digital video data, using high-speed serial links  
from multiple sources to multiple destinations.  
CYV15G0204TRB Transmit Data Path  
Transmit BIST  
Input Register  
Each transmit channel contains an internal pattern generator  
that can be used to validate both the link and device operation.  
These generators are enabled by the associated TXBISTx  
latch via the device configuration interface. When enabled, a  
register in the associated transmit channel becomes a  
signature pattern generator by logically converting to a Linear  
Feedback Shift Register (LFSR). This LFSR generates a  
511-character sequence. This provides a predictable yet  
pseudo-random sequence that can be matched to an identical  
LFSR in the attached Receiver(s).  
The parallel input bus TXDx[9:0] can be clocked in using  
TXCLKx (TXCKSELx = 0) or REFCLKx (TXCKSELx = 1).  
Phase-Align Buffer  
Data from each Input Register is passed to the associated  
Phase-Align Buffer, when the TXDx[9:0] input registers are  
clocked using TXCLKx (TXCKSELx = 0 and TXRATEx = 0).  
When the TXDx[9:0] input registers are clocked using  
REFCLKx± (TXCKSELx = 1) and REFCLKx± is a full-rate  
clock, the associated Phase Alignment Buffer in the transmit  
path is bypassed. These buffers are used to absorb clock  
phase differences between the TXCLKx input clock and the  
internal character clock for that channel.  
A device reset (RESET sampled LOW) presets the BIST  
Enable Latches to disable BIST on both channels.  
All data present at the associated TXDx[9:0] inputs are ignored  
when BIST is active on that channel.  
Once initialized, TXCLKx is allowed to drift in phase as much  
as ±180 degrees. If the input phase of TXCLKx drifts beyond  
the handling capacity of the Phase Align Buffer, TXERRx is  
asserted to indicate the loss of data, and remains asserted  
until the Phase Align Buffer is initialized. The phase of the  
TXCLKx relative to its associated internal character rate clock  
is initialized when the configuration latch PABRSTx is written  
as 0. When the associated TXERRx is deasserted, the Phase  
Align Buffer is initialized and input characters are correctly  
captured.  
Transmit PLL Clock Multiplier  
Each Transmit PLL Clock Multiplier accepts a character-rate  
or half-character-rate external clock at the associated  
REFCLKx± input, and that clock is multiplied by 10 or 20 (as  
selected by TXRATEx) to generate a bit-rate clock for use by  
the transmit shifter. It also provides a character-rate clock used  
by the transmit paths, and outputs this character rate clock as  
TXCLKOx.  
Each clock multiplier PLL can accept a REFCLKx± input  
between 19.5 MHz and 150 MHz, however, this clock range is  
limited by the operating mode of the CYV15G0204TRB clock  
If the phase offset, between the initialized location of the input  
clock and REFCLKx, exceeds the skew handling capabilities  
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CYV15G0204TRB  
multiplier (TXRATEx) and by the level on the associated  
SPDSELx input.  
Note. When a disabled transmit channel (i.e., both outputs  
disabled) is re-enabled:  
SPDSELx are 3-level select[4] inputs that select one of three  
operating ranges for the serial data outputs and inputs of the  
associated channel. The operating serial signaling-rate and  
allowable range of REFCLKx± frequencies are listed in  
Table 1.  
• data on the serial outputs may not meet all timing specifi-  
cations for up to 250 μs  
• the state of the phase-align buffer cannot be guaranteed,  
and a phase-align reset is required if the phase-align buffer  
is used  
Table 1. Operating Speed Settings  
CYV15G0204TRB Receive Data Path  
REFCLKx±  
Signaling  
Serial Line Receivers  
SPDSELx  
TXRATEx  
Frequency  
(MHz)  
Rate (Mbps)  
Two differential Line Receivers, INx1± and INx2±, are  
available on each channel for accepting serial data streams.  
The active Serial Line Receiver on a channel is selected using  
the associated INSELx input. The Serial Line Receiver inputs  
are differential, and can accommodate wire interconnect and  
filtering losses or transmission line attenuation greater than  
16 dB. For normal operation, these inputs should receive a  
signal of at least VIDIFF > 100 mV, or 200 mV peak-to-peak  
differential. Each Line Receiver can be DC- or AC-coupled to  
+3.3V powered fiber-optic interface modules (any ECL/PECL  
family, not limited to 100K PECL) or AC-coupled to +5V  
powered optical modules. The common-mode tolerance of  
these line receivers accommodates a wide range of signal  
termination voltages. Each receiver provides internal  
DC-restoration, to the center of the receiver’s common mode  
range, for AC-coupled signals.  
LOW  
1
0
1
0
1
0
reserved  
19.5–40  
20–40  
195–400  
MID (Open)  
HIGH  
400–800  
40–80  
40–75  
800–1500  
80–150  
The REFCLKx± inputs are differential inputs with each input  
internally biased to 1.4V. If the REFCLKx+ input is connected  
to a TTL, LVTTL, or LVCMOS clock source, the input signal is  
recognized when it passes through the internally biased  
reference point. When driven by a single-ended TTL, LVTTL,  
or LVCMOS clock source, connect the clock source to either  
the true or complement REFCLKx input, and leave the  
alternate REFCLKx input open (floating).  
Signal Detect/Link Fault  
Each selected Line Receiver (i.e., that routed to the clock and  
data recovery PLL) is simultaneously monitored for  
When both the REFCLKx+ and REFCLKx– inputs are  
connected, the clock source must be a differential clock. This  
can either be a differential LVPECL clock that is DC-or  
AC-coupled or a differential LVTTL or LVCMOS clock.  
• analog amplitude above amplitude level selected by  
SDASELx  
• transition density above the specified limit  
By connecting the REFCLKx– input to an external voltage  
source, it is possible to adjust the reference point of the  
REFCLKx+ input for alternate logic levels. When doing so, it  
is necessary to ensure that the input differential crossing point  
remains within the parametric range supported by the input.  
• range controls report the received data stream inside  
normal frequency range (±1500 ppm[23]  
)
• receive channel enabled  
• Presence of reference clock  
• ULCx is not asserted.  
Transmit Serial Output Drivers  
The serial output interface drivers use differential Current  
Mode Logic (CML) drivers to provide source-matched drivers  
for 50Ω transmission lines. These drivers accept data from the  
Transmit Shifters. These drivers have signal swings equivalent  
to that of standard PECL drivers, and are capable of driving  
AC-coupled optical modules or transmission lines.  
All of these conditions must be valid for the Signal Detect block  
to indicate a valid signal is present. This status is presented on  
the LFIx (Link Fault Indicator) output associated with each  
receive channel, which changes synchronous to the receive  
interface clock.  
Analog Amplitude  
Transmit Channels Enabled  
While most signal monitors are based on fixed constants, the  
analog amplitude level detection is adjustable to allow  
operation with highly attenuated signals, or in high-noise  
environments. The analog amplitude level detection is set by  
the SDASELx latch via device configuration interface. The  
SDASELx latch sets the trip point for the detection of a valid  
signal at one of three levels, as listed in Table 2. This control  
input affects the analog monitors for both receive channels.  
The Analog Signal Detect monitors are active for the Line  
Receiver as selected by the associated INSELx input.  
Each driver can be enabled or disabled separately via the  
device configuration interface.  
When a driver is disabled via the configuration interface, it is  
internally powered down to reduce device power. If both serial  
drivers for a channel are in this disabled state, the associated  
internal logic for that channel is also powered down. A device  
reset (RESET sampled LOW) disables all output drivers.  
Document #: 38-02101 Rev. *C  
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CYV15G0204TRB  
Table 2. Analog Amplitude Detect Valid Signal Levels[7]  
SDASEL Typical Signal with Peak Amplitudes Above  
Receive Channel Enabled  
The CYV15G0204TRB contains two receive channels that can  
be independently enabled and disabled. Each channel can be  
enabled or disabled separately through the RXPLLPDx input  
latch as controlled by the device configuration interface. When  
the RXPLLPDx latch = 0, the associated PLL and analog  
circuitry of the channel is disabled. Any disabled channel  
indicates a constant link fault condition on the LFIx output.  
When RXPLLPDx = 1, the associated PLL and receive  
channel is enabled to receive a serial stream.  
00  
01  
10  
11  
Analog Signal Detector is disabled  
140 mV p-p differential  
280 mV p-p differential  
420 mV p-p differential  
Transition Density  
The Transition Detection logic checks for the absence of  
transitions spanning greater than six transmission characters  
(60 bits). If no transitions are present in the data received, the  
Detection logic for that channel asserts LFIx.  
When a disabled receive channel is reenabled, the status of  
the associated LFIx output and data on the parallel outputs for  
the associated channel may be indeterminate for up to 2 ms.  
Clock/Data Recovery  
Range Controls  
The extraction of a bit-rate clock and recovery of bits from each  
received serial stream is performed by a separate CDR block  
within each receive channel. The clock extraction function is  
performed by an integrated PLL that tracks the frequency of  
the transitions in the incoming bit stream and align the phase  
of the internal bit-rate clock to the transitions in the selected  
serial data stream.  
The CDR circuit includes logic to monitor the frequency of the  
PLL Voltage Controlled Oscillator (VCO) used to sample the  
incoming data stream. This logic ensures that the VCO  
operates at, or near the rate of the incoming data stream for  
two primary cases:  
• when the incoming data stream resumes after a time in  
which it has been “missing.”  
Each CDR accepts a character-rate (bit-rate ÷ 10) or  
half-character-rate (bit-rate ÷ 20) training clock from the  
associated TRGCLKx± input. This TRGCLKx± input is used to  
• when the incoming data stream is outside the acceptable  
signaling rate range.  
• ensure that the VCO (within the CDR) is operating at the  
correct frequency (rather than a harmonic of the bit-rate)  
To perform this function, the frequency of the RXPLL VCO is  
periodically compared to the frequency of the TRGCLKx±  
input. If the VCO is running at a frequency beyond  
±1500 ppm[23] as defined by the TRGCLKx± frequency, it is  
periodically forced to the correct frequency (as defined by  
TRGCLKx±, SPDSELx, and TRGRATEx) and then released in  
an attempt to lock to the input data stream.  
• reduce PLL acquisition time  
• limit unlocked frequency excursions of the CDR VCO when  
there is no input data present at the selected Serial Line  
Receiver.  
Regardless of the type of signal present, the CDR attempts to  
recover a data stream from it. If the signalling rate of the  
recovered data stream is outside the limits set by the range  
control monitors, the CDR tracks TRGCLKx± instead of the  
data stream. Once the CDR output (RXCLK±) frequency  
returns back close to TRGCLKx± frequency, the CDR input is  
switched back to the input data stream. If no data is present at  
the selected line receiver, this switching behavior may result  
in brief RXCLK± frequency excursions from TRGCLKx±.  
However, the validity of the input data stream is indicated by  
the LFIx output. The frequency of TRGCLKx± is required to be  
within ±1500ppm[23] of the frequency of the clock that drives  
the REFCLKx± input of the remote transmitter to ensure a lock  
to the incoming data stream. This large ppm tolerance allows  
the CDR PLL to reliably receive a 1.485 or 1.485/1.001 Gbps  
SMPTE HD-SDI data stream with a constant TRGCLK  
frequency.  
The sampling and relock period of the Range Control is calcu-  
lated as follows: RANGE_CONTROL_ SAMPLING_PERIOD  
= (RECOVERED BYTE CLOCK PERIOD) * (4096).  
During the time that the Range Control forces the RXPLL VCO  
to track TRGCLKx±, the LFIx output is asserted LOW. After a  
valid serial data stream is applied, it may take up to one  
RANGE CONTROL SAMPLING PERIOD before the PLL  
locks to the input data stream, after which LFIx should be  
HIGH.  
The operating serial signaling-rate and allowable range of  
TRGCLK± frequencies are listed in Table 3.  
Table 3. Operating Speed Settings  
TRGCLKx±  
Signaling  
SPDSELx TRGRATEx  
Frequency  
(MHz)  
Rate (Mbps)  
LOW  
MID (Open)  
HIGH  
1
0
1
0
1
0
reserved  
19.5–40  
20–40  
195 – 400  
For systems using multiple or redundant connections, the LFIx  
output can be used to select an alternate data stream. When  
an LFIx indication is detected, external logic can toggle  
selection of the associated INx1± and INx2± input through the  
associated INSELx input. When a port switch takes place, it is  
necessary for the receive PLL for that channel to reacquire the  
new serial stream.  
400–800  
40–80  
40–75  
800–1500  
80–150  
Note  
7. The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals  
may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase  
the values in the table above by approximately 100 mV.  
Document #: 38-02101 Rev. *C  
Page 14 of 31  
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CYV15G0204TRB  
Reclocker  
machine aborts the compare operations and resets the LFSR  
to look for the start of the BIST sequence again.  
Each receive channel performs a reclocker function on the  
incoming serial data. To do this, the Clock and Data Recovery  
PLL first recovers the clock from the data. The data is retimed  
by the recovered clock and then passed to an output register.  
Also, the recovered character clock from the receive PLL is  
passed to the reclocker output PLL which generates the bit  
clock that is used to clock the retimed data into the output  
register. This data stream is then transmitted through the  
differential serial outputs.  
A device reset (RESET sampled LOW) presets the BIST  
Enable Latches to disable BIST on both channels.  
BIST Status State Machine  
When a receive path is enabled to look for and compare the  
received data stream with the BIST pattern, the {BISTSTx,  
RXDx[0], RXDx[1]} bits identify the present state of the BIST  
compare operation.  
The BIST state machine has multiple states, as shown in  
Figure 2 on page 20 and Table 6 on page 19. When the receive  
PLL detects an out-of-lock condition, the BIST state is forced  
to the Start-of-BIST state, regardless of the present state of the  
BIST state machine. If the number of detected errors ever  
exceeds the number of valid matches by greater than 16, the  
state machine is forced to the WAIT_FOR_BIST state where  
it monitors the receive path for the first character of the next  
BIST sequence.  
Reclocker Serial Output Drivers  
The serial output interface drivers use differential Current  
Mode Logic (CML) drivers to provide source-matched drivers  
for 50Ω transmission lines. These drivers accept data from the  
reclocker output register in the reclocker channel. These  
drivers have signal swings equivalent to that of standard PECL  
drivers, and are capable of driving AC-coupled optical  
modules or transmission lines.  
Reclocker Output Channels Enabled  
Power Control  
Each driver can be enabled or disabled separately via the  
device configuration interface.  
The CYV15G0204TRB supports user control of the powered  
up or down state of each transmit and receive channel. The  
receive channels are controlled by the RXPLLPDx latch via the  
device configuration interface. When RXPLLPDx = 0, the  
associated PLL and analog circuitry of the channel is disabled.  
The transmit channels are controlled by the TOE1x and the  
TOE2x latches via the device configuration interface. The  
reclocker function is controlled by the ROE1x and the ROE2x  
latches via the device configuration interface. When a driver is  
disabled via the configuration interface, it is internally powered  
down to reduce device power. If both serial drivers for a  
channel are in this disabled state, the associated internal logic  
for that channel is also powered down. When the reclocker  
serial drivers are disabled, the reclocker function will be  
disabled, but the deserialization logic and parallel outputs will  
remain enabled.  
When a driver is disabled via the configuration interface, it is  
internally powered down to reduce device power. If both  
reclocker serial drivers for a channel are in this disabled state,  
the associated internal reclocker logic is also powered down.  
The deserialization logic and parallel outputs will remain  
enabled. A device reset (RESET sampled LOW) disables all  
output drivers.  
Note. When the disabled reclocker function (i.e., both outputs  
disabled) is re-enabled, the data on the reclocker serial  
outputs may not meet all timing specifications for up to 250 μs.  
Output Bus  
The receive channel presents a 10-bit data signal (and a BIST  
status signal when RXBISTx[1:0] = 10).  
Receive BIST Operation  
Device Reset State  
Each receiver channel contains an internal pattern checker  
that can be used to validate both device and link operation.  
These pattern checkers are enabled by the associated  
RXBISTx[1:0] latch via the device configuration interface.  
When enabled, a register in the associated receive channel  
becomes a signature pattern generator and checker by  
logically converting to a Linear Feedback Shift Register  
(LFSR). This LFSR generates a 511-character sequence. This  
provides a predictable yet pseudo-random sequence that can  
be matched to an identical LFSR in the attached Trans-  
mitter(s). When synchronized with the received data stream,  
the associated Receiver checks each character from the  
deserializer with each character generated by the LFSR and  
indicates compare errors and BIST status at the RXDx[1:0]  
and BISTSTx bits of the Output Register.  
When the CYV15G0204TRB is reset by assertion of RESET,  
all state machines, counters, and configuration latches in the  
device are initialized to a reset state. Additionally, the JTAG  
controller must also be reset for valid operation (even if JTAG  
testing is not performed). See “JTAG Support” on page 19 for  
JTAG state machine initialization. See Table 4 on page 16 for  
the initialize values of the configuration latches.  
Following a device reset, it is necessary to enable the receive  
channels used for normal operation. This can be done by  
sequencing the appropriate values on the device configuration  
interface.[5]  
Device Configuration and Control Interface  
The CYV15G0204TRB is highly configurable via the configu-  
ration interface. The configuration interface allows each  
channel to be configured independently. Table 4 on page 16  
lists the configuration latches within the device including the  
initialization value of the latches upon the assertion of RESET.  
Table 5 on page 18 shows how the latches are mapped in the  
device. Each row in the Table 5 maps to a 7-bit latch bank.  
The BIST status bus {BISTSTx, RXDx[0], RXDx[1]} indicates  
010b or 100b for one character period per BIST loop to  
indicate loop completion. This status can be used to check test  
pattern progress.  
If the number of invalid characters received ever exceeds the  
number of valid characters by 16, the receive BIST state  
Document #: 38-02101 Rev. *C  
Page 15 of 31  
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CYV15G0204TRB  
There are 12 such write-only latch banks. When WREN = 0,  
the logic value in the DATA[7:0] is latched to the latch bank  
specified by the values in ADDR[3:0]. The second column of  
Table 5 specifies the channels associated with the corre-  
sponding latch bank. For example, the first three latch banks  
(0,1 and 2) consist of configuration bits for channel A.  
The first and second rows of each channel (address numbers  
0, 1, 3, 4, 6, 7, 9, and 10) are the static control latches. The  
third row of latches for each channel (address numbers 2, 5,  
8, and 11) are the dynamic control latches that are associated  
with enabling dynamic functions within the device.  
Static Latch Values  
Latch Types  
There are some latches in the table that have a static value  
(i.e., 1, 0, or X). The latches that have a ‘1’ or ‘0’ must be  
configured with their corresponding value each time that their  
associated latch bank is configured. The latches that have an  
‘X’ are don’t cares and can be configured with any value.  
There are two types of latch banks: static (S) and dynamic (D).  
Each channel is configured by 2 static and 1 dynamic latch  
banks. The S type contain those settings that normally do not  
change for a given application, whereas the D type controls  
the settings that could change during the application's lifetime.  
Table 4. Device Configuration and Control Latch Descriptions  
Name  
Signal Description  
TXCKSELA  
TXCKSELB  
Transmit Clock Select. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock  
source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input register  
TXDx[9:0] is clocked by REFCLKx↑. In this mode, the phase alignment buffer in the transmit path is bypassed.  
When TXCKSELx = 0, the associated TXCLKx↑ is used to clock in the input register TXDx[9:0].  
TXRATEA  
TXRATEB  
Transmit PLL Clock Rate Select. The initialization value of the TXRATEx latch = 0. TXRATEx is used to  
select the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the  
associated REFCLKx± input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the TXCLKOx  
output clocks are full-rate clocks and follow the frequency and duty cycle of the associated REFCLKx± input.  
When TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx± input by 20 to generate the  
serial bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice the frequency rate of the  
REFCLKx± input. When TXCLKSELx = 1 and TXRATEx = 1, the Transmit Data Inputs are captured using  
both the rising and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx = LOW, is an invalid state and  
this combination is reserved.  
TXBISTA  
TXBISTB  
Transmit Bist Disabled. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit  
BIST is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When TXBISTx = 0,  
the transmit BIST function is enabled.  
TOE2A  
TOE2B  
Secondary Differential Serial Data Output Driver Enable. The initialization value of the TOE2x latch = 0.  
TOE2x selects if the TOUTx2± secondary differential output drivers are enabled or disabled. When TOE2x =  
1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter.  
When TOE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via the  
configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel  
are in this disabled state, the associated internal logic for that channel is also powered down. A device reset  
(RESET sampled LOW) disables all output drivers.  
TOE1A  
TOE1B  
Primary Differential Serial Data Output Driver Enable. The initialization value of the TOE1x latch = 0.  
TOE1x selects if the TOUTx1± primary differential output drivers are enabled or disabled. When TOE1x = 1,  
the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter.  
When TOE1x = 0, the associated serial data output driver is disabled. When a driver is disabled via the  
configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel  
are in this disabled state, the associated internal logic for that channel is also powered down. A device reset  
(RESET sampled LOW) disables all output drivers.  
PABRSTA  
PABRSTB  
Transmit Clock Phase Alignment Buffer Reset. The initialization value of the PABRSTx latch = 1. The  
PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx is  
written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized.  
PABRST is an asynchronous input, but is sampled by each TXCLKx↑ to synchronize it to the internal clock  
domain. PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete the  
initialization of the Phase Alignment Buffer.  
Document #: 38-02101 Rev. *C  
Page 16 of 31  
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CYV15G0204TRB  
Table 4. Device Configuration and Control Latch Descriptions (continued)  
Name  
Signal Description  
RXRATEC  
RXRATED  
Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx is used to select  
the rate of the RXCLKx± clock output.  
When RXRATEx = 1, the RXCLKx± clock outputs are complementary clocks that follow the recovered clock  
operating at half the character rate. Data for the associated receive channels should be latched alternately  
on the rising edge of RXCLKx+ and RXCLKx–.  
When RXRATEx = 0, the RXCLKx± clock outputs are complementary clocks that follow the recovered clock  
operating at the character rate. Data for the associated receive channels should be latched on the rising edge  
of RXCLKx+ or falling edge of RXCLKx–.  
SDASEL1C[1:0] Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the SDASEL1x[1:0]  
SDASEL1D[1:0] latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the INx1± Primary  
Differential Serial Data Inputs.  
When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.  
When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.  
When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.  
When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.  
SDASEL2C[1:0] Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the  
SDASEL2D[1:0] SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the INx2±  
Secondary Differential Serial Data Inputs.  
When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled  
When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.  
When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.  
When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.  
TRGRATEC  
TRGRATED  
Training Clock Rate Select. The initialization value of the TRGRATEx latch = 0. TRGRATEx is used to select  
the clock multiplier for the training clock input to the associated CDR PLL. When TRGRATEx = 0, the  
TRGCLKx± input is not multiplied before it is passed to the CDR PLL. When TRGRATEx = 1, the TRGCLKx±  
input is multiplied by 2 before it is passed to the CDR PLL. TRGRATEx = 1 and SPDSELx = LOW is an invalid  
state and this combination is reserved.  
RXPLLPDC  
RXPLLPDD  
Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects if the  
associated receive channel is enabled or powered-down. When RXPLLPDx = 0, the associated receive PLL  
and analogcircuitry are powered-down. When RXPLLPDx = 1, the associated receive PLL and analog circuitry  
are enabled.  
RXBISTC[1:0]  
RXBISTD[1:0]  
Receive Bist Disable / SMPTE Receive Enable. The initialization value of the RXBISTx[1:0] latch = 11. For  
SMPTE data reception, RXBISTx[1:0] should not remain in this initialization state (11). RXBISTx[1:0] selects  
if receive BIST is disabled or enabled and sets the associated channel for SMPTE data reception. When  
RXBISTx[1:0] = 01, the receiver BIST function is disabled and the associated channel is set to receive SMPTE  
data. When RXBISTx[1:0] = 10, the receive BIST function is enabled and the associated channel is set to  
receive BIST data. RXBISTx[1:0] = 00 and RXBISTx[1:0] = 11 are invalid states.  
ROE2C  
ROE2D  
Reclocker Secondary Differential Serial Data Output Driver Enable. The initialization value of the ROE2x  
latch = 0. ROE2x selects if the ROUTx2± secondary differential output drivers are enabled or disabled. When  
ROE2x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit  
shifter. When ROE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via  
the configuration interface, it is internally powered down to reduce device power. If both serial drivers for a  
channel are in this disabled state, the associated internal logic for that channel is also powered down. A device  
reset (RESET sampled LOW) disables all output drivers.  
ROE1C  
ROE1D  
Reclocker Primary Differential Serial Data Output Driver Enable. The initialization value of the ROE1x  
latch = 0. ROE1x selects if the ROUTx1± primary differential output drivers are enabled or disabled. When  
ROE1x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit  
shifter. When ROE1x = 0, the associated serial data output driver is disabled. When a driver is disabled via  
the configuration interface, it is internally powered down to reduce device power. If both serial drivers for a  
channel are in this disabled state, the associated internal logic for that channel is also powered down. A device  
reset (RESET sampled LOW) disables all output drivers.  
Document #: 38-02101 Rev. *C  
Page 17 of 31  
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CYV15G0204TRB  
Device Configuration Strategy  
3. Set the dynamic bank of latches for the target channel.  
Enable the Receive PLLs and transmit channels. If a  
receive channel is enabled, set the channel for SMPTE data  
reception (RXBISTA[1:0] = 01) or BIST data reception  
(RXBISTA[1:0] = 10).  
The following is a series of ordered events needed to load the  
configuration latches on a per channel basis:  
1. Pulse RESET Low after device power-up. This operation  
resets all four channels. Initialize the JTAG state machine  
to its reset state as detailed in “JTAG Support” on page 19.  
4. Reset the Phase Alignment Buffer for the target channel.  
[Optional if phase align buffer is bypassed.]  
2. Set the static latch banks for the target channel.  
Table 5. Device Control Latch Configuration Table  
Reset  
Value  
ADDR Channel Type  
DATA6  
DATA5  
DATA4  
DATA3  
DATA2  
DATA1  
DATA0  
0
A
A
A
B
B
B
C
C
C
D
D
D
S
S
D
S
S
D
S
S
D
S
S
D
X
X
X
X
X
0
X
1011111  
(0000b)  
1
X
X
X
X
0
TXCKSELA  
TXRATEA  
PABRSTA  
X
1010110  
1011001  
1011111  
1010110  
1011001  
1011111  
1010110  
1011001  
1011111  
1010110  
1011001  
(0001b)  
2
X
X
X
TXBISTA  
OE2A  
OE1A  
(0010b)  
3
X
X
X
X
X
0
(0011b)  
4
X
X
X
X
0
TXCKSELB  
TXRATEB  
PABRSTB  
RXRATEC  
TRGRATEC  
X
(0100b)  
5
X
X
X
TXBISTB  
OE2B  
OE1B  
(0101b)  
6
1
0
X
X
0
0
(0110b)  
7
SDASEL2C[1]  
RXBISTC[1]  
1
SDASEL2C[0]  
RXPLLPDC  
0
SDASEL1C[1]  
RXBISTC[0]  
X
SDASEL1C[0]  
X
ROE2C  
0
X
ROE1C  
0
(0111b)  
8
X
(1000b)  
9
X
RXRATED  
TRGRATED  
X
(1001b)  
10  
(1010b)  
SDASEL2D[1]  
RXBISTD[1]  
SDASEL2D[0]  
RXPLLPDD  
SDASEL1D[1]  
RXBISTD[0]  
SDASEL1D[0]  
X
X
X
11  
(1011b)  
ROE2D  
ROE1D  
12  
(1100b)  
13  
(1101b)  
INTERNAL TEST REGISTERS  
DO NOT WRITE TO THESE ADDRESSES  
14  
(1110b)  
15  
(1111b)  
Document #: 38-02101 Rev. *C  
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CYV15G0204TRB  
5 consecutive TCLK cycles. This is necessary in order to  
ensure that the JTAG controller does not enter any of the test  
modes after device power-up. In this JTAG reset state, the rest  
of the device will be in normal operation.  
JTAG Support  
The CYV15G0204TRB contains a JTAG port to allow system  
level diagnosis of device interconnect. Of the available JTAG  
modes, boundary scan, and bypass are supported. This  
capability is present only on the LVTTL inputs and outputs, the  
REFCLKx± clock inputs, and the TRGCLKx± clock inputs. The  
high-speed serial inputs and outputs are not part of the JTAG  
test chain.  
Note. The order of device reset (using RESET) and JTAG  
initialization does not matter.  
3-Level Select Inputs  
Each 3-Level select inputs reports as two bits in the scan  
register. These bits report the LOW, MID, and HIGH state of  
the associated input as 00, 10, and 11 respectively  
To ensure valid device operation after power-up (including  
non-JTAG operation), the JTAG state machine should also be  
initialized to a reset state. This should be done in addition to  
the device reset (using RESET). The JTAG state machine can  
be initialized using TRST (asserting it LOW and de-asserting  
it or leaving it asserted), or by asserting TMS HIGH for at least  
JTAG ID  
The JTAG device ID for the CYV15G0204TRB is ‘0C811069’x  
Table 6. Receive Character Status Bits  
{BISTSTx, RXDx[0], RXDx[1]}  
Description  
Receive BIST Status  
(Receive BIST = Enabled)  
000, 001  
010  
BIST Data Compare. Character compared correctly.  
BIST Last Good. Last Character of BIST sequence detected and valid.  
011  
Reserved.  
100  
BIST Last Bad. Last Character of BIST sequence detected invalid.  
101  
BIST Start. Receive BIST is enabled on this channel, but character compares have not yet  
commenced. This also indicates a PLL Out of Lock condition.  
110  
111  
BIST Error. While comparing characters, a mismatch was found in one or more of the  
character bits.  
BIST Wait. The receiver is comparing characters. but has not yet found the start of BIST  
character to enable the LFSR.  
Document #: 38-02101 Rev. *C  
Page 19 of 31  
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CYV15G0204TRB  
Figure 2. Receive BIST State Machine  
Monitor Data  
Receive BIST  
Received  
Detected LOW  
{BISTSTx, RXDx[0],  
RXDx[1]} =  
BIST_START (101)  
RX PLL  
Out of Lock  
{BISTSTx, RXDx[0], RXDx[1]} =  
BIST_WAIT (111)  
Start of  
BIST Detected  
No  
Yes, {BISTSTx, RXDx[0], RXDx[1]} =  
BIST_DATA_COMPARE (000, 001)  
Compare  
Next Character  
Mismatch  
{BISTSTx, RXDx[0], RXDx[1]} =  
BIST_DATA_COMPARE (000, 001)  
Match  
Auto-Abort  
Condition  
Yes  
No  
End-of-BIST  
State  
End-of-BIST  
State  
No  
Yes, {BISTSTx, RXDx[0], RXDx[1]} =  
BIST_LAST_BAD (100)  
Yes, {BISTSTx, RXDx[0], RXDx[1]} =  
BIST_LAST_GOOD (010)  
No, {BISTSTx, RXDx[0], RXDx[1]} =  
BIST_ERROR (110)  
Document #: 38-02101 Rev. *C  
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CYV15G0204TRB  
Static Discharge Voltage..........................................> 2000 V  
(per MIL-STD-883, Method 3015)  
Maximum Ratings  
(Above which the useful life may be impaired. User guidelines  
only, not tested.)  
Latch-up Current.....................................................> 200 mA  
Power-up Requirements  
Storage Temperature ..................................–65°C to +150°C  
The CYV15G0204TRB requires one power-supply. The  
Voltage on any input or I/O pin cannot exceed the power pin  
during power-up.  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Supply Voltage to Ground Potential............... –0.5V to +3.8V  
Operating Range  
DC Voltage Applied to LVTTL Outputs  
in High-Z State .......................................–0.5V to VCC + 0.5V  
Range  
Ambient Temperature  
VCC  
Output Current into LVTTL Outputs (LOW)..................60 mA  
DC Input Voltage....................................–0.5V to VCC + 0.5V  
Commercial  
0°C to +70°C  
+3.3V ±5%  
CYV15G0204TRB DC Electrical Characteristics  
Parameter  
Description  
Test Conditions  
Min.  
Max.  
Unit  
LVTTL-compatible Outputs  
VOHT  
VOLT  
IOST  
IOZL  
Output HIGH Voltage  
Output LOW Voltage  
IOH = − 4 mA, VCC = Min.  
IOL = 4 mA, VCC = Min.  
VOUT = 0V[8], VCC = 3.3V  
VOUT = 0V, VCC  
2.4  
V
V
0.4  
–100  
20  
Output Short Circuit Current  
–20  
–20  
mA  
µA  
High-Z Output Leakage Current  
LVTTL-compatible Inputs  
VIHT  
VILT  
IIHT  
Input HIGH Voltage  
2.0  
VCC + 0.3  
0.8  
V
Input LOW Voltage  
Input HIGH Current  
–0.5  
V
REFCLKx Input, VIN = VCC  
Other Inputs, VIN = VCC  
REFCLKx Input, VIN = 0.0V  
Other Inputs, VIN = 0.0V  
1.5  
mA  
µA  
mA  
µA  
µA  
µA  
+40  
IILT  
Input LOW Current  
–1.5  
–40  
IIHPDT  
IILPUT  
Input HIGH Current with internal pull-down VIN = VCC  
+200  
–200  
Input LOW Current with internal pull-up  
VIN = 0.0V  
LVDIFF Inputs: REFCLKx±  
[9]  
VDIFF  
Input Differential Voltage  
400  
1.2  
0.0  
1.0  
VCC  
VCC  
mV  
V
VIHHP  
Highest Input HIGH Voltage  
Lowest Input LOW voltage  
Common Mode Range  
VILLP  
VCC/2  
V
[10]  
VCOMREF  
VCC – 1.2V  
V
3-Level Inputs  
VIHH  
VIMM  
VILL  
IIHH  
IIMM  
IILL  
Three-Level Input HIGH Voltage  
Min. ≤ VCC ≤ Max.  
Min. ≤ VCC ≤ Max.  
Min. ≤ VCC ≤ Max.  
VIN = VCC  
0.87 * VCC  
0.47 * VCC  
0.0  
VCC  
0.53 * VCC  
0.13 * VCC  
200  
V
V
Three-Level Input MID Voltage  
Three-Level Input LOW Voltage  
Input HIGH Current  
V
µA  
µA  
µA  
Input MID current  
VIN = VCC/2  
–50  
50  
Input LOW current  
VIN = GND  
–200  
Notes  
8. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.  
9. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the  
true (+) input is more positive than the complement (−) input. A logic-0 exists when the complement (−) input is more positive than true (+) input.  
10. The common mode range defines the allowable range of REFCLKx+ and REFCLKx− when REFCLKx+ = REFCLKx−. This marks the zero-crossing between  
the true and complement inputs as the signal switches between a logic-1 and a logic-0.  
Document #: 38-02101 Rev. *C  
Page 21 of 31  
[+] Feedback  
CYV15G0204TRB  
CYV15G0204TRB DC Electrical Characteristics (continued)  
Parameter  
Description  
Test Conditions  
Min.  
Max.  
Unit  
Differential CML Serial Outputs: TOUTA1±, TOUTA2±, TOUTB1±, TOUTB2±, ROUTC1±, ROUTC2±, ROUTD1±, ROUTD2±  
VOHC  
VOLC  
VODIF  
Output HIGH Voltage  
(Vcc Referenced)  
100Ω differential load  
150Ω differential load  
100Ω differential load  
150Ω differential load  
100Ω differential load  
150Ω differential load  
VCC – 0.5  
CC – 0.5  
VCC – 0.2  
VCC – 0.2  
VCC – 0.7  
VCC – 0.7  
900  
V
V
V
Output LOW Voltage  
(VCC Referenced)  
VCC – 1.4  
VCC – 1.4  
450  
V
V
Output Differential Voltage  
|(OUT+) − (OUT−)|  
mV  
mV  
560  
1000  
Differential Serial Line Receiver Inputs: INC1±, INC2±, IND1±, IND2±  
[9]  
VDIFFs  
VIHE  
VILE  
Input Differential Voltage |(IN+) − (IN−)|  
Highest Input HIGH Voltage  
Lowest Input LOW Voltage  
Input HIGH Current  
100  
1200  
VCC  
mV  
V
VCC – 2.0  
V
IIHE  
VIN = VIHE Max.  
VIN = VILE Min.  
1350  
+3.1  
μA  
μA  
V
IILE  
Input LOW Current  
–700  
[11]  
VICOM  
Common Mode input range  
((VCC – 2.0V)+0.5)min,  
(VCC – 0.5V) max.  
+1.25  
Power Supply  
Typ.  
Max.  
[12, 13]  
ICC  
Max Power Supply Current  
REFCLKx= Commercial  
MAX  
810  
990  
mA  
mA  
[12, 13]  
ICC  
Typical Power Supply Current  
REFCLKx= Commercial  
125 MHz  
770  
950  
AC Test Loads and Waveforms  
3.3V  
RL = 100Ω  
R
L
R1  
R2  
R1 = 590Ω  
R2 = 435Ω  
CL ≤ 7 pF  
(Includes fixture and  
probe capacitance)  
(b) CML Output Test Load[14]  
CL  
(Includes fixture and  
probe capacitance)  
(a) LVTTL Output Test Load[14]  
VIHE  
3.0V  
VIHE  
2.0V  
0.8V  
2.0V  
0.8V  
80%  
80%  
Vth = 1.4V  
Vth = 1.4V  
20%  
20%  
VILE  
≤ 270 ps  
GND  
VILE  
≤ 270 ps  
≤ 1 ns  
≤ 1 ns  
(c) LVTTL Input Test Waveform[15]  
(d) CML/LVPECL Input Test Waveform  
Notes  
11. The common mode range defines the allowable range of INPUT+ and INPUT− when INPUT+ = INPUT−. This marks the zero-crossing between the true and  
complement inputs as the signal switches between a logic-1 and a logic-0.  
12. Maximum I is measured with V = MAX, T = 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and  
CC  
CC  
A
outputs unloaded.  
13. Typical I is measured under similar conditions except with V = 3.3V, T = 25°C, with all channels enabled and one Serial Line Driver per transmit channel  
CC  
CC  
A
sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.  
14. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.  
15. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.  
Document #: 38-02101 Rev. *C  
Page 22 of 31  
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CYV15G0204TRB  
CYV15G0204TRB AC Electrical Characteristics  
Parameter  
Description  
Min.  
Max  
Unit  
CYV15G0204TRB Transmitter LVTTL Switching Characteristics Over the Operating Range  
fTS  
TXCLKx Clock Cycle Frequency  
TXCLKx Period=1/fTS  
19.5  
6.66  
2.2  
150  
MHz  
ns  
tTXCLK  
51.28  
[16]  
tTXCLKH  
TXCLKx HIGH Time  
ns  
[16]  
tTXCLKL  
TXCLKx LOW Time  
2.2  
ns  
[16, 17, 18, 19]  
tTXCLKR  
tTXCLKF  
tTXDS  
TXCLKx Rise Time  
0.2  
1.7  
1.7  
ns  
[16, 17, 18, 19]  
TXCLKx Fall Time  
0.2  
ns  
Transmit Data Set-up Time to TXCLKx↑ (TXCKSELx = 0)  
Transmit Data Hold Time from TXCLKx↑ (TXCKSELx = 0)  
TXCLKOx Clock Frequency = 1x or 2x REFCLKx Frequency  
TXCLKOx Period=1/fTOS  
2.2  
ns  
tTXDH  
1.0  
ns  
fTOS  
19.5  
6.66  
–1.9  
150  
51.28  
0
MHz  
ns  
tTXCLKO  
tTXCLKOD  
TXCLKO Duty Cycle centered at 60% HIGH time  
ns  
CYV15G0204TRB Receiver LVTTL Switching Characteristics Over the Operating Range  
fRS  
RXCLKx± Clock Output Frequency  
9.75  
6.66  
150  
102.56  
+1.0  
1.2  
MHz  
ns  
tRXCLKP  
tRXCLKD  
tRXCLKR  
RXCLKx± Period = 1/fRS  
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate)  
RXCLKx± Rise Time  
–1.0  
ns  
[16]  
[16]  
0.3  
ns  
tRXCLKF  
RXCLKx± Fall Time  
0.3  
1.2  
ns  
[20]  
tRXDv–  
tRXDv+  
fROS  
Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)  
Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)  
Status and Data Valid Time to RXCLKx± (RXRATEx = 0)  
Status and Data Valid Time to RXCLKx± (RXRATEx = 1)  
RECLKOx Clock Frequency  
5UI–2.0[21]  
5UI–1.3[21]  
5UI–1.8[21]  
5UI–2.6[21]  
19.5  
ns  
ns  
[20]  
ns  
ns  
150  
51.28  
0
MHz  
ns  
tRECLKO  
RECLKOx Period=1/fROS  
6.66  
tRECLKOD  
RECLKOx Duty Cycle centered at 60% HIGH time  
-1.9  
ns  
CYV15G0204TRB REFCLKx Switching Characteristics Over the Operating Range  
fREF  
REFCLKx Clock Frequency  
19.5  
6.6  
150  
MHz  
ns  
ns  
ns  
ns  
ns  
%
tREFCLK  
tREFH  
REFCLKx Period = 1/fREF  
51.28  
REFCLKx HIGH Time (TXRATEx = 1)(Half Rate)  
REFCLKx HIGH Time (TXRATEx = 0)(Full Rate)  
REFCLKx LOW Time (TXRATEx = 1)(Half Rate)  
REFCLKx LOW Time (TXRATEx = 0)(Full Rate)  
REFCLKx Duty Cycle  
5.9  
2.9[16]  
tREFL  
5.9  
2.9[16]  
30  
[22]  
tREFD  
70  
2
[16, 17, 18, 19]  
tREFR  
REFCLKx Rise Time (20%–80%)  
ns  
ns  
%
[16, 17, 18, 19]  
[23]  
tREFF  
REFCLKx Fall Time (20%–80%)  
2
tREFRX  
TRGCLKx Frequency Referenced to Received Clock Period  
–0.15  
+0.15  
Notes  
16. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.  
17. The ratio of rise time to falling time must not vary by greater than 2:1.  
18. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.  
19. All transmit AC timing parameters measured with 1-ns typical rise time and fall time.  
20. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.  
21. Receiver UI (Unit Interval) is calculated as 1/(f  
* 20) (when TRGRATEx = 1) or 1/(f  
* 10) (when TRGRATEx = 0). In an operating link this is equivalent to t .  
REF  
R
E
F
B
22. The duty cycle specification is a simultaneous condition with the t  
and t  
parameters. This means that at faster character rates the REFCLKx± duty cycle  
REFL  
REFH  
cannot be as large as 30%–70%.  
23. TRGCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.  
TRGCLKx± must be within ±1500 PPM (±0.15%) of the transmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver channel  
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be  
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.  
Document #: 38-02101 Rev. *C  
Page 23 of 31  
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CYV15G0204TRB  
CYV15G0204TRB AC Electrical Characteristics (continued)  
Parameter  
tTREFDS  
Description  
Min.  
Max  
Unit  
Transmit Data Set-up Time to REFCLKx - Full Rate  
(TXRATEx = 0, TXCKSELx = 1)  
2.4  
ns  
Transmit Data Set-up Time to REFCLKx - Half Rate  
(TXRATEx = 1, TXCKSELx = 1)  
2.3  
1.0  
1.6  
ns  
ns  
ns  
tTREFDH  
Transmit Data Hold Time from REFCLKx - Full Rate  
(TXRATEx = 0, TXCKSELx = 1)  
Transmit Data Hold Time from REFCLKx - Half Rate  
(TXRATEx = 1, TXCKSELx = 1)  
CYV15G0204TRB TRGCLKx Switching Characteristics Over the Operating Range  
fREF  
TRGCLKx Clock Frequency  
19.5  
6.6  
150  
MHz  
ns  
ns  
ns  
ns  
ns  
%
tREFCLK  
tREFH  
TRGCLKx Period = 1/fREF  
51.28  
TRGCLKx HIGH Time (TXRATEx = 1)(Half Rate)  
TRGCLKx HIGH Time (TXRATEx = 0)(Full Rate)  
TRGCLKx LOW Time (TXRATEx = 1)(Half Rate)  
TRGCLKx LOW Time (TXRATEx = 0)(Full Rate)  
TRGCLKx Duty Cycle  
5.9  
2.9[16]  
tREFL  
5.9  
2.9[16]  
30  
[22]  
tREFD  
70  
2
[16, 17, 18, 19]  
tREFR  
TRGCLKx Rise Time (20%–80%)  
ns  
ns  
%
[16, 17, 18, 19]  
[23]  
tREFF  
TRGCLKx Fall Time (20%–80%)  
2
tREFRX  
TRGCLKx Frequency Referenced to Received Clock Frequency  
–0.15  
+0.15  
CYV15G0204TRB Bus Configuration Write Timing Characteristics Over the Operating Range  
tDATAH  
tDATAS  
tWRENP  
Bus Configuration Data Hold  
0
ns  
ns  
ns  
Bus Configuration Data Setup  
Bus Configuration WREN Pulse Width  
10  
10  
CYV15G0204TRB JTAG Test Clock Characteristics Over the Operating Range  
fTCLK  
tTCLK  
JTAG Test Clock Frequency  
JTAG Test Clock Period  
20  
MHz  
ns  
50  
30  
CYV15G0204TRB Device RESET Characteristics Over the Operating Range  
tRST Device RESET Pulse Width  
ns  
CYV15G0204TRB Transmitter and Reclocker Serial Output Characteristics Over the Operating Range  
Parameter  
Description  
Condition  
Min.  
660  
50  
Max.  
5128  
270  
Unit  
ps  
tB  
tRISE  
Bit Time  
[16]  
CML Output Rise Time 20−80% (CML Test Load)  
SPDSELx = HIGH  
SPDSELx= MID  
SPDSELx =LOW  
SPDSELx = HIGH  
SPDSELx = MID  
SPDSELx =LOW  
ps  
100  
180  
50  
500  
ps  
1000  
270  
ps  
[16]  
tFALL  
CML Output Fall Time 80−20% (CML Test Load)  
ps  
100  
180  
500  
ps  
1000  
ps  
Document #: 38-02101 Rev. *C  
Page 24 of 31  
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CYV15G0204TRB  
PLL Characteristics  
Parameter  
Description  
Condition  
Min.  
Typ.  
Max.  
Unit  
CYV15G0204TRB Transmitter Output PLL Characteristics  
[16, 24]  
tJTGENSD  
tJTGENHD  
tTXLOCK  
Transmit Jitter Generation - SD Data Rate  
Transmit Jitter Generation - HD Data Rate  
Transmit PLL lock to REFCLKx±  
REFCLKx = 27 MHz  
200  
76  
ps  
ps  
μs  
[16, 24]  
REFCLKx = 148.5 MHz  
200  
CYV15G0204TRB Reclocker Output PLL Characteristics  
[16, 25]  
tJRGENSD  
Reclocker Jitter Generation - SD Data Rate  
Reclocker Jitter Generation - HD Data Rate  
TRGCLKx = 27 MHz  
133  
107  
ps  
ps  
[16, 25]  
tJRGENHD  
TRGCLKx = 148.5 MHz  
CYV15G0204TRB Receive PLL Characteristics Over the Operating Range  
tRXLOCK  
Receive PLL lock to input data stream (cold start)  
Receive PLL lock to input data stream  
Receive PLL Unlock Rate  
376k  
376k  
46  
UI  
UI  
UI  
tRXUNLOCK  
Capacitance[16]  
Parameter  
CINTTL  
Description  
Test Conditions  
Max.  
Unit  
TTL Input Capacitance  
PECL input Capacitance  
TA = 25°C, f0 = 1 MHz, VCC = 3.3V  
7
4
pF  
pF  
CINPECL  
TA = 25°C, f0 = 1 MHz, VCC = 3.3V  
\
CYV15G0204TRB HOTLink II Transmitter Switching Waveforms  
t
TXCLK  
Transmit Interface  
Write Timing  
TXCLKx selected  
t
t
TXCLKL  
TXCLKH  
TXCLKx  
t
t
TXDH  
TXDS  
TXDx[9:0]  
Transmit Interface  
Write Timing  
REFCLKx selected  
TXRATEx = 0  
t
REFCLK  
t
t
REFL  
REFH  
REFCLKx  
TXDx[9:0],  
t
t
TREFDS  
TREFDH  
Notes  
24. While sending BIST data at the corresponding data rate, after 10,000 histogram hits, time referenced to REFCLKx± input.  
25. Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide-bandwidth digital sampling oscilloscope. The  
measurement was recorded after 10,000 histogram hits, time referenced to REFCLKx± of the transmit channel.  
Document #: 38-02101 Rev. *C  
Page 25 of 31  
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CYV15G0204TRB  
CYV15G0204TRB HOTLink II Transmitter Switching Waveforms (continued)  
Transmit Interface  
t
REFCLK  
Write Timing  
REFCLKx selected  
TXRATEx = 1  
t
t
REFL  
REFH  
REFCLKx  
TXDx[9:0]  
Note 26  
t
t
TREFDS  
t
t
TREFDH  
TREFDS  
TREFDH  
Transmit Interface  
TXCLKOx Timing  
tREFCLK  
tREFH  
tREFL  
TXRATEx = 1  
REFCLKx  
Note 27  
tTXCLKO  
Note 28  
TXCLKOx  
(internal)  
Transmit Interface  
TXCLKOx Timing  
t
REFCLK  
t
t
REFH  
REFL  
TXRATEx = 0  
Note27  
REFCLKx  
t
TXCLKO  
Note28  
TXCLKOx  
Notes  
26. When REFCLKx± is configured for half-rate operation (TXRATEx = 1) and data is captured using REFCLKx instead of a TXCLKx clock. Data is captured using  
both the rising and falling edges of REFCLKx.  
27. The TXCLKOx output remains at the character rate regardless of the state of TXRATEx and does not follow the duty cycle of REFCLKx±.  
28. The rising edge of TXCLKOx output has no direct phase relationship to the REFCLKx± input.  
Document #: 38-02101 Rev. *C  
Page 26 of 31  
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CYV15G0204TRB  
Switching Waveforms for the CYV15G0204TRB HOTLink II Receiver  
Receive Interface  
Read Timing  
RXRATEx = 0  
tRXCLKP  
RXCLKx+  
RXCLKx–  
t
RXDV  
–
RXDx[9:0]  
t
RXDV+  
Receive Interface  
Read Timing  
RXRATEx = 1  
tRXCLKP  
RXCLKx+  
RXCLKx–  
t
RXDV  
–
RXDx[9:0]  
t
RXDV+  
Bus Configuration  
Write Timing  
ADDR[3:0]  
DATA[6:0]  
WREN  
tWRENP  
tDATAS  
tDATAH  
Document #: 38-02101 Rev. *C  
Page 27 of 31  
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CYV15G0204TRB  
Table 7. Package Coordinate Signal Allocation  
Ball  
ID  
Ball  
ID  
Ball  
ID  
Signal Name  
Signal Type  
Signal Name  
Signal Type  
Signal Name  
Signal Type  
A01  
A02  
A03  
A04  
A05  
A06  
A07  
A08  
A09  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
B01  
B02  
B03  
B04  
B05  
B06  
B07  
B08  
B09  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
C01  
C02  
C03  
INC1–  
ROUTC1–  
INC2–  
CML IN  
CML OUT  
CML IN  
C07  
C08  
C09  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
C19  
C20  
D01  
D02  
D03  
D04  
D05  
D06  
D07  
D08  
D09  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
D19  
D20  
E01  
E02  
E03  
E04  
E17  
E18  
E19  
E20  
F01  
ULCC  
GND  
LVTTL IN PU  
GROUND  
F17  
F18  
F19  
F20  
G01  
G02  
G03  
G04  
G17  
G18  
G19  
G20  
H01  
H02  
H03  
H04  
H17  
H18  
H19  
H20  
J01  
NC  
NC  
NO CONNECT  
NO CONNECT  
LVTTL OUT  
NO CONNECT  
GROUND  
DATA[6]  
DATA[4]  
DATA[2]  
DATA[0]  
GND  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN PU  
GROUND  
TXCLKOB  
NC  
ROUTC2–  
VCC  
CML OUT  
POWER  
GND  
WREN  
GND  
GND  
SPDSELB  
NC  
IND1–  
CML IN  
LVTTL IN PU  
GROUND  
ROUTD1–  
GND  
CML OUT  
GROUND  
CML IN  
NC  
NO CONNECT  
3-LEVEL SEL  
POWER  
GROUND  
IND2–  
SPDSELD  
VCC  
3-LEVEL SEL  
NO CONNECT  
3-LEVEL SEL  
NO CONNECT  
GROUND  
ROUTD2–  
GND  
CML OUT  
GROUND  
CML OUT  
GROUND  
GROUND  
CML OUT  
POWER  
LDTDEN  
TRST  
GND  
LVTTL IN PU  
LVTTL IN PU  
GROUND  
SPDSELA  
NC  
TOUTA1–  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
NC  
GND  
TDO  
LVTTL 3-S OUT  
LVTTL IN PD  
LVTTL IN PU  
LVTTL IN  
GROUND  
TOUTA2–  
VCC  
TCLK  
RESET  
INSELD  
VCC  
GROUND  
GROUND  
VCC  
POWER  
GROUND  
TOUTB1–  
VCC  
CML OUT  
POWER  
POWER  
GROUND  
VCC  
POWER  
GROUND  
TOUTB2–  
INC1+  
CML OUT  
CML IN  
VCC  
POWER  
GROUND  
SPDSELC  
GND  
3-LEVEL SEL  
GROUND  
GROUND  
ROUTC1+  
INC2+  
CML OUT  
CML IN  
J02  
GROUND  
DATA[5]  
DATA[3]  
DATA[1]  
GND  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN PU  
GROUND  
J03  
GROUND  
ROUTC2+  
VCC  
CML OUT  
POWER  
J04  
GROUND  
J17  
NO CONNECT  
NO CONNECT  
NO CONNECT  
NO CONNECT  
LVTTL OUT  
PECL IN  
IND1+  
CML IN  
J18  
NC  
ROUTD1+  
GND  
CML OUT  
GROUND  
CML IN  
GND  
GROUND  
J19  
NC  
GND  
GROUND  
J20  
NC  
IND2+  
NC  
NO CONNECT  
POWER  
K01  
RXDC[4]  
ROUTD2+  
NC  
CML OUT  
NO CONNECT  
CML OUT  
GROUND  
NO CONNECT  
CML OUT  
POWER  
VCC  
K02 TRGCLKC–  
NC  
NO CONNECT  
POWER  
K03  
K04  
K17  
K18  
K19  
K20  
L01  
GND  
GND  
NC  
GROUND  
TOUTA1+  
GND  
VCC  
GROUND  
SCANEN2  
TMEN3  
VCC  
LVTTL IN PD  
LVTTL IN PD  
POWER  
NO CONNECT  
NO CONNECT  
NO CONNECT  
NO CONNECT  
LVTTL OUT  
PECL IN  
NC  
NC  
TOUTA2+  
VCC  
NC  
VCC  
POWER  
NC  
NC  
NO CONNECT  
CML OUT  
NO CONNECT  
CML OUT  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN  
VCC  
POWER  
RXDC[5]  
TOUTB1+  
NC  
VCC  
POWER  
L02 TRGCLKC+  
VCC  
POWER  
L03  
L04  
L17  
L18  
L19  
LFIC  
GND  
NC  
LVTTL OUT  
GROUND  
TOUTB2+  
TDI  
VCC  
POWER  
VCC  
POWER  
NO CONNECT  
NO CONNECT  
NO CONNECT  
TMS  
VCC  
POWER  
NC  
INSELC  
RXDC[8]  
LVTTL OUT  
NC  
Document #: 38-02101 Rev. *C  
Page 28 of 31  
[+] Feedback  
CYV15G0204TRB  
Table 7. Package Coordinate Signal Allocation (continued)  
Ball  
ID  
Ball  
ID  
Ball  
ID  
Signal Name  
Signal Type  
Signal Name  
Signal Type  
Signal Name  
Signal Type  
C04  
C05  
C06  
M03  
M04  
VCC  
VCC  
POWER  
POWER  
F02  
F03  
F04  
U03  
U04  
U05  
U06  
U07  
U08  
U09  
U10  
RXDC[9]  
VCC  
LVTTL OUT  
POWER  
L20  
M01  
M02  
W03  
W04  
W05  
W06  
W07  
W08  
W09  
W10  
W11  
W12  
W13  
W14  
W15  
W16  
W17  
TXDB[6]  
RXDC[6]  
RXDC[7]  
LFID  
LVTTL IN  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
POWER  
ULCD  
VCC  
LVTTL IN PU  
POWER  
VCC  
POWER  
VCC  
POWER  
REPDOC  
LVTTL OUT  
PECL IN  
VCC  
POWER  
RXCLKD–  
VCC  
M17 REFCLKB+  
M18 REFCLKB–  
VCC  
POWER  
PECL IN  
RXDD[4]  
RXDD[3]  
GND  
LVTTL OUT  
LVTTL OUT  
GROUND  
LVTTL IN  
RXDD[6]  
RXDD[0]  
GND  
LVTTL OUT  
LVTTL OUT  
GROUND  
M19  
M20  
N01  
N02  
N03  
N04  
N17  
N18  
N19  
N20  
P01  
P02  
P03  
P04  
P17  
P18  
P19  
P20  
R01  
R02  
R03  
R04  
R17  
R18  
R19  
R20  
T01  
T02  
T03  
T04  
T17  
T18  
T19  
T20  
U01  
U02  
TXERRB  
TXCLKB  
GND  
LVTTL OUT  
LVTTL IN PD  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
LVTTL IN  
LVTTL IN  
LVTTL IN  
LVTTL IN  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
LVTTL OUT  
LVTTL IN  
LVTTL IN  
LVTTL IN  
LVTTL IN  
POWER  
TXDA[9]  
ADDR [0]  
ADDR [3]  
ADDR [1]  
NC  
LVTTL IN PU  
LVTTL IN PU  
NO CONNECT  
LVTTL OUT  
GROUND  
GND  
LVTTL IN PU  
PECL IN  
GND  
U11 TRGCLKD–  
GND  
U12  
U13  
U14  
U15  
U16  
U17  
U18  
U19  
U20  
V01  
V02  
V03  
V04  
V05  
V06  
V07  
V08  
V09  
V10  
TXDA[1]  
GND  
LVTTL IN  
TXERRA  
GND  
GND  
GROUND  
LVTTL IN  
GND  
TXDA[4]  
TXDA[8]  
VCC  
TXDA[2]  
TXDA[6]  
VCC  
LVTTL IN  
GND  
LVTTL IN  
LVTTL IN  
GND  
POWER  
POWER  
RXDC[3]  
RXDC[2]  
RXDC[1]  
RXDC[0]  
TXDB[5]  
TXDB[4]  
TXDB[3]  
TXDB[2]  
BISTSTC  
RECLKOC  
RXCLKC+  
RXCLKC–  
TXDB[1]  
TXDB[0]  
TXDB[9]  
TXDB[7]  
VCC  
NC  
NO CONNECT  
LVTTL IN  
NC  
NO CONNECT  
PECL IN  
TXDB[8]  
NC  
W18 REFCLKA+  
NO CONNECT  
NO CONNECT  
POWER  
W19  
W20  
Y01  
Y02  
Y03  
Y04  
Y05  
Y06  
Y07  
Y08  
Y09  
Y10  
Y11  
Y12  
Y13  
Y14  
Y15  
Y16  
Y17  
Y18  
Y19  
Y20  
NC  
NC  
NO CONNECT  
NO CONNECT  
POWER  
NC  
VCC  
VCC  
VCC  
POWER  
VCC  
POWER  
VCC  
POWER  
RXDD[9]  
RXCLKD+  
VCC  
LVTTL OUT  
LVTTL OUT  
POWER  
RXDD[8]  
VCC  
LVTTL OUT  
POWER  
RXDD[5]  
RXDD[1]  
GND  
LVTTL OUT  
LVTTL OUT  
GROUND  
LVTTL OUT  
LVTTL IN PU  
PECL IN  
RXDD[7]  
RXDD[2]  
GND  
LVTTL OUT  
LVTTL OUT  
GROUND  
BISTSTD  
ADDR [2]  
RECLKOD  
NC  
LVTTL OUT  
NO CONNECT  
LVTTL IN PD  
NO CONNECT  
GROUND  
V11 TRGCLKD+  
TXCLKA  
NC  
V12  
V13  
V14  
V15  
V16  
V17  
V18  
V19  
V20  
W01  
W02  
TXCLKOA  
GND  
TXDA[3]  
TXDA[7]  
VCC  
LVTTL OUT  
GROUND  
LVTTL IN  
GND  
VCC  
POWER  
TXDA[0]  
TXDA[5]  
VCC  
LVTTL IN  
VCC  
POWER  
LVTTL IN  
LVTTL IN  
VCC  
POWER  
POWER  
POWER  
VCC  
POWER  
NC  
NO CONNECT  
NO CONNECT  
NO CONNECT  
NO CONNECT  
POWER  
REPDOD  
REFCLKA–  
NC  
LVTTL OUT  
PECL IN  
VCC  
POWER  
NC  
VCC  
POWER  
NC  
NO CONNECT  
NO CONNECT  
VCC  
POWER  
NC  
NC  
VCC  
POWER  
VCC  
VCC  
POWER  
VCC  
POWER  
Document #: 38-02101 Rev. *C  
Page 29 of 31  
[+] Feedback  
CYV15G0204TRB  
Ordering Information  
Package  
Name  
Operating  
Range  
Speed  
Ordering Code  
Package Type  
256-Ball Thermally Enhanced Ball Grid Array  
Pb-Free 256-Ball Thermally Enhanced Ball Grid Array Commercial  
Standard  
Standard  
CYV15G0204TRB-BGC  
CYV15G0204TRB-BGXC  
BL256  
BL256  
Commercial  
Package Diagram  
Figure 3. 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256  
TOP VIEW  
0.20ꢀ4ꢁX  
BOTTOM VIEW ꢀBALL SIDEX  
A
27.00 0.13  
Ø0.15 M C  
Ø0.30 M C  
A
B
A1 CORNER I.D.  
A1 CORNER I.D.  
24.13  
Ø0.75 0.15ꢀ256ꢁX  
20 18  
19  
16  
14  
12  
10  
8
6
4
2
17  
15  
13  
11  
9
7
5
3
1
A
B
C
D
E
F
G
H
J
R 2.5 Max ꢀ4ꢁX  
K
L
M
N
P
R
T
A
U
V
W
Y
A
0.50 MIN.  
B
1.57 0.175  
0.97 REF.  
0.15  
C
26°  
0.15  
C
0.60 0.10  
C
0.20 MIN  
TOP OF MOLD COMPOUND  
TO TOP OF BALLS  
TYP.  
SEATING PLANE  
SIDE VIEW  
SECTION A-A  
51-85123-*E  
HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names  
mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-02101 Rev. *C  
Page 30 of 31  
© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the  
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to  
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
[+] Feedback  
CYV15G0204TRB  
Document History Page  
Document Title: CYV15G0204TRB Independent Clock HOTLink II™ Dual Serializer and Dual Reclocking Deserializer  
Document Number: 38-02101  
ISSUE  
DATE  
ORIG. OF  
CHANGE  
REV.  
ECN NO.  
DESCRIPTION OF CHANGE  
**  
244348  
338721  
384307  
1034060  
See ECN  
See ECN  
See ECN  
See ECN  
FRE  
SUA  
AGT  
UKK  
New Data Sheet  
*A  
*B  
*C  
Added Pb-Free package option availability  
Revised setup and hold times (tTXDH, tTREFDS,tTREFDH, tRXDv–, tRXDv+  
)
Added clarification for the necessity of JTAG controller reset and the  
methods to implement it.  
Document #: 38-02101 Rev. *C  
Page 31 of 31  
[+] Feedback  
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