330Ω to 3.3kΩ pull-up resistor will be necessary, depending
on the stray capacitance on the synchronizing line. A maxi-
mum of 8 PWS745-1s can be connected without the use of
an external TTL buffer.
with satisfactory operation; however, three layers provide
greater density and better control of interference from the
power switching lines. Should a four-layer board be required
for other circuitry, the use of separate layers for ground and
power planes, a layer for switching signals and a layer for
analog signals would allow the most straightforward layout
of the PWS745 system. Critical consideration should go to
minimizing electromagnetic radiation from the power switch-
ing lines T-TO and T-TO. The dynamic component of the
current is supplied by the bypass capacitor on the VD pin of
the transformer. The high frequency AC current flows through
the transformer, TO, returning in the T pin, passing through
the MOSFET and exiting through the COM pin back to the
bypass capacitor. This current path defines a magnetic loop
which transmits a magnetic field. The magnetic field lines
reinforce at the center of the loop, while the field lines from
opposite points of the loop oppose each other outside the
loop. Cancellation of the magnetic radiation occurs when the
loop is collapsed to two tightly spaced parallel line seg-
ments, each carrying the same current in the opposite direc-
tion. All of the current in the ground or power plane will
flow directly under the T-TO traces because this is the path
of least inductance or impedance. Another potential problem
with the T-TO lines is electric field radiation. Here, the
power plane is effective in terminating most of the field lines
because of its proximity. Additional shielding can be ob-
tained by running ground trace(s) along the T-TO lines,
facilitating a minimum loop area for the transformer’s cen-
ter-tap bypass capacitor.
ENABLE
An ENABLE pin is provided so that the DRIVE and DRIVE
pins can be shut down to the low state within one cycle to
minimize power use if desired. A TTL low applied to the pin
will shut down the driver and a TTL high will enable the
driver. The TTLOUT will still have the 1.2MHz signal so that
a master driver can be disabled without shutting down the
remaining synchronized drivers. The pin can be left open for
normal operation.
DRIVE, DRIVE
These pins are normally connected directly to the adjacent
GATE pin and are used to drive the gates of the internally
packaged MOSFETs. If desired, these pins may be used
instead to drive the gates of external FETs, such as those
used in the PWS750 series of power components. It is
important to minimize the capacitance on these nodes to
insure the rapid charging of the MOSFET gates.
GATE, GATE
These pins are normally connected directly to the adjacent
DRIVE pins, which are internally connected to the gates of
the MOSFETs.
T, T
The connection between the outputs of the transformer and
the diode bridge should be kept as short as possible. Unnec-
essary stray capacitance on these lines could cause resonant
peaking to occur, resulting in a slight increase in output
voltage.
The T and T pins are the complementary transformer drive
connections. The signals on these pins are 600kHz comple-
mentary square waves with twice the amplitude of the input
voltage. These lines connect MOSFET switches to the iso-
lation transformers through the TO and TO pins. Without
proper printed circuit board layout techniques, these lines
could generate interference to analog circuits. Refer to the
section on layout techniques.
EXTERNAL FILTER COMPONENTS
Filter components are necessary to reduce the input ripple
current and output voltage noise. Without any input filtering,
the sawtooth currents of the switching power lines T-TO and
T-TO would flow in the supply line. Since this AC current
can be as great as 1A peak, voltage interference with other
components using this supply line would likely occur. Use
of a pi-filter can reduce the input ripple current to about
1mA peak. Recommended values are a 20µH inductor prior
to the connection of the supply to the power plane. A 10µF
tantalum capacitor with a 0.33µF ceramic capacitor is ad-
equate for the input bypassing . The inductor must be rated
for at least 2A or a DC resistance of 0.1Ω. An example of a
low-cost inductor is part number 51591 from Pulse Engi-
neering. Output voltage filtering is achieved with a 0.33µF
capacitor connecting each VOUT pin of the diode bridge to
ground. Short leads and close placement of the capacitors to
the bridge provide optimum high frequency bypassing. Us-
ing correct bypassing techniques, 600kHz ripple of less than
5mVp-p is achievable. High frequency noise bursts coincid-
ing with the switch times are approximately 20mVp-p.
Inductance of 20µH in series with the output loads will
significantly reduce the noise seen by the loads.
TO, TO
These pins are the primary terminals of the transformer and
are connected to the T and T pins of the PWS745-1.
VD
The center tap of the primary of the transformer is tied
directly to the supply. A 0.3µF bypass capacitor must be
located as close to this pin as possible.
AC
The output of the isolation transformer which is connected
to the AC inputs on the PWS740-3 or PWS750-3 diode
bridge.
PC BOARD LAYOUT
CONSIDERATIONS
Multilayer printed circuit boards are recommended for
PWS745 systems. Two-layer boards are certainly possible
®
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PWS745
