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PWS740

型号：

PWS740

描述：

分布式多通道隔离式DC -DC转换器[ Distributed Multi-Channel Isolated DC-TO-DC CONVERTER ]

品牌：

BB[ BURR-BROWN CORPORATION ]

页数：

8 页

PDF大小：

119 K

下载PDF手册
®
PWS740  
PWS740  
Distributed Multi-Channel Isolated  
DC-TO-DC CONVERTER  
APPLICATIONS  
● INDUSTRIAL MEASUREMENT AND  
FEATURES  
● ISOLATED ±7 TO ±20VDC OUTPUTS  
● BARRIER 100% TESTED AT 1500VAC, 60Hz  
● LOWEST POSSIBLE COST PER CHANNEL  
● MINIMUM PC BOARD SPACE  
CONTROL  
● DATA ACQUISITION SYSTEMS  
● TEST EQUIPMENT  
● 80% EFFICIENCY (8 CHANNELS, RATED  
The PWS740-1 is a high-frequency (400kHz nominal)  
oscillator/driver, handling up to eight channels. This  
part is a hybrid containing an oscillator and two power  
FETs. It is supplied in a TO-3 case to provide the  
power dissipation necessary at full load. Transformer  
impedance limits the maximum input current to about  
700mA at 15V input, well within the unit’s thermal  
limits. A TTL-compatible ENABLE pin provides out-  
put shut-down if desired. A SYNC pin allows syn-  
chronization of several PWS740-1s.  
LOADS)  
● FLEXIBLE USE WITH PWS745  
COMPONENTS  
DESCRIPTION  
The PWS740 is a multichannel, isolated DC-to-DC  
converter with a 1500VAC continuous isolation rat-  
ing. The outputs track the input voltage to the con-  
verter over the range of 7 to 20VDC. The converter’s  
modular design, comprising three components, mini-  
mizes the cost of isolated multichannel power for the  
user.  
The PWS740-2 is a trifilar-wound isolation trans-  
former using a ferrite core and is encapsulated in a  
plastic package, allowing a higher isolation voltage  
rating. One PWS740-2 is used per isolated channel.  
–VO  
–VO  
Gnd1 +VO  
Gnd1 +VO  
10µH  
10µH  
10µH  
10µH  
Functional Diagram  
0.3µF  
0.3µF  
0.3µF  
0.3µF  
BAV99  
BAV99  
BAV99  
BAV99  
2
5
2
3
4
1
3
4
1
V+  
PWS740-2  
PWS740-1  
8
4
6
6
5
TO  
*7  
10µF  
5
20µH  
Up to  
6 More  
Oscillator/  
Driver  
VDRIVE  
*2  
*1  
Channels  
Freq  
Adj  
0.3µF  
0.3µF  
TO  
6
* Optional features; if unused, leave open.  
** User Option  
3
International Airport Industrial Park  
•
Mailing Address: PO Box 11400, Tucson, AZ 85734  
FAXLine: (800) 548-6133 (US/Canada Only)  
• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111  
Internet: http://www.burr-brown.com/  
•
•
Cable: BBRCORP  
•
Telex: 066-6491  
•
FAX: (520) 889-1510  
•
Immediate Product Info: (800) 548-6132  
© 1987 Burr-Brown Corporation  
PDS-758H  
Printed in U.S.A. January, 1998  
SPECIFICATIONS  
ELECTRICAL  
At VIN = 15V, output load on each of 8 channels = ±15mA, TA = +25°C, unless otherwise specified.  
PARAMETER  
CONDITION  
MIN  
TYP  
MAX  
UNITS  
PWS740 SYSTEM  
ISOLATION  
Rated Voltage  
Continuous, AC, 50/60Hz  
Continuous, DC  
1500  
2121  
VACrms  
VDC  
Test Voltage  
Impedance  
Leakage Current  
10s, minimum  
Measured from Pin 2 to Pin 5 of the PWS740-2  
240VACrms, 60Hz Per Channel  
4000  
VACrms  
Ω || pF  
µA  
1012 || 3  
0.5  
1.5  
20  
INPUT  
Rated Voltage  
Voltage Range  
Current  
15  
VDC  
VDC  
mA  
mA  
mA  
7
±30mA Output Load on 8 Channels, VIN = 15V  
Rated Output Load on 8 Channels, VIN = 15V  
Full Output Load on 8 Channels, VIN = 15V with π Filter on Input  
520  
300  
1
Current Ripple  
OUTPUT  
Rated Voltage  
±15mA Output Load on 8 Channels  
±1mA/Channel  
±15mA Output Load on Each Channel  
±15mA Output Load on Each Channel  
±3mA < Output Load < ±30mA  
VOUT/VIN  
See Typical Performance Curves  
See Theory of Operation  
Each Channel  
14  
15  
30  
16  
VDC  
VDC  
VDC  
V/°C  
V/mA  
V/V  
Voltage at Min Load  
Voltage Range  
VOUT vs Temp  
Load Regulation  
Tracking Regulation  
Ripple Voltage  
±7  
±20  
±0.05  
0.25  
1.2  
Noise Voltage  
Current | +IOUT | + | –IOUT  
|
60  
mA  
TEMPERATURE  
Specification  
Operation  
–25  
–25  
+85  
+85  
°C  
°C  
PWS740-1 OSCILLATOR/DRIVER  
Frequency  
Supply  
VIN = 15V  
350  
7
400  
15  
470  
20  
kHz  
V
Enable  
Drivers On  
Drivers Off  
2
0
VS  
0.8  
V
V
PWS740-2 ISOLATION TRANSFORMER  
Isolation Test Voltage  
10s, minimum  
60s, minimum  
Continuous  
4000  
1500  
VACrms  
VACrms  
VACrms  
Ω || pF  
µA  
Rated Isolation Voltage  
Isolation Impedance  
Isolation Leakage  
Primary Inductance  
Winding Ratio  
1500  
1.5  
1012 || 3  
0.5  
300  
240VAC  
400kHz, Pin 1 to Pin 5  
Primary/Secondary  
µH  
68/76  
DIODE BRIDGE SPECIFICATIONS  
Reverse Recovery  
Reverse Breakdown  
Reverse Current  
Forward Voltage  
IF = IR = 50mA  
IR = 100µA  
VR = 40V  
40  
ns  
V
µA  
V
55  
1.5  
1.8  
IF = 100mA  
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes  
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change  
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant  
any BURR-BROWN product for use in life support devices and/or systems.  
®
2
PWS740  
PIN CONFIGURATION  
ELECTROSTATIC  
DISCHARGE SENSITIVITY  
Top Views  
TO-3  
This integrated circuit can be damaged by ESD. Burr-Brown  
recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling  
and installation procedures can cause damage.  
Plastic DIP  
Sync  
2
Gnd  
Freq Adj  
3
5
1
7
1
2
3
6
5
AC  
Gnd  
AC  
TO  
VD  
TO  
TO  
ESD damage can range from subtle performance degradation  
to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric  
changes could cause the device not to meet its published  
specifications.  
+V  
PWS740-1  
IN  
4
8
4
Return  
Enable  
6
PWS740-2  
TO  
(Drawings Not to Scale)  
PACKAGE INFORMATION  
PACKAGE DRAWING  
NUMBER(1)  
PRODUCT  
PACKAGE  
PWS740-1 Driver  
PWS740-2 Transformer  
TO-3  
6-Pin Plastic DIP  
030  
216  
NOTE: (1) For detailed drawing and dimension table, please see end of data  
sheet, or Appendix C of Burr-Brown IC Data Book.  
®
3
PWS740  
TYPICAL PERFORMANCE CURVES  
LINE REGULATION  
VRIPPLE vs CLOAD  
1 THROUGH 8 CHANNELS  
25  
25  
20  
15  
10  
5
±IO = ±15mA/Channel  
VIN = 15V  
I
O = ±15mA/Channel  
20  
15  
10  
5
1 channel  
4 or 8 channels  
0
0
0
0.2  
0.4  
0.6  
0.8  
1.0  
0
5
10  
15  
20  
25  
CLOAD (µF)  
VIN (V)  
EFFICIENCY vs LOAD 1,4, AND 8 CHANNELS  
OUTPUT VOLTAGE DRIFT  
100  
80  
60  
40  
20  
0
0
8 Channels  
4 Channels  
–5  
1 Channel  
VIN = +15V  
–10  
+25  
Temperature (°C)  
0
0
5
10  
15  
20  
25  
30  
–25  
+85  
+50  
±IOUT (mA)  
LOAD REGULATION 1, 4 AND 8 CHANNELS  
1 Channel  
FREQUENCY ADJUSTMENT RANGE  
20  
15  
10  
5
500  
400  
300  
200  
100  
0
4 and 8 Channel  
VIN = 15V  
See Functional Diagram  
0
5
10  
15  
20  
25  
30  
1
10  
100  
1k  
10k  
100k  
±IOUT (mA)  
Frequency Adjustment Resistor (  
)
Ω
®
4
PWS740  
If this feature is not required, leave the SYNC pin open. The  
SYNC pin is sensitive to capacitance loading. 150pF or less  
is recommended. Also external parasitic capacitive feedback  
between either TO and the SYNC pin can cause unstable  
operation (commonly seen as jitter in the TO outputs). Keep  
SYNC connections and TO lines as physically isolated as  
possible. Avoid shorting the SYNC pin directly to ground or  
supply potentials; otherwise, damage may result.  
PIN DESCRIPTIONS OF  
PWS740-1 DRIVER  
+VIN, RETURN, AND GND  
These are the power supply pins. The ground connection,  
RETURN, for the N-channel MOSFET sources is brought  
out separately from the ground connection for the oscillator/  
driver chip. The waveform of the FETs’ ground return  
current (and also the current in the VDRIVE line) is an 800kHz  
sawtooth. A capacitor between +VIN and the FET ground  
provides a bypass for the AC portion of this current.  
Figure 1 shows a method for synchronizing a greater number  
of PWS740-1 drivers. One unit is chosen as the master. Its  
synchronization signal, buffered by a high-speed unity gain  
amplifier can synchronize up to 20 slave units. Pin 1 of each  
slave unit must be grounded to assure synchronization.  
Minimize capacitive coupling between the buffered sync  
line and the outputs of the drivers, especially at the end of  
long lines. Capacitance to ground is not critical, but total  
stray capacitance between the sync line and switching out-  
puts should be kept below 50pF. Where extreme line lengths  
are needed, such as between printed circuit boards, addi-  
tional OPA633 buffers may be added to keep drive imped-  
ance at an acceptably low value. Because of temperature-  
influenced shifts in the switching levels, best operation of  
this circuit will occur when differences in ambient tempera-  
tures between the PWS740-1 drivers are minimized, typi-  
cally within a 35°C range.  
The power should never be instantaneously interrupted to  
the PWS740 system (i.e., a break in the line from V+, either  
accidental or by means of a series switch). Normal power-  
down of the V+ supply is not considered instantaneous.  
Should a rapid break in input power occur, however, the  
transformers’ voltage will rapidly increase to maintain cur-  
rent flow. Such a voltage spike may damage the PWS740-1.  
The bypass capacitors at the +VIN pin of the PWS740-1 and  
the VDRIVE pins of the transformers provide a path for the  
primary current if power is interrupted; however, total pro-  
tection requires some type of bidirectional 1A voltage clamp-  
ing at the +VIN pin. A low cost SA20A TransZorb® from  
General Semiconductor(1) or equivalent, which will clamp  
the +VIN pin between –0.6V and +23V, is recommended.  
TO AND TO  
These pins are the drains of the N-channel MOSFET switches  
which drive all the transformer primaries in parallel. The  
signals on these pins are 400kHz complementary square  
waves with twice the amplitude of the voltage at +VIN. It is  
these lines that allow the power to be distributed to the  
individual high voltage isolation transformers. Without proper  
printed circuit board layout techniques, these lines could  
generate interference to analog circuits. See the next section  
on PCB layout.  
8 Channels  
4
6
+15V  
OPA633  
–15V  
Master  
740-1  
1
2
NC  
Typical at  
25°C  
3.0V  
2.5V  
200ns  
400kHz  
4
ENABLE  
Slave  
740-1  
#1  
2
6
1
A high TTL logic level on this pin activates the MOSFET  
driver circuitry. A low TTL level applied to the ENABLE  
pin shuts down all drive to the transformers and the output  
voltages go to zero (only the oscillator is unaffected). For  
continuous operation, the ENABLE pin can be left open or  
tied to a voltage between +2V and +V.  
8 Channels  
4
2
6
Slave  
740-1  
#20  
SYNCHRONIZATION  
1
8 Channels  
The SYNC pin is used to synchronize up to eight PWS740-  
1 oscillators. Synchronization is useful to prevent beat fre-  
quencies in the supply voltages. The SYNC pins of two or  
more PWS740-1s are tied together to force all units to the  
same frequency of oscillation. The resultant frequency is  
slightly higher than that of the highest unsynchronized unit.  
FIGURE 1. Master/Slave Synchronization of Multiple  
PWS740 Drivers.  
(1) General Semiconductor Industries Inc., 2001 W. 10th Place, Tempe AZ 85281,  
602-968-3101.  
TransZorb® General Semiconductor Industries Inc.  
®
5
PWS740  
+VIN (7-20V)  
2N3904  
330Ω  
+5V  
1W  
2
PWS740-1  
4.0V(2)  
2.5V  
8
4
TTL Sync(1)  
1
Peripheral  
Driver  
(MC1472 or  
Equivalent)  
1
2
620Ω  
200ns  
3
2N3904  
1/8W  
2
PWS740-1  
100Ω  
1
Other  
Other  
PWS740s  
PWS740s  
NOTES: (1) See text for frequency range; duty cycle = 5-75%. (2) Typical waveform at 25°C. Active  
pull-up initiates synchronization; pulse width is set by PWS740 pull-down characteristics and is not  
affected by frequency of operation.  
FIGURE 2. External Synchronization of Multiple PWS740 Drivers with TTL-Level Signals.  
If larger temperature gradients are likely to occur, the user  
may wish to consider the synchronization method shown in  
Figure 2. This circuit is driven from an external TTL-  
compatible source such as a system clock or a simple free-  
running oscillator constructed of TTL gates. The output  
stage provides temperature compensation over the rated  
temperature range of the PWS740. The signal source fre-  
quency should be about 800kHz for rated performance, but  
may range from 500kHz to 2MHz with slightly reduced  
performance. Precautions with regard to circuit coupling and  
layout are the same as for the circuit of Figure 1. Repeaters  
using the OPA633 may be used for long line lengths.  
Symmetry and good high-frequency layout practice are  
important in successful application of both of these synchro-  
nization techniques.  
with the addition of two components—a bypass capacitor  
between the +VIN pin and ground, and a series inductor in the  
VDRIVE line. A 10µF tantalum capacitor is adequate for  
bypass. A parallel 0.33µF ceramic capacitor will extend the  
bandwidth of the tantalum. Additional bypass capacitors at  
each primary center-tap of the transformers are recom-  
mended. In general, the higher the capacitance, the lower the  
ripple, but the parasitic series inductance of the bypass  
capacitors will eventually be the limiting factor. The induc-  
tor value recommended is approximately 20µH. Greater  
reduction in ripple current is achieved with values up to  
100µH; then physical size may become a concern. The  
inductor should be rated for at least 2A and its DC resistance  
should be less than 0.1Ω. An example of a low cost indicator  
is part number 51591 from Pulse Engineering(2)  
.
Output voltage filtering is achieved with a 0.33µF capacitor  
connecting each VOUT pin of the diode bridge to ground.  
Short leads and close placement of the capacitors to the unit  
provide optimum high frequency bypassing. The 800kHz  
output ripple should be below 5mVp-p. Higher frequency  
noise bursts are also present at the outputs. They coincide  
with the switch times and are approximately 20mV in ampli-  
tude. Inductance of 10µH or less in series with the output  
loads will significantly reduce the noise as seen by the loads.  
FREQUENCY ADJUSTMENT  
The FREQ ADJ pin may be connected to an external  
potentiometer to lower an unsynchronized PWS740-1 oscil-  
lator frequency. This may be useful if the frequency of the  
PWS740-1 is too close to some other signal’s frequency in  
the system and beat interference is possible. See Typical  
Performance Curves. Use of this pin is not usually required;  
if not used, leave open for rated performance.  
PC BOARD LAYOUT CONSIDERATIONS  
THEORY OF OPERATION  
EXTERNAL FILTER COMPONENTS  
Multilayer printed circuit boards are recommended for  
PWS740 systems. Two-layer boards are certainly possible  
with satisfactory operation; however, three layers provide  
greater density and better control of interference from the  
FET switch signals. Should four-layer boards be required for  
other circuitry, the use of separate layers for power and  
ground planes, a layer for switching signals, and a layer for  
analog signals would allow the most straightforward layout  
for the PWS740 system. The following discussion pertains  
to a three- or four-layer board layout.  
Filter components are necessary to reduce the input ripple  
current and the output voltage noise. Without any input  
filtering, the sawtooth currents in the FET switches would  
flow in the +V supply line. Since this AC current can be as  
great as 1A peak, voltage interference with other compo-  
nents using this supply line would likely occur. The input  
ripple current can be reduced to approximately 1mA peak  
(2) Pulse Engineering, PO Box 12235, San Diego CA 92112, 619-268-2400.  
®
6
PWS740  
VDRIVE  
+
+15V  
20µH  
+V  
10µF  
0.3µF  
PWS740-2  
1
6
4
T
O
8
IN  
BAV99  
0.3µF  
2
5
PWS740-1  
0.3µF  
BAV99  
6
T
O
3
0.3µF  
4
3
5
10µH(2)  
Switch Power to  
Other 7 Channels  
+15V(1)  
–15V(1)  
Gnd1  
0.1µF  
0.1µF  
4
24  
1
System Uses:  
1 Oscillator/Driver  
8 Transformers  
8 Bridges  
13  
12  
Isolation  
Amplifier  
ISO102(3)  
2
4
14  
16  
8 ISO102s  
V 1  
IN  
1 Multiplexer  
Not all components are shown.  
1
5
6
7
12  
11  
AO  
16 AO  
VOUT  
10  
MPC8S  
Multiplexer  
13  
–15V  
Input  
From  
Other 7  
Channels 10  
9
8
GND  
22  
21  
14  
3
Offset  
–15V  
NOTES: (1) Supplies ±15mA of isolated supply current per channel.  
(2) WestCap DKM-10 or equivalent. (3) Or ISO120 or ISO122.  
FIGURE 3. Low Cost Eight-Channel Isolation Amplifier Block with Channel-to-Channel Isolation.  
Critical consideration should go to minimizing electromag-  
netic radiation from the switching signal’s lines. TO and TO.  
You can identify the path of the switching current by starting  
at the +VIN pin. The dynamic component of the current is  
supplied primarily from the bypass capacitor. The high  
frequency current flows through the inductor and down the  
VDRIVE line, through one side of the transformer windings,  
returning in the TO with the “on” FET switch, and then back  
up through the bypass capacitor. This current path defines a  
loop antenna which transmits magnetic energy. The mag-  
netic field lines reinforce at the center of the loop, while the  
field lines reinforce at the center of the loop, while the field  
lines from opposite points of the loop oppose each other  
outside the loop. Cancellation of magnetic radiation occurs  
when the loop is collapsed to two tightly spaced parallel line  
segments, each carrying the same current in opposite direc-  
tions. For this reason, the printed circuit traces for both TO  
connections should lay directly over a power plane forming  
the VDRIVE connection. This plane need not extend much  
wider than TO and TO. All of the current in the plane will  
flow directly under the TO traces because this is the path of  
least inductance (and least radiation).  
these lines. Additional shielding can be obtained by running  
ground trace(s) along the TO lines, which also facilitate  
minimum loop area connections for the transformer’s center  
tap bypass capacitors.  
The connections between the secondary (output side) of the  
transformer and the diode bridges should be kept as short as  
possible. Unnecessary stray capacitance on these lines could  
cause tuned circuit peaking to occur, resulting in a slight  
increase of output voltage.  
The PWS740 is intended for use with the ISO102, ISO120  
or ISO122 isolation amplifiers (see Figure 3). Place the  
PWS740-2 transformer on the VOUT side of the buffer rather  
than on the C1 (bandwidth control) side to prevent possible  
pickup of switch signal by the ISO102.  
The best ground connection ties the ISO102 output analog  
common pin to the PWS740-1 ground pin with a ground  
plane. This is where a four-layer board design becomes  
convenient. The digital ground of the ISO102 can be con-  
nected to the ground plane or closer to the +V supply. If  
possible, you should include the analog components that the  
ISO102 drives on the same board. For example, if several  
ISO102s are multiplexed to an analog/digital converter, then  
having all components sharing the same ground plane will  
significantly simplify ground errors. Avoid connecting  
Another potential problem with the TO lines is electric field  
radiation. Fortunately, the VDRIVE plane is effective at termi-  
nating most of the field lines because of its proximity to  
®
7
PWS740  
digital ground and the PWS740 ground together locally,  
leaving the ISO102 analog ground to be connected off of the  
board; the differential voltage between analog and digital  
ground may become too great.  
It should be noted that many analog circuit functions do not  
simultaneously draw full rated current from both the positive  
and negative supplies. Thus, the PWS740 can power more  
circuits per channel than is first apparent. For example, an  
operational amplifier does not draw maximum current from  
both supplies simultaneously. If a circuit draws 10mA from  
the positive supply and 3mA from the negative supply, the  
PWS740 could power (60 ÷ 13), about four devices per  
channel.  
OUTPUT CURRENT RATINGS  
The PWS740-1 driver contains “soft-start” driver circuitry  
to protect the driver FETs and eliminate high inrush currents  
during turn-on. Because the PWS740 can have between one  
and eight channels connected, it was not possible to provide  
a suitable internal current limit within the driver. Instead,  
impedance-limiting protects the driver and transformer from  
overload. This means that the internal impedance of each  
PWS740-2 transformer is high enough that, when short-  
circuited at its output, it limits the current drawn from the  
driver to a safe value. In addition, the wire size and mass of  
the transformer are large enough that the transformer does  
not receive damage under continuous short-circuit condi-  
tions.  
ISOLATION VOLTAGE RATINGS  
Because a long-term test is impractical in a manufacturing  
situation, the generally accepted practice is to perform a  
production test at a higher voltage for some shorter period of  
time. The relationship between actual test conditions and the  
continuous derated maximum specification is an important  
one. Burr-Brown has chosen a deliberately conservative  
one: VTEST = (2 x VCONTINUOUS RATING) + 1000V. This  
choice is appropriate for conditions where system transient  
voltages are not well defined.(3) Where the real voltages are  
well-defined or where the isolation voltage is not continu-  
ous, the user may choose a less conservative derating to  
establish a specification from the test voltage.  
The PWS740-1 is capable of driving up to eight individual  
channels to their full current rating. The total current which  
can be drawn from each isolation channel is a function of  
total power being drawn from both DC V+ and V– outputs.  
For example, if one output is not used, then maximum  
current can be drawn from the other output. In all cases, the  
maximum total current that can be drawn from any indi-  
vidual channel is:  
| IL + | + | IL – | ≤ 60mA  
(3) Reference National Electrical Manufacturers Association (NEMA) Standards part  
ICS I-109 and ICS1-111.  
®
8
PWS740  
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HAMMOND

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ADVANTECH

 		PWS-440-6E000E [ 3.7" Ultra Rugged PDA ] 2 页

ADVANTECH

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ADVANTECH

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