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PWS725A

型号：

PWS725A

描述：

隔离，非稳压DC / DC转换器[ Isolated, Unregulated DC/DC CONVERTERS ]

品牌：

BB[ BURR-BROWN CORPORATION ]

页数：

6 页

PDF大小：

71 K

下载PDF手册
PWS725A  
PWS726A  
Isolated, Unregulated  
DC/DC CONVERTERS  
FEATURES  
● ISOLATED ±7 TO ±18VDC OUTPUT FROM  
● PROTECTED AGAINST OUTPUT FAULTS  
● COMPACT  
SINGLE 7 TO 18VDC SUPPLY  
● ±15mA OUTPUT AT RATED VOLTAGE  
● LOW COST  
ACCURACY  
● EASY TO APPLY—FEW EXTERNAL PARTS  
● HIGH ISOLATION VOLTAGE  
PWS725A, 1500Vrms  
PWS726A, 3500Vrms  
APPLICATIONS  
● MEDICAL EQUIPMENT  
● INDUSTRIAL PROCESS EQUIPMENT  
● TEST EQUIPMENT  
● LOW LEAKAGE CAPACITANCE: 9pF  
● LOW LEAKAGE CURRENT: 2µA max,  
at 240VAC 50/60Hz  
● HIGH RELIABILITY DESIGN  
● DATA ACQUISITION  
● AVAILABLE WITH OUTPUT  
SYNCHRONIZATION SIGNAL FOR USE  
WITH ISO120 AND ISO121  
DESCRIPTION  
The PWS725A and PWS726A convert a single 7 to  
18VDC input to bipolar voltages of the same value as  
the input voltage. The converters are capable of  
providing ±15mA at rated voltage accuracy and up to  
±40mA without damage. (See Output Current Rating.)  
oscillator before either MOSFET driver turns on,  
protects the switches, and eliminates high inrush cur-  
rents during turn-on. Input current sensing protects  
both the converter and the load from possible thermal  
damage during a fault condition.  
The PWS725A and PWS726A converters provide  
reliable, engineered solutions where isolated power is  
required in critical applications. The high isolation  
voltage rating is achieved through use of a specially-  
designed transformer and physical spacing. An addi-  
tional high dielectric-strength, low leakage transformer  
coating increases the isolation rating of the PWS726A.  
Special design features make these converters  
especially easy to apply. The compact size allows  
dense circuit layout while maintaining critical isola-  
tion requirements. The Input Sync connection allows  
frequency synchronization of multiple converters. The  
Output Sync is available to synchronize ISO120 and  
ISO121 isolation amplifiers. The Enable input allows  
control over output power in instances where  
shutdown is desired to conserve power, such as in  
battery-powered equipment, or where sequencing of  
power turn-on/turn-off is desired.  
Reliability and performance are designed in. The  
bifilar wound, wirebonded transformer simultaneously  
provides lower output ripple than competing designs,  
and a higher performance/cost ratio. The soft-start  
oscillator/driver design assures full operation of the  
International Airport Industrial Park  
•
Mailing Address: PO Box 11400  
Cable: BBRCORP  
•
Tucson, AZ 85734  
•
Street Address: 6730 S. Tucson Blvd.  
• Tucson, AZ 85706  
Tel: (520) 746-1111 Twx: 910-952-1111  
•
•
•
Telex: 066-6491  
•
FAX: (520) 889-1510  
•
Immediate Product Info: (800) 548-6132  
© 1987 Burr-Brown Corporation  
PDS-736D  
Printed in U.S.A. October, 1993  
SPECIFICATIONS  
ELECTRICAL  
TA = +25°C, CL = 1µF ceramic, VIN = 15VDC, operating frequency = 800kHz, VOUT = ±15VDC, CIN = 1µF ceramic, IOUT = ±15mA, unless otherwise specified.  
PWS725A  
TYP  
PSW726A  
TYP  
PARAMETER  
CONDITIONS  
MIN  
MAX  
MIN  
MAX  
UNITS  
INPUT  
Rated Voltage  
Input Voltage Range  
Input Current  
15  
*
VDC  
VDC  
mA  
mAp-p  
mAp-p  
mAp-p  
7
18  
*
*
I
O = ±15mA  
77  
150  
5
*
*
*
Input Current Ripple  
No External Filtering  
L-C Input Filter, LIN = 100µH, CIN = 1µF(1)  
C Only, CIN = 1µF  
60  
ISOLATION  
Test Voltages  
Input to Output, 10 seconds  
Input to Output, 60 seconds, min  
Input to Output, Continuous, AC 60Hz  
Input to Output, Continuous DC  
Input to Output  
4000  
1500  
8000  
3500  
VDC  
Vrms  
Vrms  
VDC  
Ω || pF  
µA  
Rated Voltage  
1500  
2121  
3500  
4950  
Isolation Impedance  
Leakage Current  
1012 || 9  
1.2  
*
*
Input to Output, 240Vrms, 60Hz  
2.0  
*
OUTPUT  
Rated Output Voltage  
Output Current  
14.25  
15  
15  
15.75  
40  
80  
*
*
*
*
*
*
*
VDC  
mA  
mA  
%/mA  
mVp-p  
mVp-p  
Balanced Loads  
Single-Ended  
Balanced Loads, ±10mA < IOUT < ±40mA  
No External Capacitor  
Load Regulation  
Ripple Voltage (400kHz)  
0.4  
60  
10  
*
*
L
O = 10µH, CO = 1µF (Figure 1)  
O = 0µH, CO Filter Only  
O = 10µH, CO = 1µF  
See Performance Curves  
L
Output Switching Noise  
Output Capacitive Load  
L
L
1
*
mVp-p  
µF  
µF  
O = 100µH, C Filter  
C Filter Only  
10  
1
*
*
Voltage Balance, V+, V–  
Sensitivity to ∆VIN  
Output Voltage Temp. Coefficient  
Output Sync Signal  
0.04  
1.15  
10  
%
V/V  
mV/°C  
Vp-p  
Square Wave, 50% Duty Cycle  
30  
*
TEMPERATURE  
Specification  
Operating  
–25  
–25  
–25  
+85  
+85  
+125  
*
*
*
*
*
*
°C  
°C  
°C  
Storage  
* Specification same as PWS725A.  
PACKAGE INFORMATION(1)  
PIN CONFIGURATION  
Top View  
DIP  
PACKAGE DRAWING  
NUMBER  
MODEL  
PACKAGE  
1
2
3
4
32  
+VO  
–VO  
NC  
PWS725A  
PWS726A  
32-Pin Ceramic DIP  
32-Pin Ceramic DIP  
210  
210  
31 NC  
NOTE: (1) For detailed drawing and dimension table, please see end of data  
sheet, or Appendix D of Burr-Brown IC Data Book.  
NC  
30 Output Ground  
29 Output Sync  
Output Ground  
NC 13  
Input Ground 14  
Input Sync 15  
VIN 16  
20 Frequency Adjust  
19 Frequency Adjust  
18 Enable  
17 NC  
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes  
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change  
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant  
any BURR-BROWN product for use in life support devices and/or systems.  
®
2
PWS725A/726A  
TYPICAL PERFORMANCE CURVES  
TA = +25°C, VCC = ±15VDC unless otherwise noted.  
LOAD REGULATION  
OUTPUT CAPACITANCE vs RIPPLE VOLTAGE  
20  
100  
90  
80  
70  
60  
50  
40  
30  
20  
VIN = +15V  
IO = ±15mA  
18  
16  
14  
V
IN = ±15V  
Balanced Loads  
Single-ended Loads  
Peak-to-Peak  
DC < f < 20MHz  
Capacitor Only  
12  
10  
10  
0
L-C Filter, L = 100µH  
0
10  
20  
20  
40  
30  
60  
40 Balanced  
80 Single  
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
Capacitance (µF)  
1
Output Current (mA)  
LINE REGULATION  
IO = ±15mA  
MAXIMUM POWER DISSIPATION  
20  
2
18  
16  
14  
12  
10  
8
1.44  
1
6
4
0
6
7
8
10  
12  
14  
16  
18  
–25  
0
25  
50  
75 85  
100  
Input Voltage (V)  
Temperature (°C)  
OUTPUT VOLTAGE DRIFT  
INPUT CURRENT vs OUTPUT CURRENT  
0
–1  
–2  
–3  
–4  
–5  
140  
77  
70  
–6  
–50  
0
0
50  
Temperature (°C)  
85 100  
0
±15  
±30  
±45  
IO (mA)  
®
3
PWS725A/726A  
TYPICAL PERFORMANCE CURVES (CONT)  
TA = +25°C, VCC = ±15VDC unless otherwise noted.  
SYNC FREQUENCY vs  
INPUT CURRENT AND OUTPUT VOLTAGE  
VIN = +15V  
90  
80  
70  
60  
±VOUT  
15  
14  
IINPUT (IO = ±15mA)  
400  
800  
1200  
1600  
SYNC Frequency (kHz)  
(Optional External Control)  
THEORY OF OPERATION  
The PWS725A and the PWS726A DC/DC converters con-  
sist of a free-running oscillator, control and switch driver  
circuitry, MOSFET switches, a transformer, a bridge recti-  
fier, and filter capacitors together in a 32-pin DIP (0.900  
inches nominal) package. The control circuitry consists of  
current limiting, soft start, frequency adjust, enable, and  
synchronization features. See Figure 1. In instances where  
several converters are used in a system, beat frequencies  
developed between the converters are a potential source of  
low frequency noise in the supply and ground paths. This  
noise may couple into signal paths. See Figures 2 and 3 for  
connection of INPUT SYNC pin. Converters can be syn-  
chronized and these beat frequencies avoided. The unit with  
the highest natural frequency will determine the synchro-  
nized running frequency. To avoid excess stray capaci-  
tance, the INPUT SYNC pin should not be loaded with  
more than 50pF. If unused, the INPUT SYNC must be left  
open.  
Soft start circuitry protects the MOSFET switches during  
start up. This is accomplished by holding the gate-to-source  
voltage of both MOSFET switches low until the free-  
running oscillator is fully operational. In addition to that  
soft start circuitry, input current sensing also protects the  
MOSFET switches. This current limiting keeps the FET  
OUTPUT SYNC  
29  
(5)  
LIN  
RSC  
VIN  
7-18/VDC  
16  
(4)  
(5)  
LO  
+IO  
CIN  
0.22µF  
+VOUT  
32  
+
20  
(4)  
(4)  
CO  
20kΩ  
Oscillator/  
Driver  
Control  
Full-Wave  
Bridge  
Rectifier  
–
Frequence  
Increase(1)  
+
–
4 & 30  
CO  
19  
0.22µF  
1
–VOUT  
0.22µF  
–IO  
(4)  
LO  
18  
15  
14  
ENABLE(3) INPUT  
SYNC(2)  
NOTES: (1) Frequency Adjust is optional, with pins 19 and 20 left open. The normal switching frequency is 800kHz.  
(2) Leave INPUT SYNC pin open if unused; limit stray capacitance on INPUT SYNC pin to less than 50pF.  
(3) Leave ENABLE pin open or connect to VIN if not used.  
(4) Optional output filtering, with LO = 0, limit CO ≤ 1µF, with LO = 100µH, limit CO ≤ 10µF, see Performance  
Curves for LO = 0.  
(5) Optional input filtering, see Performance Curves for LIN = 0.  
(6) CAUTION: Do not connect pin 29 to low impedance loads. See Figure 5.  
FIGURE 1. PWS725A/726A Functional Diagram.  
®
4
PWS725A/726A  
+7V to +18 V  
+7V to +18 V  
MC1472  
or Equivalent  
Peripheral  
+VCC  
Driver  
+5V  
16  
330Ω  
1W  
8
1
15  
4
8
Master  
PWS725A  
3
OPA633  
Slave  
PWS725A/726A  
2N3904  
TTL  
Buffer  
2
4
SYNC  
15  
Signal(2)  
PWS725A/726A  
–VCC  
16  
620Ω  
15  
19(1)  
16  
1/8W  
Keep Connection  
Short  
2N3904  
19(1)  
100Ω  
Slave  
PWS725A/726A  
15  
NOTE: (1) Units to be synchronized  
should have a lower free-running  
frequency than the master unit.  
Grounding Frequency Adjust (pin 19)  
will shift the free-running frequency  
to approximately 400kHz.  
PWS725A/726A  
NOTES: (1) Units to be synchronized  
should have a lower free-running  
frequency than the TTL signal.  
16  
15  
19(1)  
16  
19(1)  
Grounding Frequency Adjust (Pin 19)  
will shift the free-running frequency  
to approximately 400kHz. (2) The TTL  
SYNC signal can have a frequency  
range of 450kHz to 1.5MHz.  
To Other  
PWS725A/726A  
Converters  
To Other  
PWS725A/726A  
Converters  
FIGURE 2. Synchronization of Multiple PWS725As or  
PWS726As from a Master Converter.  
FIGURE 3. Synchronization of Multiple PWS725As or  
PWS726As from an External TTL Signal.  
switches operating in their safe operating area under fault  
conditions or excessive loads. When either of these condi-  
tions occur, the peak input current exceeds a safe limit. The  
result is an approximate 5% duty cycle, 300µs drive period  
to the MOSFET switches. This protects the internal MOSFET  
switches as well as the external load from any thermal  
damage. When the fault or excessive load is removed, the  
converter resumes normal operation. A delay period of  
approximately 50µs incorporated in the current sensing  
circuitry allows the output filter capacitors to fully charge  
after a fault is removed. This delay period corresponds to a  
filter capacitance of no more than 1µF at either of the output  
pins. This provides full protection of the MOSFET switches  
and also sufficiently filters the output ripple voltage (see  
specification table). The current sensing circuitry is de-  
signed to provide thermal protection for the MOSFET  
switches over the operating temperature range as well. The  
low thermal resistance for the package (θJC = 10°C/W)  
ensures safe operation under rated conditions. When these  
rated conditions are exceeded, the unit will go into its  
shutdown mode.  
PWS725A/726A  
Monitor frequency with scope  
or frequency counter (use  
15  
low C probe).  
19  
20kΩ  
20  
(1)  
Frequency  
Increase  
+5VBE  
+4VBE  
1.25µs Nominal  
SYNC Signal  
NOTE: (1) For nominal 800kHz operation, leave  
pins 19 and 20 open.  
FIGURE 4. Frequency Adjustment Procedure.  
OUTPUT CURRENT RATING  
An optional potentiometer can be connected between the  
two FREQUENCY ADJUST pins to trim the oscillator  
operating frequency ±10% (see Figure 4). Care should be  
taken when trimming the frequency near the low frequency  
range. If the frequency is trimmed too low, the peak induc-  
tive currents in the primary will trip the input current  
sensing circuitry to protect the MOSFET switches from  
these peak inductive currents.  
The total current which can be drawn from the PWS725A  
or PWS726A is a function of total power being drawn from  
both outputs (see Functional Diagram). If one output is not  
used, then maximum current can be drawn from the other  
output. If both outputs are loaded, the total current must be  
limited such that:  
|IL+| + |IL–| ≤ 80mA  
It should be noted that many analog circuit functions do not  
simultaneously draw full rated current from both the posi-  
tive and negatives supplies. For example, an operational  
amplifier may draw 13mA from the positive supply under  
The ENABLE pin allows external control of output power.  
When this pin is pulled low, output power is disabled. Logic  
thresholds are TTL compatible. When not used, the Enable  
input may be left open or tied to VIN (pin 16).  
®
5
PWS725A/726A  
full load while drawing only 3mA from the negative supply.  
Under these conditions, the PWS725A/726A could supply  
power for up to five devices (80mA ÷ 16mA ≈ 5). Thus, the  
PWS725A/726A can power more circuits than is at first  
apparent.  
OUTPUT SYNC SIGNAL  
To allow synchronization of an ISO120 or ISO121 isolation  
amplifier, the PWS725A and PWS726A have an OUTPUT  
SYNC signal at pin 29. It should be connected as shown in  
Figure 5 to keep capacitive loading of pin 29 to a minimum.  
If output sync is not used, leave pin open.  
ISOLATION VOLTAGE RATINGS  
Because a long-term test is impractical in a manufacturing  
situation, the generally accepted practice is to perform a  
production test at a higher voltage for some shorter period of  
time. The relationship between actual test conditions and the  
continuous derated maximum specification is an important  
one. Burr-Brown has chosen a deliberately conservative  
one: VDCTEST = (2 X VACrmsCONTINUOUS RATING) + 1000V for  
ten seconds. This choice is appropriate for conditions where  
system transient voltages are not well defined.(1) Where the  
real voltages are well-defined or where the isolation voltage  
is not continuous, the user may choose a less conservative  
derating to establish a specification from the test voltage.  
Ext Osc  
Connection  
of  
ISO120  
or  
20kΩ  
4
29  
PWS725A/726A  
20pF  
ISO121  
FIGURE 5. Synchronization with ISO120 or ISO121 Isola-  
tion Amplifier.  
NOTE: (1) Reference National Electrical Manufacturers Association (NEMA)  
Standards Parts ICS I-109 and ICS I-111.  
®
6
PWS725A/726A  
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