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8X931AA

型号:

8X931AA

描述:

通用串行总线外围设备控制器[ UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLERS ]

品牌:

INTEL[ INTEL ]

页数:

30 页

PDF大小:

223 K

ADVANCE INFORMATION  
8x931AA/8x931HA  
UNIVERSAL SERIAL BUS  
PERIPHERAL CONTROLLERS  
8x931AA Hubless USB Peripheral  
8x931HA Includes all 8x931AA  
Controller  
Features  
On-chip USB Transceivers  
On-chip Phase-locked loop  
FIFO Data Buffers  
8x931HA USB Hub has One Internal  
Downstream, and Four External  
Downstream Ports  
— Universal Serial Bus Specification  
1.0 Compliant  
— Two Pairs of 8-byte Transmit and  
Receive FIFOs  
— Serves as both USB Hub and USB  
Embedded Function (Internal Port)  
— One Pair of 16-byte Transmit and  
Receive FIFOs  
USB Hub  
— Supports Isochronous and  
Non-isochronous Data  
— Connectivity Management  
— Downstream Device  
Automatic FIFO Management  
Three USB Interrupt Vectors  
— Endpoint Transmit/Receive Done  
— Start of Frame  
Connect/Disconnect Detection  
— Power Management, Including  
Suspend and Resume  
— Bus Fault Detection and Recovery  
— Global Suspend/Resume/USB Reset  
— Full and Low Speed Downstream  
Device Support  
Regulated 3V Output for Root Port  
Pullup Resistor  
Hub Endpoint Done Interrupt  
Output Pin for Port Power Switching  
Input Pin for Overcurrent Detection  
Hub FIFO Data Buffers  
On-chip ROM Options  
— 0 or 8 Kbytes  
256 bytes On-chip Data RAM  
Four Input/Output Ports  
MCS® 51 UART  
— One Pair of 8-byte Transmit and  
Receive FIFOs  
— One 1-byte Transmit Register  
Three 16-bit Timer/Counters  
Keyboard Control Interface  
Four Dedicated LED Driver Outputs  
6- or 12-MHz Crystal Operation  
— Low Clock Mode (3MHz)  
Embedded Function FIFO Data Buffers  
— Same as the 8x931AA  
12-MHz Crystal Operation  
— Low Clock Mode (3MHz)  
The 8x931AA and 8x931HA USB peripheral controllers are based on the MCS®51 microcontroller. They  
consist of standard 8XC51Fx peripherals plus a USB module. The 8x931HA USB module provides both USB  
hub and USB embedded function capabilities. The 8x931HA supports USB hub functionality, embedded  
function, suspend/resume modes, isochronous/non-isochronous transfers, and is USB rev 1.0 specification  
compliant. The USB module contains one internal and 4 external downstream ports and integrates the USB  
transceivers, serial bus interface engine (SIE), hub interface unit (HIU), function interface unit (FIU), and  
transmit/receive FIFOs. The 8x931AA is a hubless USB peripheral controller which contains the same  
feature set as the 8x931HA hub controller except for the hub module. The 8x931AA/HA uses the standard  
instruction set of the MCS 51 architecture.  
COPYRIGHT © INTEL CORPORATION, 1997  
November 1997  
Order Number: 273108-002  
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or oth-  
erwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of  
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to  
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or  
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life  
saving, or life sustaining applications.  
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.  
*Third-party brands and names are the property of their respective owners.  
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.  
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be  
obtained from:  
Intel Corporation  
Literature Sales  
PO Box 5937  
Denver, CO 80217-9808  
or call 1-800-548-4725  
COPYRIGHT © INTEL CORPORATION, 1997  
CONTENTS  
1.0 About This Document.......................................................................................................... 1  
1.1 Additional Information Sources ...................................................................................... 1  
1.2 Electronic Information..................................................................................................... 1  
1.3 Product Summary........................................................................................................... 2  
2.0 Nomenclature Overview...................................................................................................... 4  
3.0 Pinout.................................................................................................................................. 6  
3.0.1  
3.0.2  
8x931HA 68-pin PLCC Package ..................................................................................6  
8x931AA 68-pin PLCC Package ..................................................................................7  
4.0 Signals .............................................................................................................................. 10  
5.0 Electrical Characteristics................................................................................................... 13  
5.1 Operating Frequencies................................................................................................. 14  
5.2 DC Characteristics........................................................................................................ 15  
5.3 Explanation of Timing Symbols.................................................................................... 17  
5.4 System Bus AC Characteristics.................................................................................... 18  
5.4.1  
System Bus Timing Diagrams ....................................................................................19  
5.5 AC Characteristics — Synchronous Mode 0................................................................ 21  
5.6 External Clock Drive..................................................................................................... 22  
5.7 Testing Waveforms ...................................................................................................... 23  
6.0 Thermal Characteristics .................................................................................................... 24  
7.0 Design Considerations...................................................................................................... 24  
7.1 Low Clock Mode Frequency......................................................................................... 24  
7.2 Setting RXFFRC Bit Clears Only the Oldest Packet in the FIFO ................................. 24  
7.3 Series Resistor Requirement for Impedance Matching................................................ 24  
7.4 Pullup Resistor Requirement for 8x931AA/HA devices................................................ 24  
7.5 Powerdown Mode Cannot Be Invoked Before USB Suspend...................................... 24  
7.6 Unused Downstream Ports........................................................................................... 24  
7.7 ECAP Usage to Supply 3.0 to 3.6 Volts for 1.5K Ohm Pullup...................................... 24  
8.0 8x931AA/HA Errata........................................................................................................... 25  
9.0 Datasheet Revision History............................................................................................... 25  
iii  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
Figures  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
9.  
8x931 Functional Block Diagram..........................................................................................2  
8x931HA USB Module Block Diagram.................................................................................3  
Product Nomenclature .........................................................................................................4  
8x931HA 68-pin PLCC Package..........................................................................................6  
8x931AA 68-pin PLCC Package..........................................................................................7  
8x931AA/HA External Program Memory Read ..................................................................19  
8x931AA/HA External Data Memory Read ........................................................................20  
8x931AA/HA External Data Memory Write.........................................................................20  
Serial Port Waveform — Synchronous Mode 0..................................................................21  
10. External Clock Drive Waveforms........................................................................................22  
11. AC Testing Input, Output Waveforms.................................................................................23  
12. Float Waveforms................................................................................................................23  
Tables  
1.  
2.  
3.  
5.  
4.  
6.  
7.  
8.  
9.  
Related Documentation........................................................................................................1  
Electronic Information ..........................................................................................................1  
Description of Product Nomenclature...................................................................................4  
8x931AA Proliferation Options .............................................................................................5  
8x931HA Proliferation Options.............................................................................................5  
68-pin PLCC Pin Assignment...............................................................................................8  
68-pin PLCC Signal Assignments Arranged by Functional Category ..................................9  
Signal Description ..............................................................................................................10  
8x931AA/8x931HA Supply Voltages..................................................................................13  
10. 8x931HA Operating Frequency..........................................................................................14  
11. 8x931AA Operating Frequencies.......................................................................................14  
12. DC Characteristics at Operating Conditions.......................................................................15  
13.  
AC Timing Symbol Definitions...........................................................................................17  
14. External Bus Characteristics..............................................................................................18  
15. Serial Port Timing — Synchronous Mode 0.......................................................................21  
16. External Clock Drive...........................................................................................................22  
17. Thermal Characteristics .....................................................................................................24  
18. Vcc and Typical ECAP Voltages........................................................................................25  
iv  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
1.2 Electronic Information  
1.0 ABOUT THIS DOCUMENT  
This data sheet contains advance information about  
Intel’s 8x931AA and 8x931HA Universal Serial Bus  
peripheral controllers, based on the MCS®51  
peripheral controller, which includes a functional  
overview, mechanical data, targeted electrical  
specifications (simulated), and bus functional  
waveforms. A detailed functional description, other  
than parametric performance, is published in the  
8x931AA, 8x931HA Universal Serial Bus Peripheral  
Controller User’s Manual (273102-001).  
We offer a variety of technical and product infor-  
mation through the World Wide Web (see Table 2  
for URL) and through FaxBack service which is an  
on-demand publishing system that sends  
documents to your fax machine. You can get  
product announcements, change notifications,  
product literature, device characteristics, design  
recommendations, and quality and reliability infor-  
mation 24 hours a day, 7 days a week. Just dial the  
telephone number and respond to the system  
prompts.  
1.1 Additional Information Sources  
Intel documentation is available from your local Intel  
Sales Representative or Intel Literature Sales.  
Intel Corporation  
Literature Sales  
PO Box 5937  
Denver, CO 80217-9808  
or call 1-800-548-4725  
Table 1. Related Documentation  
Document Title  
Order/Contact  
8x931AA, 8x931HA Universal Serial Bus Peripheral  
Controller User’s Manual  
Intel Order #273102-001  
Intel Order #272904  
Universal Serial Bus Specification, Rev. 1.0  
Table 2. Electronic Information  
Document Title  
Order/Contact  
Intel’s World-Wide Web (WWW) Location:  
Customer Support (US and Canada):  
FaxBack Service:  
http://www.intel.com/design/usb/  
800-628-8686  
US and Canada  
800-628-2283  
+44(0)793-496646  
916-356-3105  
Europe  
worldwide  
Application Bulletin Board Service:  
up to 14.4-Kbaud line, worldwide  
dedicated 2400-baud line, worldwide  
Europe  
916-356-3600  
916-356-7209  
+44(0)793-496340  
ADVANCE INFORMATION  
1
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
1.3 Product Summary  
Data  
Address  
Register  
Program  
Address  
Register  
Program  
Counter  
Upstream  
Port  
RAM  
ROM  
USB  
Module  
B
ACC  
Stack  
Pointer  
Downstream  
Ports  
ALU  
HA only  
Data  
Pointer  
On-chip  
Peripherals  
Instruction  
Sequencer  
Parallel  
Ports  
Clock  
and  
Reset  
A4518-01  
Figure 1. 8x931 Functional Block Diagram  
2
ADVANCE INFORMATION  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
USB External  
Downstream Ports  
DM2  
DP2  
Transceiver  
USB Upstream Port  
(Hub Root Port)  
DM3  
DP3  
Transceiver  
DM0  
Repeater  
Transceiver  
DP0  
DM4  
Transceiver  
DP4  
DM5  
Transceiver  
DP5  
Serial Bus Interface Engine  
(SIE)  
Hub  
Interface  
Unit  
Function  
Interface  
Unit  
(HIU)  
(FIU)  
Control  
Transmit/Receive Bus  
To  
CPU  
Data Bus  
Control  
FIFOs  
A5247-01  
Figure 2. 8x931HA USB Module Block Diagram  
ADVANCE INFORMATION  
3
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
2.0 NOMENCLATURE OVERVIEW  
X
XX  
8
X
X
XXXXX XX  
A2815-01  
Figure 3. Product Nomenclature  
Table 3. Description of Product Nomenclature  
Options Description  
Parameter  
Temperature and Burn-in  
no mark Commercial operating temperature range (0oC to 70oC) with  
Intel standard burn-in  
Packaging Options  
N
0
3
Plastic Leaded Chip Carrier (PLCC)  
Without ROM  
Program Memory Options  
With ROM  
Process and Voltage Information no mark CHMOS  
Product Family  
931Hx  
Advanced 8-bit microcontroller architecture with on-chip  
Universal Serial Bus Hub and Function capability. Indicates  
ROM size, RAM size, and quantity of external downstream  
ports (see Table 4).  
931Ax  
Advanced 8-bit microcontroller architecture with on-chip  
Universal Serial Bus Function capability. Indicates ROM  
size, RAM size, and quantity of external downstream ports  
(see Table 5).  
Device Speed  
no mark 6 or 12 MHz crystal (8x931AA), 12MHz crystal (8x931HA)  
4
ADVANCE INFORMATION  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
Table 4. 8x931HA Proliferation Options  
Part Name  
N80931HA  
N83931HA  
ROM Size  
0
RAM Size  
256 bytes  
256 bytes  
Package  
68-pin PLCC  
68-pin PLCC  
8 Kbytes  
Table 5. 8x931AA Proliferation Options  
Part Name  
N80931AA  
N83931AA  
ROM Size  
0
RAM Size  
256 bytes  
256 bytes  
Package  
68-pin PLCC  
68-pin PLCC  
8 Kbytes  
ADVANCE INFORMATION  
5
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
3.0 PINOUT  
3.0.1 8x931HA 68-pin PLCC Package  
Figure 4 illustrates a diagram of the 8x931HA PLCC package. Table 6 and Table 7 contain indexes of the pin  
arrangement. Table 8 contains the signal descriptions for all pins.  
.
D
D
D
D
V
AD7 / P0.7 / KSI7  
AD6 / P0.6 / KSI6  
AD5 / P0.5 / KSI5  
AD4 / P0.4 / KSI4  
AD3 / P0.3 / KSI3  
AD2 / P0.2 / KSI2  
AD1 / P0.1 / KSI1  
AD0 / P0.0 / KSI0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
P4  
M4  
P5  
M5  
CC  
D
P0  
D
8x931Hx  
M0  
ECAP  
V
V
SS  
SS  
V
V
CC  
CC  
V
P3.0 / OVRI#  
P3.1 / SOF#  
P3.2 / INT0#  
SS  
View of component as  
mounted on PC board  
D
P3  
D
M3  
V
P3.3 / INT1#  
SS  
D
P3.4 / T0 / KSO16  
P3.5 / T1 / KSO17  
P3.6 / WR# / KSO18  
P2  
D
M2  
LED0  
Note:  
Reserved pins must be left unconnected.  
A5340-02  
Figure 4. 8x931HA 68-pin PLCC Package  
6
ADVANCE INFORMATION  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
3.0.2 8x931AA 68-pin PLCC Package  
Figure 5 illustrates a diagram of the 8x931AA PLCC package. Table 6 and Table 7 contain indexes of the pin  
arrangement. Table 8 contains the signal descriptions for all pins.  
Reserved (NC)  
Reserved (NC)  
Reserved (NC)  
Reserved (NC)  
AD7 / P0.7 / KSI7  
AD6 / P0.6 / KSI6  
AD5 / P0.5 / KSI5  
AD4 / P0.4 / KSI4  
AD3 / P0.3 / KSI3  
AD2 / P0.2 / KSI2  
AD1 / P0.1 / KSI1  
AD0 / P0.0 / KSI0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
V
CC  
D
P0  
D
8x931Ax  
M0  
ECAP  
V
V
SS  
SS  
V
V
CC  
CC  
V
P3.0  
P3.1 / SOF#  
P3.2 / INT0#  
SS  
View of component as  
mounted on PC board  
Reserved (NC)  
Reserved (NC)  
V
P3.3 / INT1#  
SS  
Reserved (NC)  
Reserved (NC)  
LED0  
P3.4 / T0 / KSO16  
P3.5 / T1 / KSO17  
P3.6 / WR# / KSO18  
Note:  
Reserved pins must be left unconnected.  
A5348-02  
Figure 5. 8x931AA 68-pin PLCC Package  
ADVANCE INFORMATION  
7
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
Table 6. 68-pin PLCC Pin Assignment  
Pin  
1
Name  
Pin  
24  
Name  
P3.4/T0/KSO16  
Pin  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
Name  
VSS  
VSS  
Reserved/ DM3  
Reserved/ DP3  
††  
††  
2
A15/P2.7/KSO15  
A14/P2.6/KSO14  
A13/P2.5/KSO13  
A12/P2.4/KSO12  
A11/P2.3/KSO11  
A10/P2.2/KSO10  
A9/P2.1/KSO9  
A8/P2.0/KSO8  
AD7/P0.7/KSI7  
AD6/P0.6/KSI6  
AD5/P0.5/KSI5  
AD4/P0.4/KSI4  
AD3/P0.3/KSI3  
AD2/P0.2/KSI2  
AD1/P0.1/KSI1  
AD0/P0.0/KSI0  
VSS  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
P3.5/T1/KSO17  
P3.6/WR#/KSO18  
P3.7/RD#/KSO19  
P1.0/T2/KSO0  
P1.1/T2EX/KSO1  
P1.2/KSO2  
P1.3/KSO3  
P1.4/KSO4  
P1.5/KSO5  
P1.6/KSO6/RXD  
P1.7/KSO7/TXD  
LED3  
3
4
VSS  
5
VCC  
VSS  
6
7
ECAP  
DM0  
DP0  
VCC  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
††  
Reserved/ DM5  
Reserved/ DP5  
Reserved/ DM4  
Reserved/ DP4  
Reserved (NC)  
Reserved (NC)  
VSS  
††  
††  
††  
LED2  
XTAL1  
XTAL2  
AVCC  
RST  
FSSEL/ UPWEN#††  
VCC  
PLLSEL  
PSEN#  
ALE  
P3.0/ OVRI#††  
LED1  
P3.1/SOF#  
LED0  
EA#  
††  
P3.2/INT0#  
Reserved/ DM2  
VCC  
††  
P3.3/INT1#  
Reserved/ DP2  
Specific to the 8x931AA  
†† Specific to the 8x931HA  
8
ADVANCE INFORMATION  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
Table 7. 68-pin PLCC Signal Assignments Arranged by Functional Category  
Address & Data  
Name  
Input/Output  
Name  
USB  
Name  
Pin  
2
Pin  
28  
29  
30  
31  
32  
33  
34  
35  
20  
21  
22  
23  
24  
25  
26  
27  
Pin  
42  
54  
55  
57  
58  
45  
46  
48  
49  
53  
59  
60  
64  
20  
A15/P2.7/KSO15  
P1.0/T2/KSO0  
PLLSEL  
DM0  
A14/P2.6/KSO14  
A13/P2.5/KSO13  
A12/P2.4/KSO12  
A11/P2.3/KSO11  
A10/P2.2/KSO10  
A9/P2.1/KSO9  
A8/P2.0/KSO8  
AD7/P0.7/KSI7  
AD6/P0.6/KSI6  
AD5/P0.5/KSI5  
AD4/P0.4/KSI4  
AD3/P0.3/KSI3  
AD2/P0.2/KSI2  
AD1/P0.1/KSI1  
AD0/P0.0/KSI0  
3
P1.1/T2EX/KSO1  
P1.2/KSO2  
4
DP0  
††  
5
P1.3/KSO3  
Reserved/ DM5  
††  
6
P1.4/KSO4  
Reserved/ DP5  
††  
7
P1.5/KSO5  
Reserved/ DM2  
††  
8
P1.6/KSO6  
Reserved/ DP2  
††  
9
P1.7/KSO7  
P3.0/ OVRI#††  
Reserved/ DM3  
††  
10  
11  
12  
13  
14  
15  
16  
17  
Reserved/ DP3  
ECAP  
P3.1/SOF#  
††  
P3.2/INT0#  
Reserved/ DM4  
††  
P3.3/INT1#  
Reserved/ DP4  
FSSEL/UPWEN#††  
OVRI#††  
P3.4/T0/KSO16  
P3.5/T1/KSO17  
P3.6/WR#/KSO18  
P3.7/RD#/KSO19  
Processor Control  
Name  
P3.2/INT0#  
Power & Ground  
Name  
Bus Control & Status  
Pin  
Pin  
Name  
Pin  
22  
VCC  
19,51,  
56,68  
P3.6/WR#/KSO18  
26  
P3.3/INT1#  
RST  
23  
41  
AVCC  
VSS  
40  
P3.7/RD#/KSO19  
PSEN#  
27  
65  
1,18,  
47,50,  
52,63  
XTAL1  
XTAL2  
38  
39  
ALE  
EA#  
66  
67  
Specific to the 8x931AA  
†† Specific to the 8x931HA  
ADVANCE INFORMATION  
9
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
4.0 SIGNALS  
Table 8. Signal Description (Sheet 1 of 3)  
Signal  
Name  
Alternate  
Function  
Type  
Description  
A15:8  
O
Address Lines. Upper byte of external memory address.  
P2.7:0/KS08:15  
P0.7:0/KSI0:7  
AD7:0  
I/O  
Address/Data Lines. Lower byte of external memory address  
multiplexed with data  
ALE  
O
Address Latch Enable. ALE signals the start of an external  
bus cycle and indicates that valid address information is  
available on lines A15:8 and AD7:0. An external latch can use  
ALE to demultiplex the address from the address/data bus.  
AVCC  
PWR Analog VCC. A separate VCC input for the phase-locked loop  
circuitry.  
D
M0, DP0  
I/O  
USB Port 0. Root port. Upstream port to the host PC. DP0 and  
M0 are the differential data plus and data minus signals of USB  
D
port 0. These lines do not have internal pullup resistors. Provide  
an external 1.5 Kpullup resistor at DP0 so the device indicates  
to the host that it is a full-speed device; or provide an external  
1.5 Kpullup resistor at DM0 so the device indicates to the host  
that it is a low-speed device.  
NOTE:  
D
P0 low AND DM0 low signals an SE0 (USB reset),  
causing the 8x931 to stay in reset.  
D
D
D
D
M2, DP2  
M3, DP3  
M4, DP4  
M5, DP5  
I/O  
USB External Downstream Ports 2, 3, 4,5. These pins are the  
differential data plus and data minus lines for the four USB  
external downstream ports. These lines do not have internal  
pulldown resistors. Provide an external 15 Kpulldown resistor  
at each of these pins. See “Design Considerations” on page  
24.  
EA#  
I
External Access. Directs program memory accesses to on-  
chip or off-chip code memory. For EA# strapped to ground, all  
program memory accesses are off-chip. For EA# strapped to  
V
CC, program accesses on-chip ROM if the address is within the  
range of the on-chip ROM; otherwise the access is off-chip. The  
value of EA# is latched at reset. For devices without on-chip  
ROM, EA# must be strapped to ground.  
ECAP  
I
External Capacitor. Connect a 1 µF or larger capacitor  
between this pin and VSS to ensure proper operation of the  
differential line drivers. May be used to supply 3.0v to 3.6v for  
1.5K pullup resistor connected to USB Port 0. See “Design  
Considerations” on page 24.  
FSSEL  
Full Speed Select. Applies to the 8x931AA only. If this pin is  
high, full speed USB data rate is selected (12Mbps). If pin is  
low, low speed USB data rate is selected (1.5 Mbps). Refer to  
Table 11.  
10  
ADVANCE INFORMATION  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
Table 8. Signal Description (Sheet 2 of 3)  
Signal  
Name  
Alternate  
Function  
Type  
Description  
INT1:0#  
I
External Interrupts 0 and 1. These inputs set the IE1:0  
interrupt flags in the TCON register. Bits IT1:0 in TCON select  
the triggering method: edge-triggered (high-to-low) or level  
triggered (active low). INT1:0 also serves as external run  
control for timer1:0 when selected by GATE1:0# in TCON.  
P3.3:2  
KSI7:0  
I
Keyboard Scan Input. Schmitt-trigger inputs with firmware-  
enabled internal pullup resistors used for the input side of the  
keyboard scan matrix.  
AD7:0/P0.7:0  
P3.7/RD#  
KSO19  
O
Keyboard Scan Output. Quasi-bidirectional ports with weak  
KSO18  
internal pullup resistors used for the output side of the keyboard P3.6/WR#  
KSO17:16  
KSO15:8  
KSO7:0  
scan matrix.  
P3.5:4/T1:0  
A15:8/P2.7:0  
P1.7:0  
LED3:0  
O
LED Drivers. Designed to drive LEDs connected directly to  
V
V
CC. The current each driver is capable of sinking is given as  
OL2 in the datasheet.  
OVRI#  
I
Overcurrent Sense. Sense input to indicate an overcurrent  
condition on an external down-stream port. Active low with an  
internal pullup.  
P3.0  
P0.7:0  
P1.7:0  
P2.7:0  
I/O  
I/O  
I/O  
I/O  
Port 0. Eight-bit, open-drain, bidirectional I/O port. Port 0 pins  
have Schmitt trigger inputs.  
AD7:0/KSI7:0  
KSO7:0  
Port 1. Eight-bit quasi-bidirectional I/O port with internal  
pullups.  
Port 2. Eight-bit quasi-bidirectional I/O port with internal  
pullups.  
A15:8/KSO15:8  
P3.0  
P3.1  
P3.2  
P3.3  
P3.4  
P3.5  
P3.6  
P3.7  
Port 3. Eight-bit quasi-bidirectional I/O port with internal  
pullups.  
OVRI#  
SOF#  
INT0#  
INT1#  
T0/KSO16  
T1/KSO17  
WR#/KSO18  
RD#/KSO19  
PLLSEL  
I
Phase-locked Loop Select. For normal operation using the  
8x931HA, connect PLLSEL to logic high. PLLSEL = 0 is used  
for factory test only. (See Table 10). For 8x931AA operation,  
see Table 11.  
PSEN#  
RD#  
O
O
Program Store Enable. Read signal output. Asserted for read  
accesses to external program memory.  
Read. Read signal output. Asserted for read accesses to  
external data memory.  
P3.7/KSO19  
P1.6  
RXD  
I/O  
Receive Serial Data. RXD sends and receives data in serial  
I/O mode 0 and receives data in serial I/O modes 1, 2, and 3.  
ADVANCE INFORMATION  
11  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
Table 8. Signal Description (Sheet 3 of 3)  
Signal  
Name  
Alternate  
Function  
Type  
Description  
RST  
I
Reset. Reset input to the chip. Holding this pin high for two  
machine cycles while the oscillator is running resets the device.  
The port pins are driven to their reset conditions when a voltage  
greater than VIH1 is applied, whether or not the oscillator is  
running. This pin has an internal pulldown resistor which allows  
the device to be reset by connecting a capacitor between this  
pin and VCC  
.
Asserting RST when the chip is in idle mode or powerdown  
mode returns the chip to normal operation.  
SOF#  
O
Start of Frame. Start of frame pulse. Active low. Asserted for 8 P3.1  
states when frame timer is locked to USB frame timing and  
SOF token or artificial SOF is detected.  
T1:0  
T2  
I
Timer 1:0 External Clock Input. When timer 1:0 operates as a P3.5:4/KSO17:16  
counter, a falling edge on the T1:0 pin increments the count.  
I/O  
Timer 2 Clock Input/Output. For the timer 2 capture mode,  
this signal is the external clock input. For the clock-out mode, it  
is the timer 2 clock output.  
P1.0  
T2EX  
TXD  
I
Timer 2 External Input. In timer 2 capture mode, a falling edge P1.1  
initiates a capture of the timer 2 registers. In auto-reload mode,  
a falling edge causes the timer 2 registers to be reloaded. In the  
up-down counter mode, this signal determines the count  
direction: 1 = up, 0 = down.  
O
O
Transmit Serial Data. TXD outputs the shift clock in serial I/O  
P1.7  
mode 0 and transmits serial data in serial I/O modes 1, 2, and  
3.  
UPWEN#  
VCC  
USB Power Enable. A low signal on this pin applies power to  
the external downstream ports.  
PWR Supply Voltage. Connect this pin to the +5v supply voltage.  
Use a 0.1µf decoupling capacitor for each Vcc pin.  
VSS  
GND Circuit Ground. Connect this pin to ground.  
WR#  
XTAL1  
O
I
Write. Write signal output to external memory.  
P3.6/KSO19  
Oscillator Amplifier Input. When implementing the on-chip  
oscillator, connect the external crystal or ceramic resonator  
across XTAL1 and XTAL2. If an external clock source is used,  
connect it to this pin.  
XTAL2  
O
Oscillator Amplifier Output. When implementing the on-chip  
oscillator, connect the external crystal or ceramic resonator  
across XTAL1 and XTAL2. If an external oscillator is used,  
leave XTAL2 unconnected.  
12  
ADVANCE INFORMATION  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
5.0 ELECTRICAL CHARACTERISTICS  
ABSOLUTE MAXIMUM RATINGS†  
NOTICE: This document contains information on  
products in the sampling and initial production  
phases of development. The specifications are  
subject to change without notice.Verify with your  
local Intel sales office that you have the latest  
datasheet before finalizing a design.  
Ambient Temperature Under Bias................... –40°C to +85°C  
Storage Temperature .................................. –65°C to +150°C  
Voltage on Any Pins to VSS .............................–0.5 V to +6.5 V  
IOL per I/O Pin................................................................. 15 mA  
Power Dissipation (1) ..................................................... 1.5 W  
WARNING: Stressing the device beyond the  
“Absolute Maximum Ratings” may cause  
permanent damage. These are stress ratings  
only. Operation beyond the “Operating  
Conditions” is not recommended and extended  
exposure beyond the “Operating Conditions”  
may affect device  
OPERATING CONDITIONS†  
TA (Ambient Temperature Under Bias):  
Commercial........................................................ -0°C to +70°C  
VCC (Digital Supply Voltage) .......................... 4.40 V to 5.25 V  
VSS...................................................................................... 0 V  
AVCC (Analog Supply Voltage) ...................... 4.40 V to 5.25 V  
FOSC ............................................................................. 12 MHz  
reliability.  
NOTE:  
1. Maximum power dissipation is based on package  
heat-transfer limitations, not device power  
consumption.  
Table 9. 8x931AA/8x931HA Supply Voltages  
Parameter  
Condition  
Symbol  
Min  
Max  
Supply Voltage  
8x931HA Vcc/Vbus  
8x931AA Vcc/Vbus  
4.40V  
4.15V†  
5.25V  
5.25V  
For bus-powered device, voltage droop during hot plug may cause the supply voltage to drop  
to 4V worst case. The functionality of the device is supported at this voltage.  
ADVANCE INFORMATION  
13  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
5.1 Operating Frequencies  
Table 10. 8x931HA Operating Frequency  
XTAL1  
Clocks per  
State  
(TOSC/state)  
(3)  
Internal  
Frequency  
XTAL1  
Frequency  
USB Rate  
(1)  
PLLSEL  
Comments  
(FCLK  
)
(FOSC  
)
(2)  
0 (4)  
2
1
12 MHz  
12 Mbps  
6 MHz (3)  
PLL On  
(Full Speed)  
NOTES:  
1. The sampling rate is 4 times the USB rate.  
2. The internal frequency, FCLK = 1/TCLK, is the clock signal distributed to the CPU and the  
on-chip peripherals,  
3. Following device reset, the CPU and on-chip peripherals operate in low-clock mode  
(FCLK = 3 MHz) until the LC bit in the PCON register is cleared. In low clock mode,  
there are four TOSC periods per state. Low-clock mode does not affect the USB rate.  
4. PLLSEL = 0 is used during factory test only.  
.
Table 11. 8x931AA Operating Frequencies  
Core  
XTAL1  
Frequency  
(MHz)  
USB Rate  
(FS/LS)  
(2)  
PLLSEL FSSEL  
LC Bit  
(1)  
Frequency  
FCLK  
(Mhz)  
Comment  
Pin  
Pin  
0
0
0
0
0
1
1
0
1
0
1
0
1
6
LS  
LS  
LS  
LS  
FS  
FS  
3
3
6
3
6
3
PLL Off  
PLL Off  
PLL Off  
PLL Off  
PLL On  
PLL On  
0
6
1
12  
12  
12  
12  
1
1
1
NOTES:  
1. Reset and power up routines set the LC bit in PCON to put the 8x931AA in low-clock mode (core  
frequency = 3 MHz) for lower ICC prior to device enumeration. Following completion of device  
enumeration, firmware should clear the LC bit to exit the low-clock mode. The user may switch the  
core frequency back and forth at any time, as needed.  
2. USB rates: Low speed = 1.5 Mbps; Full speed = 12 Mbps. The USB sample rate is 4X the USB rate.  
14  
ADVANCE INFORMATION  
 
 
 
 
 
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
5.2 DC Characteristics  
Table 12. DC Characteristics at Operating Conditions  
Typical  
(1)  
Symbol  
Parameter  
Min  
Max  
Units  
Test Conditions  
VIL  
Input Low Voltage  
(except EA#)  
–0.5  
0.2 VCC – 0.1  
V
VIL1  
VIH  
Input Low Voltage  
(EA#)  
0
0.2 VCC – 0.3  
VCC + 0.5  
V
V
V
V
Input High Voltage  
(except XTAL1, RST)  
0.2 VCC + 0.9  
0.7 VCC  
VIH1  
VOL  
Input High Voltage  
(XTAL1, RST)  
VCC + 0.5  
Output Low Voltage  
(port 1, 2, 3)  
(2)  
0.3  
0.45  
1.0  
I
I
OL = 100 µA  
OL = 1.6 mA  
IOL = 3.5 mA  
VOL1  
Output Low Voltage  
(port 0, ALE, PSEN#,  
SOF#)  
0.3  
0.45  
1.0  
V
I
I
OL = 200 µA  
OL = 3.2 mA  
IOL = 7.0 mA  
(2)  
VOL2  
Output Low Voltage  
(LED 0, 1, 2, 3)  
2.0  
3.0  
V
V
IOL = 6 mA  
IOL = 22 mA  
VOH  
Output High Voltage  
(port 1, 2, 3, ALE,  
PSEN#, SOF#)  
(3)  
V
CC – 0.3  
IOH = –10 µA  
IOH = –30 µA  
VCC – 0.7  
V
CC – 1.5  
IOH = –60 µA  
VOH1  
Output High Voltage  
(port 0 in external  
address space)  
(3)  
V
V
CC – 0.3  
CC – 0.7  
V
IOH = –200 µA  
OH = –3.2 mA  
IOH = –7.0 mA  
I
VCC – 1.5  
IIL  
Logical 0 Input  
Current  
(port 1,2,3)  
–50  
µA  
µA  
VIN = 0.45 V  
ILI  
Input Leakage Current  
(port 0)  
±10  
VIN = VIL or VIH  
NOTE:  
1. Typical values are obtained using VCC = 5.0V, TA = 25°C and are not guaranteed.  
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level  
outputs of ALE and ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the  
port 0 and port 2 pins when these pins change from 1 to 0. In applications where capacitive loading  
exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify  
ALE or other signals with a Schmitt trigger or CMOS-level input logic.  
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN to drop below the VCC  
specification when the address lines are stabilizing.  
ADVANCE INFORMATION  
15  
 
 
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
Table 12. DC Characteristics at Operating Conditions (Continued)  
Typical  
(1)  
Symbol  
Parameter  
Logical 1-to-0  
Min  
Max  
Units  
Test Conditions  
ITL  
–650  
µA  
V
IN = 2.0 V  
Transition Current  
(Port 1, 2,3)  
RRST  
CIO  
RST Pulldown  
Resistor  
40  
100  
KΩ  
Pin Capacitance  
10  
pF  
FOSC = 12 MHz  
TA = 25°C  
IPD  
Powerdown Current  
USB suspend  
µA  
145  
175  
IDL  
Idle Mode ICC  
40  
30  
70  
mA  
FCLK =6 MHz  
FCLK =3 MHz  
ICC  
Active ICC  
mA  
FCLK = 6 MHz  
50  
25  
FCLK = 3MHz  
UZDRV  
USB Drivers Output  
10  
KΩ  
NOTE:  
1. Typical values are obtained using VCC = 5.0V, TA = 25°C and are not guaranteed.  
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level  
outputs of ALE and ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the  
port 0 and port 2 pins when these pins change from 1 to 0. In applications where capacitive loading  
exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify  
ALE or other signals with a Schmitt trigger or CMOS-level input logic.  
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN to drop below the VCC  
specification when the address lines are stabilizing.  
16  
ADVANCE INFORMATION  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
5.3 Explanation of Timing Symbols  
Table 13 defines the timing symbols used in Tables 14 through 16 and the associated timing diagrams. They  
have the form TXXYY, where the character pairs represent a signal and its condition. Timing symbols represent  
the time between two signal / condition points.  
Table 13. AC Timing Symbol Definitions  
Symbol  
Definition  
A
C
D
L
Address: A15:8, A7:0  
External Clock (XTAL1)  
Data In: D7:0  
ALE: Address Latch Enable  
Program Store Enable (PSEN#)  
Data Out: D7:0  
P
Q
R
W
Read: RD#  
Write: WR#  
Character  
Condition  
H
L
High  
Low  
V
X
Z
Valid, Setup  
No Longer Valid, Hold  
Floating (low impedance)  
ADVANCE INFORMATION  
17  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
5.4 System Bus AC Characteristics  
Test Conditions: FOSC = 12 MHz. Rise and fall times = 10 ns. Capacitive loading on ALE, PSEN#, and port P0  
= 100 pF. Capacitive loading on all other outputs = 80 pF.  
Table 14. External Bus Characteristics  
Symbol  
Parameter  
F
OSC = 12 MHz,  
Variable FCLK  
Units  
FCLK = 6 MHz  
Min Max  
Min  
Max  
FOSC  
XTAL1 Frequency  
12 ± 0.25%  
MHz  
ns  
TCLK  
1/FCLK = 1/CPU Fre-  
quency  
166.67 (Typical)  
TLHLL  
TAVLL  
TLLAX  
ALE Pulse Width  
127  
43  
TCLK – 40  
0.5TCLK – 40  
0.5TCLK – 30  
ns  
ns  
ns  
Address Valid to ALE Low  
Address Hold after ALE  
Low  
53  
TPLAZ  
TLLIV  
PSEN# Low to Address  
Float  
10  
10  
ns  
ns  
ALE Low to Instruction In  
Valid  
259  
2TCLK – 75  
TLLPL  
TPLPH  
TPLIV  
ALE Low to PSEN# Low  
PSEN# Pulse Width  
53  
205  
77  
0.5TCLK – 30  
1.5TCLK – 45  
ns  
ns  
ns  
PSEN# Low to Instruction  
In Valid  
TCLK – 90  
TPHIX  
TPHIZ  
Instruction Hold after  
PSEN# High  
0
0
ns  
ns  
ns  
ns  
Instruction Float after  
PSEN# High  
63  
312  
0.5TCLK – 20  
2.5TCLK – 105  
1.5TCLK + 50  
TAVIV  
Address Valid to Instruc-  
tion Valid  
T
LLRL, TLLWL  
ALE Low to RD# or WR#  
Low  
200  
400  
300  
1.5TCLK – 50  
3TCLK – 100  
TRLRH,  
TWLWH  
RD# and WR# Pulse  
Width  
ns  
TLLDV  
TRLDV  
TRLAZ  
TRHDX  
TRHDz  
ALE Low to Data In Valid  
RD# Low to Data In Valid  
RD# Low to Address Float  
Data Hold After RD# High  
Data Float After RD# High  
578  
322  
0
4TCLK – 90  
2.5TCLK – 95  
0
ns  
ns  
ns  
ns  
ns  
ns  
0
0
23  
0.5TCLK – 60  
T
AVRL, TAVWL  
Address Valid to RD# or  
WR# Low  
244  
2TCLK – 90  
18  
ADVANCE INFORMATION  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
Table 14. External Bus Characteristics (Continued)  
Symbol  
Parameter  
FOSC = 12 MHz,  
CLK = 6 MHz  
Variable FCLK  
Units  
ns  
F
Min Max  
Min  
Max  
TAVDV  
Address Valid to Data In  
Valid  
661  
4.5TCLK – 90  
T
RHLH, TWHLH RD# or WR# High to ALE  
High  
43  
48  
123  
0.5TCLK – 40  
0.5TCLK – 35  
0.5TCLK + 40  
ns  
ns  
TQVWX  
Data Valid to WR# Transi-  
tion  
TQVWH  
TWHQX  
Data Valid to WR# High  
Data Hold After WR# High  
514  
43  
3.5TCLK – 70  
0.5TCLK – 40  
ns  
ns  
5.4.1 System Bus Timing Diagrams  
TLHLL  
ALE  
TLLIV  
TLLPL  
TAVLL  
TPLPH  
TPLIV  
TPLAZ  
PSEN#  
TPHIZ  
TLLAX  
A7:0  
TAVIV  
TPHIX  
Port 0  
Port 2  
INSTR IN  
A7:0  
A15:8  
A15:8  
A5280-02  
Figure 6. 8x931AA/HA External Program Memory Read  
ADVANCE INFORMATION  
19  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
ALE  
TLHLL  
TRHLH  
PSEN#  
TLLDV  
TLLRL  
TRLRH  
RD#  
Port 0  
Port 2  
TAVLL  
TLLAX  
TRLDV  
TRLAZ  
TRHDZ  
TRHDX  
A7:0 from PCL  
A7:0 from RI or DPL  
Data In  
Inst. In  
TAVRL  
TAVDV  
P2.7:0 or A15:8 from DPH  
A15:8 from PCH  
A5275-02  
Figure 7. 8x931AA/HA External Data Memory Read  
ALE  
TLHLL  
TWHLH  
PSEN#  
WR#  
TLLWL  
TWLWH  
TAVLL  
TLLAX  
TQVWX  
TWHQX  
TQVWH  
Data Out  
Port 0  
Port 2  
A7:0 from RI or DPL  
TAVWL  
A7:0 from PCL  
Inst. In  
P2.7:0 or A15:8 from DPH  
A15:8 from PCH  
A5276-01  
Figure 8. 8x931AA/HA External Data Memory Write  
20  
ADVANCE INFORMATION  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
5.5 AC Characteristics — Synchronous Mode 0  
T
XLXL  
TXD  
T
XHQX  
Set TI  
T
QVXH  
1
RXD  
(Out)  
0
2
7
4
6
3
5
T
T
XHDV  
XHDX  
Set RI  
RXD  
(In)  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.  
A2592-02  
Figure 9. Serial Port Waveform — Synchronous Mode 0  
Table 15. Serial Port Timing — Synchronous Mode 0  
Symbol  
TXLXL  
Parameter  
Min  
12 TOSC  
Max  
Units  
ns  
Serial Port Clock Cycle Time  
TQVXH  
TXHQX  
TXHDX  
TXHDV  
Output Data Setup to Clock Rising Edge  
Output Data Hold after Clock Rising Edge  
Input Data Hold after Clock Rising Edge  
Clock Rising Edge to Input Data Valid  
10 TOSC – 133  
2 TOSC – 50  
0
ns  
ns  
ns  
10 TOSC – 133  
ns  
ADVANCE INFORMATION  
21  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
5.6 External Clock Drive  
TCLCH  
TCHCX  
VCC – 0.5  
0.7 VCC  
TCLCX  
0.2 VCC – 0.1  
0.45 V  
TCHCL  
TCLCL  
A4119-01  
Figure 10. External Clock Drive Waveforms  
Table 16. External Clock Drive  
Symbol  
1/TOSC  
TCHCX  
TCLCX  
Parameter  
Oscillator Frequency (FOSC  
High Time  
Min  
6
Max  
Units  
MHz  
ns  
)
12  
20  
20  
Low Time  
ns  
TCLCH  
Rise Time  
20  
20  
ns  
TCHCL  
Fall Time  
ns  
22  
ADVANCE INFORMATION  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
5.7 Testing Waveforms  
Outputs  
Inputs  
VCC – 0.5  
0.45 V  
0.2 VCC + 0.9  
0.2 VCC – 0.1  
VIH MIN  
VOL MAX  
AC inputs during testing are driven at VCC – 0.5V for a logic 1  
and 0.45 V for a logic 0. Timing measurements are made at  
a min of VIH for a logic 1 and VOL for a logic 0.  
A4118-01  
Figure 11. AC Testing Input, Output Waveforms  
VLOAD + 0.1 V  
VLOAD  
VOH – 0.1 V  
Timing Reference  
Points  
VOL + 0.1 V  
VLOAD – 0.1 V  
For timing purposes, a port pin is no longer floating when a  
100 mV change from load voltage occurs and begins to float  
when a 100 mV change from the loading VOH/VOL level occurs  
with IOL/IOH = ± 20 mA.  
A4117-01  
Figure 12. Float Waveforms  
ADVANCE INFORMATION  
23  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
condition can be seen on the oscilloscopes as  
excessive overshoot and undershoot. This condition  
can potentially introduce bit errors.  
6.0 THERMAL CHARACTERISTICS  
The microcontroller operates over the commercial  
temperature range from 0oC to 70oC. All thermal  
impedance data (see Table 17) is approximate for  
static air conditions at 1 watt of power dissipation.  
Values change depending on operating conditions  
and application requirements. The Intel Packaging  
Handbook (order number 240800) describes Intel’s  
thermal impedance test methodology. The  
Components Quality and Reliability Handbook  
(order number 210997) provides quality and  
reliability information.  
7.4 Pullup Resistor Requirement  
for 8x931AA/HA devices  
The USB specification requires a pullup resistor to  
allow the host to identify which devices are low  
speed and which are full speed in order to commu-  
nicate at the appropriate data rate. For 8x931HA  
hub devices (12 Mbps), use a 1.5Kpullup resistor  
(to 3.0 V – 3.6 V; may use the ECAP pin.) on the  
DP0 line. 8x931AA devices can be either full speed  
or low speed; add a 1.5Kpullup to the appropriate  
USB line.  
Table 17. Thermal Characteristics  
Package Type  
θJA  
N/A  
θJC  
N/A  
68-pin PLCC  
Data unavailable at time of publication.  
7.5 Powerdown Mode Cannot Be  
Invoked Before USB Suspend  
7.0 DESIGN CONSIDERATIONS  
7.1 Low Clock Mode Frequency  
If the 8x931AA/HA is put into powerdown mode  
before receiving a USB suspend signal from the  
host, then a USB resume will not properly wake up  
the 8x931AA/HA from powerdown mode.  
During low clock mode, the internal clock FCLK  
distributed to the CPU and peripherals is 3 MHz.  
Peripheral timing and external bus accesses  
(including instruction fetch and data read/write) are  
affected. Refer to Table 10 and Table 11 for clock  
rates.  
7.6 Unused Downstream Ports  
If the USB downstream ports are not used, it is still  
required that the two data lines be pulled low  
externally (similar to a disconnect) so that the inputs  
are not floating. This will eliminate the possibility of  
induced system noise. All USB data lines require  
15Kexternal pulldown resistors. Do not leave  
unused port(s) disconnected.  
7.2 Setting RXFFRC Bit Clears Only  
the Oldest Packet in the FIFO  
If the receive FIFO is set as a dual packet mode,  
then it can receive two packets. Setting RXFFRC (in  
RXCON registers) to indicate FIFO Read Complete  
will not flush the entire FIFO; it will flush only the  
oldest packet. The read marker will be advanced to  
the location of the read pointer.  
7.7 ECAP Usage to Supply 3.0 to 3.6  
Volts for 1.5K Ohm Pullup  
For a self-powered or bus-powered device, when  
the voltage at the VCC pins are at 5.25v, the voltage  
at ECAP pin will be at approximately 3.6v. If the VCC  
pin is at 4.65v [Min, Vbus Powered (host or hub)  
Port specification], the voltage at the ECAP pin will  
be at approximately 3.2v (refer to Table 18 below).  
The capability for this pin to supply the 3.0v to 3.6v  
voltage to the 1.5KUSB pullup terminator  
depends upon the VCC voltage level.  
7.3 Series Resistor Requirement for  
Impedance Matching  
Per USB rev. 1.0 specification (page 111, section  
7.1.1.1), the impedance of the differential driver  
must be between 29and 44. To match the cable  
impedance, a series resistor of 27to 33should  
be connected to each USB line; i.e., on DP0 and on  
D
M0. If the USB line is improperly terminated or not  
matched, then signal fidelity will suffer. This  
24  
ADVANCE INFORMATION  
8x931AA, 8x931HA USB PERIPHERAL CONTROLLER  
For a bus-powered device that is connected to a  
8.0 8x931AA/HA ERRATA  
bus-powered hub, when the voltage at the Vcc pins  
(in the bus-powered devices) are at 4.28v, the  
voltage at ECAP pin will be at approximately 3.0v. If  
the Vcc voltage drops below 4.28v, the ECAP pin  
can not supply voltage above 3.0 v for the 1.5KΩ  
USB pullup terminator.  
The 8x931AA/HA may contain design defects or  
errors known as errata. Characterized errata that  
may cause the 8x931AA/HA’s operational behavior  
to deviate from published specifications are  
documented in a specification update. Specification  
updates can be obtained from your local Intel sales  
office  
(www.intel.com).  
or  
from  
the  
World  
Wide  
Web  
NOTE: The typical ECAP values, listed in the table  
below, reflect a 1 µF capacitor connection between  
the ECAP pin and ground.  
Table 18. Vcc and Typical ECAP Voltages  
9.0 DATASHEET REVISION HISTORY  
VCC  
ECAP Pin  
3.6v  
Datasheets are changed as new device information  
becomes available. Verify with your local Intel sales  
office that you have the latest version before  
finalizing a design or ordering devices.  
5.25v  
5.00v  
4.65v  
4.40v  
4.28v  
3.5v  
3.2v  
3.1v  
This is the original version of the datasheet.  
3.0v  
ADVANCE INFORMATION  
25  
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