8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
7.0 THERMAL CHARACTERISTICS
8.3 Setting RXFFRC Bit Clears Only
the Oldest Packet in the FIFO
The microcontroller operates over the commercial
temperature range from 0oC to 70oC. All thermal
impedance data (see Table 20) is approximate for
static air conditions at 1 watt of power dissipation.
Values change depending on operating conditions
and application requirements. The Intel Packaging
Handbook (order number 240800) describes Intel’s
thermal impedance test methodology. The
Components Quality and Reliability Handbook
(order number 210997) provides quality and
reliability information.
If the receive FIFO is set as a dual packet mode,
then it can receive two packets. Setting RXFFRC (in
RXCON registers) to indicate FIFO Read Complete
will not flush the entire FIFO; it will flush only the
oldest packet. The read marker will be advanced to
the location of the read pointer.
8.4 Series Resistor Requirement for
Impedance Matching
Table 20. Thermal Characteristics
Per USB rev. 1.0 specification (page 111, section
7.1.1.1), the impedance of the differential driver
must be between 29Ω and 44Ω. To match the cable
impedance, a series resistor of 27Ω to 33Ω should
be connected to each USB line; i.e., on DP0 (pin 55)
and on DM0 (pin 54). If the USB line is improperly
terminated or not matched, then signal fidelity will
suffer. This condition can be seen on the oscillo-
scopes as excessive overshoot and undershoot.
This condition can potentially introduce bit errors.
Package Type
θJA
θJC
68-pin PLCC
N/A
N/A
8.0 DESIGN CONSIDERATIONS
8.1 External Bus Timing and
Peripheral Timing Affected by
PLLSEL2:0 Selection
PLLSEL2 (pin 43), PLLSEL1 (pin 42), and PLLSEL0
(pin 44) determine the 8x930Hx internal CPU
operating frequency. See Table 13. Operate the
8x930Hx at full speed by setting PLLSEL2:0 to 110.
8.5 Pullup Resistor Requirement
for 8x930Hx Hub devices
The USB specification requires a pullup resistor to
allow the host to identify which devices are low
speed and which are full speed in order to commu-
nicate at the appropriate data rate. For 8x930Hx
hub devices (12 Mbps), use a 1.5KΩ pullup resistor
(to 3.0 V – 3.6 V) on the DP0 line.
This provides an internal clock frequency of 12 MHz
(FCLK = FOSC) and sets the microcontroller state time
equal to one oscillator period (TOSC).
The CPU operating frequency influences the timing
of all on-chip peripherals. Refer to the 8X930Ax,
8X930Hx Universal Serial Bus Microcontroller
User’s Manual for peripheral timing formulas (refer
to Table 1 on page 1 for ordering information).
8.6 Powerdown Mode Cannot Be
Invoked Before USB Suspend
If the 8x930Hx is put into powerdown mode before
receiving a USB suspend signal from the host, then
8.2 Low Clock Mode Frequency
a
USB resume will not properly wake up the
8x930Hx from powerdown model.
The internal clock FCLK distributed to the CPU and
peripherals is 3 MHz. Peripheral timing and external
bus accesses (including instruction fetch and data
read/write) are affected. Refer to Table 13 for clock
rates.
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ADVANCE INFORMATION
