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CYWUSB6935

WirelessUSB LR™ 2.4-GHz DSSS Radio SoC

1.0

Features

2.0

Functional Description

• 2.4-GHz radio transceiver

The CYWUSB6935 transceiver is a single-chip 2.4-GHz Direct

Sequence Spread Spectrum (DSSS) Gaussian Frequency

Shift Keying (GFSK) baseband modem radio that connects

directly to a microcontroller via a simple serial peripheral

interface.

The CYWUSB6935 is offered in an industrial temperature

range 48-pin QFN and a commercial temperature range 48-

pin QFN.

• Operates in the unlicensed Industrial, Scientific, and

Medical (ISM) band (2.4 GHz–2.483 GHz)

• –95-dBm receive sensitivity

• Up to 0dBm output power

• Range of up to 50 meters or more

• Data throughput of up to 62.5 kbits/sec

• Highly integrated low cost, minimal number of external

3.0

Applications

components required

• Building/Home Automation

— Climate Control

— Lighting Control

— Smart Appliances

— On-Site Paging Systems

— Alarm and Security

• Industrial Control

— Inventory Management

• Dual DSSS reconfigurable baseband correlators

• SPI microcontroller interface (up to 2-MHz data rate)

• 13-MHz input clock operation

• Low standby current < 1 µA

• Integrated 30-bit Manufacturing ID

• Operating voltage from 2.7V to 3.6V

• Operating temperature from –40° to 85°C

• Offered in a small footprint 48 QFN

— Factory Automation

— Data Acquisition

• Automatic Meter Reading (AMR)

• Transportation

— Diagnostics

— Remote Keyless Entry

• Consumer / PC

—Locator Alarms

— Presenter Tools

— Remote Controls

— Toys

DIOVAL

DIO

GFSK

DSSS

RFOUT

RFIN

SERDES

Modulator

IRQ

Baseband

A

SS

SCK

DSSS

Baseband

B

Digital

MISO

MOSI

SERDES

B

GFSK

Demodulator

RESET

PD

Synthesizer

Figure 3-1. CYWUSB6935 Simplified Block Diagram

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-16008 Rev. *C

Revised March 17, 2005

CYWUSB6935

3.1

Applications Support

4.2

GFSK Modem

The CYWUSB6935 is supported by both the CY3632

WirelessUSB Development Kit and the CY3635 WirelessUSB

N:1 Development Kit. The CY3635 development kit provides

all of the materials and documents needed to cut the cord on

multipoint to point and point-to-point low bandwidth, high node

density applications including four small form-factor sensor

boards and a hub board that connects to WirelessUSB LR RF

module boards, a software application that graphically demon-

strates the multipoint to point protocol, comprehensive

WirelessUSB protocol code examples and all of the

associated schematics, gerber files and bill of materials. The

WirelessUSB N:1 Development Kit is also supported by the

WirelessUSB Listener Tool.

The transmitter uses a DSP-based vector modulator to

convert the 1-MHz chips to an accurate GFSK carrier.

The receiver uses a fully integrated Frequency Modulator (FM)

detector with automatic data slicer to demodulate the GFSK

signal.

4.3

Dual DSSS Baseband

Data is converted to DSSS chips by a digital spreader. De-

spreading is performed by an oversampled correlator. The

DSSS baseband cancels spurious noise and assembles

properly correlated data bytes.

The DSSS baseband has three operating modes: 64-chips/bit

Single Channel, 32-chips/bit Single Channel, and 32-chips/bit

Single Channel Dual Data Rate (DDR).

4.0

Functional Overview

The CYWUSB6935 provides a complete SPI-to-antenna radio

modem. The CYWUSB6935 is designed to implement

wireless devices operating in the worldwide 2.4-GHz Indus-

trial, Scientific, and Medical (ISM) frequency band

(2.400 GHz–2.4835 GHz). It is intended for systems compliant

with world-wide regulations covered by ETSI EN 301 489-1

V1.4.1, ETSI EN 300 328-1 V1.3.1 (European Countries);

FCC CFR 47 Part 15 (USA and Industry Canada) and ARIB

STD-T66 (Japan).

4.3.1

64 Chips/Bit Single Channel

The baseband supports a single data stream operating at

15.625 kbits/sec. The advantage of selecting this mode is its

ability to tolerate a noisy environment. This is because the

15.625 kbits/sec data stream utilizes the longest PN Code

resulting in the highest probability for recovering packets over

the air. This mode can also be selected for systems requiring

data transmissions over longer ranges.

The CYWUSB6935 contains a 2.4-GHz radio transceiver, a

GFSK modem, and a dual DSSS reconfigurable baseband.

The radio and baseband are both code- and frequency-agile.

Forty-nine spreading codes selected for optimal performance

(Gold codes) are supported across 78 1-MHz channels

yielding a theoretical spectral capacity of 3822 channels. The

CYWUSB6935 supports a range of up to 50 meters or more.

4.3.2

32 Chips/Bit Single Channel

The baseband supports a single data stream operating at

31.25 kbits/sec.

4.3.3

32 Chips/Bit Single Channel Dual Data Rate (DDR)

The baseband spreads bits in pairs and supports a single data

stream operating at 62.5 kbits/sec.

4.1

2.4-GHz Radio

The receiver and transmitter are a single-conversion, low-

Intermediate Frequency (low-IF) architecture with fully

integrated IF channel matched filters to achieve high perfor-

mance in the presence of interference. An integrated Power

Amplifier (PA) provides an output power control range of 30 dB

in seven steps.

4.4

Serializer/Deserializer (SERDES)

data Serializer/Deserializer

CYWUSB6935 provides

a

(SERDES), which provides byte-level framing of transmit and

receive data. Bytes for transmission are loaded into the

SERDES and receive bytes are read from the SERDES via the

SPI interface. The SERDES provides double buffering of

transmit and receive data. While one byte is being transmitted

by the radio the next byte can be written to the SERDES data

register insuring there are no breaks in transmitted data.

After a receive byte has been received it is loaded into the

SERDES data register and can be read at any time until the

next byte is received, at which time the old contents of the

SERDES data register will be overwritten.

Table 4-1. Internal PA Output Power Step Table

PA Setting

Typical Output Power (dBm)

7

6

5

4

3

2

1

0

–2.4

–5.6

–9.7

–16.4

–20.8

–24.8

–29.0

4.5

Application Interfaces

CYWUSB6935 has a fully synchronous SPI slave interface for

connectivity to the application MCU. Configuration and byte-

oriented data transfer can be performed over this interface. An

interrupt is provided to trigger real time events.

An optional SERDES Bypass mode (DIO) is provided for appli-

cations that require a synchronous serial bit-oriented data

path. This interface is for data only.

Both the receiver and transmitter integrated Voltage

Controlled Oscillator (VCO) and synthesizer have the agility to

cover the complete 2.4-GHz GFSK radio transmitter ISM

band. The synthesizer provides the frequency-hopping local

oscillator for the transmitter and receiver. The VCO loop filter

is also integrated on-chip.

Document #: 38-16008 Rev. *C

Page 2 of 33

CYWUSB6935

4.6

Clocking and Power Management

5.0

5.1

Application Interfaces

SPI Interface

A 13-MHz crystal is directly connected to X13IN and X13

without the need for external capacitors. The CYWUSB6935

has a programmable trim capability for adjusting the on-chip

load capacitance supplied to the crystal. The Radio Frequency

(RF) circuitry has on-chip decoupling capacitors. The

CYWUSB6935 is powered from a 2.7V to 3.6V DC supply. The

CYWUSB6935 can be shutdown to a fully static state using the

PD pin.

The CYWUSB6935 has a four-wire SPI communication

interface between an application MCU and one or more slave

devices. The SPI interface supports single-byte and multi-byte

serial transfers. The four-wire SPI communications interface

consists of Master Out-Slave In (MOSI), Master In-Slave Out

(MISO), Serial Clock (SCK), and Slave Select (SS).

The SPI receives SCK from an application MCU on the SCK

pin. Data from the application MCU is shifted in on the MOSI

pin. Data to the application MCU is shifted out on the MISO

pin. The active-low Slave Select (SS) pin must be asserted to

initiate a SPI transfer.

The application MCU can initiate a SPI data transfer via a

multi-byte transaction. The first byte is the Command/Address

byte, and the following bytes are the data bytes as shown in

Figure 5-1 through Figure 5-4. The SS signal should not be

deasserted between bytes. The SPI communications interface

is as follows:

Below are the requirements for the crystal to be directly

connected to X13IN and X13:

• Nominal Frequency: 13 MHz

• Operating Mode: Fundamental Mode

• Resonance Mode: Parallel Resonant

• Frequency Stability: ± 30 ppm

• Series Resistance: ≤ 100 ohms

• Load Capacitance: 10 pF

• Drive Level: 10 µW–100 µW

• Command Direction (bit 7) = “0” Enables SPI read transac-

4.7

Receive Signal Strength Indicator (RSSI)

tion. A “1” enables SPI write transactions.

The RSSI register (Reg 0x22) returns the relative signal

• Command Increment (bit 6) = “1” Enables SPI auto address

increment. When set, the address field automatically incre-

ments at the end of each data byte in a burst access, oth-

erwise the same address is accessed.

• Six bits of address.

• Eight bits of data.

The SPI communications interface has a burst mechanism,

where the command byte can be followed by as many data

bytes as desired. A burst transaction is terminated by

deasserting the slave select (SS = 1). For burst read transac-

tions, the application MCU must abide by the timing shown in

Figure 12-2.

The SPI communications interface single read and burst read

sequences are shown in Figure 5-2 and Figure 5-3, respec-

tively.

strength of the ON-channel signal power and can be used to:

1. Determine the connection quality

2. Determine the value of the noise floor

3. Check for a quiet channel before transmitting.

The internal RSSI voltage is sampled through a 5-bit analog-

to-digital converter (ADC). A state machine controls the

conversion process. Under normal conditions, the RSSI state

machine initiates a conversion when an ON-channel carrier is

detected and remains above the noise floor for over 50 µs. The

conversion produces a 5-bit value in the RSSI register (Reg

0x22, bits 4:0) along with a valid bit, RSSI register (Reg 0x22,

bit 5). The state machine then remains in HALT mode and

does not reset for a new conversion until the receive mode is

toggled off and on. Once a connection has been established,

the RSSI register can be read to determine the relative

connection quality of the channel. A RSSI register value lower

than 10 indicates that the received signal strength is low, a

value greater than 28 indicates a strong signal level.

The SPI communications interface single write and burst write

sequences are shown in Figure 5-4 and Figure 5-5, respec-

tively.

To check for a quiet channel before transmitting, first set up

receive mode properly and read the RSSI register (Reg 0x22).

If the valid bit is zero, then force the Carrier Detect register

(Reg 0x2F, bit 7=1) to initiate an ADC conversion. Then, wait

greater than 50 µs and read the RSSI register again. Next,

clear the Carrier Detect Register (Reg 0x2F, bit 7=0) and turn

the receiver OFF. Measuring the noise floor of a quiet channel

is inherently a 'noisy' process so, for best results, this

procedure should be repeated several times (~20) to compute

an average noise floor level. A RSSI register value of 0-10

indicates a channel that is relatively quiet. A RSSI register

value greater than 10 indicates the channel is probably being

used. A RSSI register value greater than 28 indicates the

presence of a strong signal.

Document #: 38-16008 Rev. *C

Page 3 of 33

CYWUSB6935

Byte 1

Byte 1+N

[7:0]

Bit #

7

6

[5:0]

Bit Name

DIR

INC

Address

Data

Figure 5-1. SPI Transaction Format

S C K

S S

c m d

a d d r

IN C

^D0^IR

0

M O S I

M IS O

A 5

A 4

A 3

A 2

A 1

A 0

d a ta to m c u

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

Figure 5-2. SPI Single Read Sequence

S C K

S S

cm d

addr

IN C

^D0^IR

1

A 5

A 4

A 3

A 2

A 1

A 0

M O S I

M IS O

data to m cu

1+N

1

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

Figure 5-3. SPI Burst Read Sequence

SCK

SS

cmd

addr

data from mcu

INC

^D1^IR

0

MOSI

MISO

D0

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

Figure 5-4. SPI Single Write Sequence

SCK

SS

cmd

addr

data from mcu

1+N

1

INC

^D1^IR

1

MOSI

MISO

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

A5

A4

A3

A2

A1

A0

Figure 5-5. SPI Burst Write Sequence

Document #: 38-16008 Rev. *C

Page 4 of 33

CYWUSB6935

5.3.1

Wake Interrupt

5.2

DIO Interface

When the PD pin is low, the oscillator is stopped. After PD is

deasserted, the oscillator takes time to start, and until it has

done so, it is not safe to use the SPI interface. The wake

interrupt indicates that the oscillator has started, and that the

device is ready to receive SPI transfers.

The wake interrupt is enabled by setting bit 0 of the Wake

Enable register (Reg 0x1C, bit 0=1). Whether or not a wake

interrupt is pending is indicated by the state of bit 0 of the Wake

Status register (Reg 0x1D, bit 0). Reading the Wake Status

register (Reg 0x1D) clears the interrupt.

The DIO communications interface is an optional SERDES

bypass data-only transfer interface. In receive mode, DIO and

DIOVAL are valid after the falling edge of IRQ, which clocks

the data as shown in Figure 5-6. In transmit mode, DIO and

DIOVAL are sampled on the falling edge of the IRQ, which

clocks the data as shown in Figure 5-7. The application MCU

samples the DIO and DIOVAL on the rising edge of IRQ.

5.3

Interrupts

The CYWUSB6935 features three sets of interrupts: transmit,

received, and a wake interrupt. These interrupts all share a

single pin (IRQ), but can be independently enabled/disabled.

In transmit mode, all receive interrupts are automatically

disabled, and in receive mode all transmit interrupts are

automatically disabled. However, the contents of the enable

registers are preserved when switching between transmit and

receive modes.

Interrupts are enabled and the status read through 6 registers:

Receive Interrupt Enable (Reg 0x07), Receive Interrupt Status

(Reg 0x08), Transmit Interrupt Enable (Reg 0x0D), Transmit

Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake

Status (Reg 0x1D).

If more than 1 interrupt is enabled at any time, it is necessary

to read the relevant interrupt status register to determine which

event caused the IRQ pin to assert. Even when a given

interrupt source is disabled, the status of the condition that

would otherwise cause an interrupt can be determined by

reading the appropriate interrupt status register. It is therefore

possible to use the devices without making use of the IRQ pin

at all. Firmware can poll the interrupt status register(s) to wait

for an event, rather than using the IRQ pin.

The polarity of all interrupts can be set by writing to the Config-

uration register (Reg 0x05), and it is possible to configure the

IRQ pin to be open drain (if active low) or open source (if active

high).

5.3.2

Transmit Interrupts

Four interrupts are provided to flag the occurrence of transmit

events. The interrupts are enabled by writing to the Transmit

Interrupt Enable register (Reg 0x0D), and their status may be

determined by reading the Transmit Interrupt Status register

(Reg 0x0E). If more than 1 interrupt is enabled, it is necessary

to read the Transmit Interrupt Status register (Reg 0x0E) to

determine which event caused the IRQ pin to assert.

The function and operation of these interrupts are described in

detail in Section 7.0.

5.3.3

Receive Interrupts

Eight interrupts are provided to flag the occurrence of receive

events, four each for SERDES A and B. In 64 chips/bit and 32

chips/bit DDR modes, only the SERDES A interrupts are

available, and the SERDES B interrupts will never trigger,

even if enabled. The interrupts are enabled by writing to the

Receive Interrupt Enable register (Reg 0x07), and their status

may be determined by reading the Receive Interrupt Status

register (Reg 0x08). If more than one interrupt is enabled, it is

necessary to read the Receive Interrupt Status register (Reg

0x08) to determine which event caused the IRQ pin to assert.

The function and operation of these interrupts are described in

detail in Section 7.0.

IRQ

DIOVAL

v8

v9

v10

d10

v11

d11

v12

d12

v13

d13

v14

d14

v...

d...

v0

d0

v1

d1

v2

d2

v3

d3

v4

d4

v5

d5

v6

v7

data to mcu

DIO

d6

d7

d8

d9

Figure 5-6. DIO Receive Sequence

IRQ

DIOVAL

DIO

v8

v9

v10

v11

d11

v12

d12

v13

d13

v14

d14

v...

d...

v0

v1

v2

d2

v3

d3

v4

d4

v5

v6

v7

data from mcu

d8

d9

d10

d0

d1

d5

d6

d7

Figure 5-7. DIO Transmit Sequence

Document #: 38-16008 Rev. *C

Page 5 of 33

CYWUSB6935

Figure 6-2 shows an application example of a WirelessUSB

LR alarm system where a single hub node is connected to an

alarm panel. The hub node wirelessly receives information

from multiple sensor nodes in order to control the alarm panel.

6.0

Application Examples

Figure 6-1 shows a block diagram example of a typical battery

powered device using the CYWUSB6935 chip.

LDO/

3.3 V

PCB Trace

DC2DC

0.1µF

Antenna

+

-

Battery

2.0 pF

3.3 nH

1.2 pF

Vcc

RESET

RFIN

PD

RFOUT

PSoC

Application

Hardware

2.2 nH

27 pF

IRQ

WirelessUSB LR

8-bit MCU

13MHz

Crystal

SPI

4

Figure 6-1. CYWUSB6935 Battery Powered Device

PSoC + SMOKE

DETECTOR

W irelessUSB LR

ALARM PANEL

PSoC + MOTION

DETECTOR

PSoC + DOOR

SENSOR

W irelessUSB LR +

PSoC

…

W irelessUSB LR

PSoC + KEYPAD

Figure 6-2. WirelessUSB LR Alarm System

Document #: 38-16008 Rev. *C

Page 6 of 33

CYWUSB6935

7.0

Register Descriptions

Table 7-1 displays the list of registers inside the

CYWUSB6935 that are addressable through the SPI interface.

All registers are read and writable, except where noted.

Table 7-1. CYWUSB6935 Register Map^[1]

CYWUSB6935

Address

Register Name

Revision ID

Control

Data Rate

Configuration

SERDES Control

Receive SERDES Interrupt Enable REG_RX_INT_EN

Receive SERDES Interrupt Status REG_RX_INT_STAT

Receive SERDES Data A

Receive SERDES Valid A

Receive SERDES Data B

Receive SERDES Valid B

Transmit SERDES Interrupt Enable REG_TX_INT_EN

Transmit SERDES Interrupt Status REG_TX_INT_STAT

Transmit SERDES Data

Transmit SERDES Valid

PN Code

Threshold Low

Threshold High

Wake Enable

Wake Status

Analog Control

Channel

Receive Signal Strength Indicator REG_RSSI

PA Bias

Crystal Adjust

Mnemonic

Page

8

Default

0x07

0x00

0x01

0x03

0x00

Access

RO

REG_ID

0x00

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

REG_CONTROL

REG_DATA_RATE

REG_CONFIG

RW

RO

9

10

11

12

13

14

15

16

17

18

19

20

21

REG_SERDES_CTL

REG_RX_DATA_A

REG_RX_VALID_A

REG_RX_DATA_B

REG_RX_VALID_B

RW

RO

REG_TX_DATA

REG_TX_VALID

REG_PN_CODE

REG_THRESHOLD_L

REG_THRESHOLD_H

REG_WAKE_EN

REG_WAKE_STAT

REG_ANALOG_CTL

REG_CHANNEL

RW

RO

RW

RO

RW

RO

0x1E8B6A3DE0E9B222

0x18–0x11

0x19

0x08

0x38

0x00

0x01

0x04

0x00

0x64

–

0x1A

0x1C

0x1D

0x20

0x21

0x22

0x23

0x24

0x26

0x2E

0x2F

0x32

0x33

0x38

REG_PA

REG_CRYSTAL_ADJ

REG_VCO_CAL

VCO Calibration

Reg Power Control

Carrier Detect

Clock Manual

Clock Enable

REG_PWR_CTL

REG_CARRIER_DETECT

REG_CLOCK_MANUAL

REG_CLOCK_ENABLE

REG_SYN_LOCK_CNT

REG_MID

Synthesizer Lock Count

Manufacturing ID

0x3C–0x3F

Note:

1. All registers are accessed Little Endian.

Document #: 38-16008 Rev. *C

Page 7 of 33

CYWUSB6935

Addr: 0x00

REG_ID

Default: 0x07

7

6

5

4

3

2

1

0

Silicon ID

Product ID

Figure 7-1. Revision ID Register

Bit

7:4

3:0

Name

Silicon ID

Description

These are the Silicon ID revision bits. 0000 = Rev A, 0001 = Rev B, etc. These bits are read-only.

Product ID These are the Product ID revision bits. Fixed at value 0111. These bits are read-only.

Addr: 0x03

REG_CONTROL

Default: 0x00

7

6

5

4

3

2

1

0

RX

TX

PN Code

Bypass Internal Auto Internal PA

Internal PA

Reserved

Enable

Select

Syn Lock Signal Disable

Enable

Figure 7-2. Control

Bit Name

Description

7

6

5

RX Enable

The Receive Enable bit is used to place the IC in receive mode.

1 = Receive Enabled

0 = Receive Disabled

TX Enable

The Transmit Enable bit is used to place the IC in transmit mode.

1 = Transmit Enabled

0 = Transmit Disabled

PN Code Select The Pseudo-Noise Code Select bit selects between the upper or lower half of the 64 chips/bit PN code.

1 = 32 Most Significant Bits of PN code are used

0 = 32 Least Significant Bits of PN code are used

This bit applies only when the Code Width bit is set to 32 chips/bit PN codes (Reg 0x04, bit 2=1).

4

Bypass Internal This bit controls whether the state machine waits for the internal Syn Lock Signal before waiting for the amount of

Syn Lock Signal time specified in the Syn Lock Count register (Reg 0x38), in units of 2 µs. If the internal Syn Lock Signal is used

then set Syn Lock Count to 25 to provide additional assurance that the synthesizer has settled.

1 = Bypass the Internal Syn Lock Signal and wait the amount of time in Syn Lock Count register (Reg 0x38)

0 = Wait for the Syn Lock Signal and then wait the amount of time specified in Syn Lock Count register (Reg 0x38)

It is recommended that the application MCU sets this bit to 1 in order to guarantee a consistent settle time for the

synthesizer.

3

2

AutoInternalPA The Auto Internal PA Disable bit is used to determine the method of controlling the Internal Power Amplifier. The

Disable

two options are automatic control by the baseband or by firmware through register writes. For external PA usage,

please see the description of the REG_ANALOG_CTL register (Reg 0x20).

1 = Register controlled Internal PA Enable

0 = Auto controlled Internal PA Enable

When this bit is set to 1, the enabled state of the Internal PA is directly controlled by bit Internal PA Enable (Reg

0x03, bit 2). It is recommended that this bit is set to 0, leaving the PA control to the baseband.

Internal PA

Enable

The Internal PA Enable bit is used to enable or disable the Internal Power Amplifier.

1 = Internal Power Amplifier Enabled

0 = Internal Power Amplifier Disabled

This bit only applies when the Auto Internal PA Disable bit is selected (Reg 0x03, bit 3=1), otherwise this bit is don’t

care.

1

0

Reserved

This bit is reserved and should be written with a zero.

Document #: 38-16008 Rev. *C

Page 8 of 33

CYWUSB6935

Addr: 0x04

REG_DATA_RATE

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

Code Width

Data Rate

Sample Rate

Figure 7-3. Data Rate

Bit Name

Description

These bits are reserved and should be written with zeroes.

7:3 Reserved

2^[2]Code Width The Code Width bit is used to select between 32 chips/bit and 64 chips/bit PN codes.

1 = 32 chips/bit PN codes

0 = 64 chips/bit PN codes

The number of chips/bit used impacts a number of factors such as data throughput, range and robustness to inter-

ference. By choosing a 32 chips/bit PN-code, the data throughput can be doubled or even quadrupled (when double

data rate is set). A 64 chips/bit PN code offers improved range over its 32 chips/bit counterpart as well as more

robustness to interference. By selecting to use a 32 chips/bit PN code a number of other register bits are impacted

and need to be addressed. These are PN Code Select (Reg 0x03, bit 5), Data Rate (Reg 0x04, bit 1), and Sample

Rate (Reg 0x04, bit 0).

1^[2]Data Rate

The Data Rate bit allows the user to select Double Data Rate mode of operation which delivers a raw data rate of

62.5kbits/sec.

1 = Double Data Rate - 2 bits per PN code (No odd bit transmissions)

0 = Normal Data Rate - 1 bit per PN code

This bit is applicable only when using 32 chips/bit PN codes which can be selected by setting the Code Width bit (Reg

0x04, bit 2=1). When using Double Data Rate, the raw data throughput is 62.5 kbits/sec because every 32 chips/bit

PN code is interpreted as 2 bits of data. When using this mode a single 64 chips/bit PN code is placed in the PN code

register. This 64 chips/bit PN code is then split into two and used by the baseband to offer the Double Data Rate

capability. When using Normal Data Rate, the raw data throughput is 32 kbits/sec. Additionally, Normal Data Rate

enables the user to potentially correlate data using two differing 32 chips/bit PN codes.

0^[2]Sample Rate The Sample Rate bit allows the use of the 12x sampling when using 32 chips/bit PN codes and Normal Data Rate.

1 = 12x Oversampling

0 = 6x Oversampling

Using 12x oversampling improves the correlators receive sensitivity. When using 64 chips/bit PN codes or Double Data

Rate this bit is don’t care. The only time when 12x oversampling can be selected is when a 32 chips/bit PN code is

being used with Normal Data Rate.

Note:

2. The following Reg 0x04, bits 2:0 values are not valid:

•

001–Not Valid

010–Not Valid

011–Not Valid

111–Not Valid

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CYWUSB6935

Addr: 0x05

REG_CONFIG

Default: 0x01

7

6

5

4

3

2

1

0

Reserved

IRQ Pin Select

Figure 7-4. Configuration

Bit Name

Description

7:2 Reserved

These bits are reserved and should be written with zeroes.

1:0 IRQ Pin Select The Interrupt Request Pin Select bits are used to determine the drive method of the IRQ pin.

11 = Open Source (IRQ asserted = 1, IRQ deasserted = Hi-Z)

10 = Open Drain (IRQ asserted = 0, IRQ deasserted = Hi-Z)

01 = CMOS (IRQ asserted = 1, IRQ deasserted = 0)

00 = CMOS Inverted (IRQ asserted = 0, IRQ deasserted = 1)

Addr: 0x06

REG_SERDES_CTL

Default: 0x03

7

6

5

4

3

2

1

0

Reserved

SERDES

Enable

EOF Length

Figure 7-5. SERDES Control

Bit

7:4

3

Name

Reserved

Description

These bits are reserved and should be written with zeroes.

SERDES Enable The SERDES Enable bit is used to switch between bit-serial mode and SERDES mode.

1 = SERDES enabled

0 = SERDES disabled, bit-serial mode enabled

When the SERDES is enabled data can be written to and read from the IC one byte at a time, through the use of

the SERDES Data registers. The bit-serial mode requires bits to be written one bit at a time through the use of

the DIO/DIOVAL pins, refer to section 3.2. It is recommended that SERDES mode be used to avoid the need to

manage the timing required by the bit-serial mode.

2:0

EOF Length

The End of Frame Length bits are used to set the number of sequential bit times for an inter-frame gap without

valid data before an EOF event will be generated. When in receive mode and a valid bit has been received the

EOF event can then be identified by the number of bit times that expire without correlating any new data. The

EOF event causes data to be moved to the proper SERDES Data Register and can also be used to generate

interrupts. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception.

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CYWUSB6935

Addr: 0x07

REG_RX_INT_EN

Default: 0x00

7

6

5

4

3

2

1

0

Underflow B

Overflow B

EOF B

Full B

Underflow A

Overflow A

EOF A

Full A

Figure 7-6. Receive SERDES Interrupt Enable

Bit Name

Description

7

6

5

Underflow B

The Underflow B bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES

Data B register (Reg 0x0B)

1 = Underflow B interrupt enabled for Receive SERDES Data B

0 = Underflow B interrupt disabled for Receive SERDES Data B

An underflow condition occurs when attempting to read the Receive SERDES Data B register (Reg 0x0B) when it is

empty.

Overflow B

EOF B

The Overflow B bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES

Data B register (Reg 0x0B)

1 = Overflow B interrupt enabled for Receive SERDES Data B

0 = Overflow B interrupt disabled for Receive SERDES Data B

An overflow condition occurs when new received data is written into the Receive SERDES Data B register (Reg

0x0B) before the prior data is read out.

The End of Frame B bit is used to enable the interrupt associated with the Channel B Receiver EOF condition.

1 = EOF B interrupt enabled for Channel B Receiver

0 = EOF B interrupt disabled for Channel B Receiver

The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has

been detected, and then the number of invalid bits in the frame exceeds the number in the EOF length field. If 0 is

the EOF length, and EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by

reading the receive status register

4

Full B

The Full B bit is used to enable the interrupt associated with the Receive SERDES Data B register (Reg 0x0B) having

data placed in it.

1 = Full B interrupt enabled for Receive SERDES Data B

0 = Full B interrupt disabled for Receive SERDES Data B

A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B

register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or

not a complete byte has been received.

3

2

1

Underflow A

Overflow A

EOF A

The Underflow A bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES

Data A register (Reg 0x09)

1 = Underflow A interrupt enabled for Receive SERDES Data A

0 = Underflow A interrupt disabled for Receive SERDES Data A

An underflow condition occurs when attempting to read the Receive SERDES Data A register (Reg 0x09) when it is

empty.

The Overflow A bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES

Data A register (0x09)

1 = Overflow A interrupt enabled for Receive SERDES Data A

0 = Overflow A interrupt disabled for Receive SERDES Data A

An overflow condition occurs when new receive data is written into the Receive SERDES Data A register (Reg 0x09)

before the prior data is read out.

The End of Frame A bit is used to enable the interrupt associated with an End of Frame condition with the Channel

A Receiver.

1 = EOF A interrupt enabled for Channel A Receiver

0 = EOF A interrupt disabled for Channel A Receiver

The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has

been detected, and then the number of invalid bits in a frame exceeds the number in the EOF length field. If 0 is the

EOF length, an EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by reading

the receive status register.

0

Full A

The Full A bit is used to enable the interrupt associated with the Receive SERDES Data A register (0x09) having

data written into it.

1 = Full A interrupt enabled for Receive SERDES Data A

0 = Full A interrupt disabled for Receive SERDES Data A

A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A

register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or

not a complete byte has been received.

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CYWUSB6935

Addr: 0x08

REG_RX_INT_STAT

Default: 0x00

7

6

5

4

3

2

1

0

Valid B

Flow Violation B

EOF B

Full B

Valid A

Flow Violation A

EOF A

Full A

Figure 7-7. Receive SERDES Interrupt Status^[3]

Bit Name

Description

7

Valid B

The Valid B bit is true when all the bits in the Receive SERDES Data B register (Reg 0x0B) are valid.

1 = All bits are valid for Receive SERDES Data B

0 = Not all bits are valid for Receive SERDES Data B

When data is written into the Receive SERDES Data B register (Reg 0x0B) this bit is set if all of the bits within the

byte that has been written are valid. This bit cannot generate an interrupt.

6

Flow Violation B The Flow Violation B bit is used to signal whether an overflow or underflow condition has occurred for the Receive

SERDES Data B register (Reg 0x0B).

1 = Overflow/underflow interrupt pending for Receive SERDES Data B

0 = No overflow/underflow interrupt pending for Receive SERDES Data B

Overflow conditions occur when the radio loads new data into the Receive SERDES Data B register (Reg 0x0B)

before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data B

register (Reg 0x0B) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register

(Reg 0x08)

5

4

EOF B

Full B

The End of Frame B bit is used to signal whether an EOF event has occurred on the Channel B receive.

1 = EOF interrupt pending for Channel B

0 = No EOF interrupt pending for Channel B

An EOF condition occurs for the Channel B Receiver when receive has begun and then the number of bit times

specified in the SERDES Control register (Reg 0x06) elapse without any valid bits being received. This bit is cleared

by reading the Receive Interrupt Status register (Reg 0x08)

The Full B bit is used to signal when the Receive SERDES Data B register (Reg 0x0B) is filled with data.

1 = Receive SERDES Data B full interrupt pending

0 = No Receive SERDES Data B full interrupt pending

A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B

register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or

not a complete byte has been received.

3

2

Valid A

The Valid A bit is true when all of the bits in the Receive SERDES Data A Register (Reg 0x09) are valid.

1 = All bits are valid for Receive SERDES Data A

0 = Not all bits are valid for Receive SERDES Data A

When data is written into the Receive SERDES Data A register (Reg 0x09) this bit is set if all of the bits within the

byte that has been written are valid. This bit cannot generate an interrupt.

Flow Violation A The Flow Violation A bit is used to signal whether an overflow or underflow condition has occurred for the Receive

SERDES Data A register (Reg 0x09).

1 = Overflow/underflow interrupt pending for Receive SERDES Data A

0 = No overflow/underflow interrupt pending for Receive SERDES Data A

Overflow conditions occur when the radio loads new data into the Receive SERDES Data A register (Reg 0x09)

before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data A

register (Reg 0x09) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register

(Reg 0x08)

1

0

EOF A

Full A

The End of Frame A bit is used to signal whether an EOF event has occurred on the Channel A receive.

1 = EOF interrupt pending for Channel A

0 = No EOF interrupt pending for Channel A

An EOF condition occurs for the Channel A Receiver when receive has begun and then the number of bit times

specified in the SERDES Control register (0x06) elapse without any valid bits being received. This bit is cleared by

reading the Receive Interrupt Status register (Reg 0x08).

The Full A bit is used to signal when the Receive SERDES Data A register (Reg 0x09) is filled with data.

1 = Receive SERDES Data A full interrupt pending

0 = No Receive SERDES Data A full interrupt pending

A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A

Register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or

not a complete byte has been received.

Note:

3. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The

status bits are affected by TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the receive status will read 0 if the IC is not in receive mode. These

registers are read-only.

Document #: 38-16008 Rev. *C

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CYWUSB6935

Addr: 0x09

REG_RX_DATA_A

Default: 0x00

7

6

5

4

3

2

1

0

Data

Figure 7-8. Receive SERDES Data A

Bit

Name Description

Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,

7:0

Data

followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.

Addr: 0x0A

REG_RX_VALID_A

Default: 0x00

7

6

5

4

3

2

1

0

Valid

Figure 7-9. Receive SERDES Valid A

Bit Name

Description

These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A “1” indicates that the

7:0 Valid

corresponding data bit is valid for Channel A.

If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES Data A

register (Reg 0x09) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg 0x0A). This

register is read-only.

Addr: 0x0B

REG_RX_DATA_B

Default: 0x00

7

6

5

4

3

2

1

0

Data

Figure 7-10. Receive SERDES Data B

Bit Name

Description

Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,

7:0 Data

followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.

Addr: 0x0C

REG_RX_VALID_B

Default: 0x00

7

6

5

4

3

2

1

0

Valid

Figure 7-11. Receive SERDES Valid B

Bit Name Description

These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A “1” indicates that the

7:0 Valid

corresponding data bit is valid for Channel B.

If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES Data B register

(Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register (Reg 0x0C). This register

is read-only.

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CYWUSB6935

Addr: 0x0D

REG_TX_INT_EN

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

Underflow

Overflow

Done

Empty

Figure 7-12. Transmit SERDES Interrupt Enable

Bit Name

7:4 Reserved

Description

These bits are reserved and should be written with zeroes.

The Underflow bit is used to enable the interrupt associated with an underflow condition associated with the Transmit

3

Underflow

SERDES Data register (Reg 0x0F)

1 = Underflow interrupt enabled

0 = Underflow interrupt disabled

An underflow condition occurs when attempting to transmit while the Transmit SERDES Data register (Reg 0x0F) does

not have any data.

The Overflow bit is used to enabled the interrupt associated with an overflow condition with the Transmit SERDES Data

register (0x0F).

2

Overflow

1 = Overflow interrupt enabled

0 = Overflow interrupt disabled

An overflow condition occurs when attempting to write new data to the Transmit SERDES Data register (Reg 0x0F)

before the preceding data has been transferred to the transmit shift register.

1

0

Done

The Done bit is used to enable the interrupt that signals the end of the transmission of data.

1 = Done interrupt enabled

0 = Done interrupt disabled

The Done condition occurs when the Transmit SERDES Data register (Reg 0x0F) has transmitted all of its data and

there is no more data for it to transmit.

Empty

The Empty bit is used to enable the interrupt that signals when the Transmit SERDES register (Reg 0x0F) is empty.

1 = Empty interrupt enabled

0 = Empty interrupt disabled

The Empty condition occurs when the Transmit SERDES Data register (Reg 0x0F) is loaded into the transmit buffer

and it's safe to load the next byte

Addr: 0x0E

REG_TX_INT_STAT

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

Underflow

Overflow

Done

Empty

Figure 7-13. Transmit SERDES Interrupt Status^[4]

Bit Name

Description

7:4 Reserved These bits are reserved. This register is read-only.

3

Underflow The Underflow bit is used to signal when an underflow condition associated with the Transmit SERDES Data register

(Reg 0x0F) has occurred.

1 = Underflow Interrupt pending

0 = No Underflow Interrupt pending

This IRQ will assert during an underflow condition to the Transmit SERDES Data register (Reg 0x0F). An underflow occurs

when the transmitter is ready to sample transmit data, but there is no data ready in the Transmit SERDES Data register

(Reg 0x0F). This will only assert after the transmitter has transmitted at least one bit. This bit is cleared by reading the

Transmit Interrupt Status register (Reg 0x0E).

2

Overflow The Overflow bit is used to signal when an overflow condition associated with the Transmit SERDES Data register (0x0F)

has occurred.

1 = Overflow Interrupt pending

0 = No Overflow Interrupt pending

This IRQ will assert during an overflow condition to the Transmit SERDES Data register (Reg 0x0F). An overflow occurs

when the new data is loaded into the Transmit SERDES Data register (Reg 0x0F) before the previous data has been sent.

This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E).

1

Done

The Done bit is used to signal the end of a data transmission.

1 = Done Interrupt pending

0 = No Done Interrupt pending

This IRQ will assert when the data is finished sending a byte of data and there is no more data to be sent. This will only

assert after the transmitter has transmitted as least one bit. This bit is cleared by reading the Transmit Interrupt Status

register (Reg 0x0E)

0

Empty

The Empty bit is used to signal when the Transmit SERDES Data register (Reg 0x0F) has been emptied.

1 = Empty Interrupt pending

0 = No Empty Interrupt pending

This IRQ will assert when the transmit serdes is empty. When this IRQ is asserted it is ok to write to the Transmit SERDES

Data register (Reg 0x0F). Writing the Transmit SERDES Data register (Reg 0x0F) will clear this IRQ. It will be set when

the data is loaded into the transmitter, and it is ok to write new data.

Note:

4. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling

IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in

transmit mode. These registers are read-only.

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CYWUSB6935

Addr: 0x0F

REG_TX_DATA

Default: 0x00

7

6

5

4

3

2

1

0

Data

Figure 7-14. Transmit SERDES Data

Bit Name Description

7:0 Data

Transmit Data. The over-the-air transmitted order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit

4, followed by bit 5, followed by bit 6, followed by bit 7.

Addr: 0x10

REG_TX_VALID

Default: 0x00

7

6

5

4

3

2

1

0

Valid

Figure 7-15. Transmit SERDES Valid

Bit

7:0

Name Description

Valid^[5]The Valid bits are used to determine which of the bits in the Transmit SERDES Data register (reg 0x0F) are valid.

1 = Valid transmit bit

0 = Invalid transmit bit

Default:

Addr: 0x18-11

REG_PN_CODE

0x1E8B6A3DE0E9B222

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

Address 0x18 Address 0x17 Address 0x16 Address 0x15

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Address 0x14 Address 0x13 Address 0x12

9

8

7

6

5

4

3

2

1

0

Address 0x11

Figure 7-16. PN Code

Bit

Name

Description

63:0 PN Codes

The value inside the 8 byte PN code register is used as the spreading code for DSSS communication. All 8 bytes can

be used together for 64 chips/bit PN code communication, or the registers can be split into two sets of 32 chips/bit

PN codes and these can be used alone or with each other to accomplish faster data rates. Not any 64 chips/bit value

can be used as a PN code as there are certain characteristics that are needed to minimize the possibility of multiple

PN codes interfering with each other or the possibility of invalid correlation. The over-the-air order is bit 0 followed by

bit 1... followed by bit 62, followed by bit 63.

Note:

5. The Valid bit in the Transmit SERDES Valid register (Reg 0x10) is used to mark whether the radio will send data or preamble during that bit time of the data

byte. Data is sent LSB first. The SERDES will continue to send data until there are no more VALID bits in the shifter. For example, writing 0x0F to the Transmit

SERDES Valid register (Reg 0x10) will send half a byte.

Document #: 38-16008 Rev. *C

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CYWUSB6935

Addr: 0x19

REG_THRESHOLD_L

Default: 0x08

7

6

5

4

3

2

1

0

Reserved

Threshold Low

Figure 7-17. Threshold Low

Bit Name

Description

7

Reserved

This bit is reserved and should be written with zero.

6:0 Threshold Low

The Threshold Low value is used to determine the number of missed chips allowed when attempting to correlate

a single data bit of value ‘0’. A perfect reception of a data bit of ‘0’ with a 64 chips/bit PN code would result in zero

correlation matches, meaning the exact inverse of the PN code has been received. By setting the Threshold Low

value to 0x08 for example, up to eight chips can be erroneous while still identifying the value of the received data

bit. This value along with the Threshold High value determine the correlator count values for logic ‘1’ and logic ‘0’.

The threshold values used determine the sensitivity of the receiver to interference and the dependability of the

received data. By allowing a minimal number of erroneous chips the dependability of the received data increases

while the robustness to interference decreases. On the other hand increasing the maximum number of missed

chips means reduced data integrity but increased robustness to interference and increased range.

Addr: 0x1A

REG_THRESHOLD_H

Default: 0x38

7

6

5

4

3

2

1

0

Reserved

Threshold High

Figure 7-18. Threshold High

Bit

7

6:0

Name

Reserved

Threshold High

Description

This bit is reserved and should be written with zero.

The Threshold High value is used to determine the number of matched chips allowed when attempting to correlate

a single data bit of value ‘1’. A perfect reception of a data bit of ‘1’ with a 64 chips/bit or a 32 chips/bit PN code

would result in 64 chips/bit or 32 chips/bit correlation matches, respectively, meaning every bit was received

perfectly. By setting the Threshold High value to 0x38 (64-8) for example, up to eight chips can be erroneous

while still identifying the value of the received data bit. This value along with the Threshold Low value determine

the correlator count values for logic ‘1’ and logic ‘0’. The threshold values used determine the sensitivity of the

receiver to interference and the dependability of the received data. By allowing a minimal number of erroneous

chips the dependability of the received data increases while the robustness to interference decreases. On the

other hand increasing the maximum number of missed chips means reduced data integrity but increased

robustness to interference and increased range.

Document #: 38-16008 Rev. *C

Page 16 of 33

CYWUSB6935

Addr: 0x1C

REG_WAKE_EN

Default: 0x00

7

6

5

4

3

2

1

0

Wakeup Enable

Reserved

Figure 7-19. Wake Enable

Bit Name

Description

These bits are reserved and should be written with zeroes.

7:1 Reserved

0

Wakeup Enable Wakeup interrupt enable.

0 = disabled

1 = enabled

A wakeup event is triggered when the PD pin is deasserted and once the IC is ready to receive SPI communications.

Addr: 0x1D

REG_WAKE_STAT

Default: 0x01

7

6

5

4

3

2

1

0

Wakeup Status

Reserved

Figure 7-20. Wake Status

Bit

7:1

0

Name

Reserved

Description

These bits are reserved. This register is read-only.

Wakeup Status Wakeup status.

0 = Wake interrupt not pending

1 = Wake interrupt pending

This IRQ will assert when a wakeup condition occurs. This bit is cleared by reading the Wake Status register (Reg

0x1D). This register is read-only.

Addr: 0x20

REG_ANALOG_CTL

Default: 0x00

7

6

5

4

3

2

1

0

Reg Write

Control

MID Read

Enable

Reserved

PA Output

Enable

PA Invert

Reset

Figure 7-21. Analog Control

Bit Name

Description

This bit is reserved and should be written with zero.

7

6

Reserved

Reg Write Control Enables write access to Reg 0x2E and Reg 0x2F.

1 = Enables write access to Reg 0x2E and Reg 0x2F

0 = Reg 0x2E and Reg 0x2F are read-only

5

MID Read Enable The MID Read Enable bit must be set to read the contents of the Manufacturing ID register (Reg 0x3C-0x3F).

Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. This bit should only be set when

reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F).

1 = Enables read of MID registers

0 = Disables read of MID registers

4:3 Reserved

These bits are reserved and should be written with zeroes.

2

PA Output Enable The Power Amplifier Output Enable bit is used to enable the PACTL pin for control of an external power amplifier.

1 = PA Control Output Enabled on PACTL pin

0 = PA Control Output Disabled on PACTL pin

1

PA Invert

Reset

The Power Amplifier Invert bit is used to specify the polarity of the PACTL signal when the PaOe bit is set high.

PA Output Enable and PA Invert cannot be simultaneously changed.

1 = PACTL active low

0 = PACTL active high

0

The Reset bit is used to generate a self-clearing device reset.

1 = Device Reset. All registers are restored to their default values.

0 = No Device Reset.

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CYWUSB6935

Addr: 0x21

REG_CHANNEL

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

Channel

Figure 7-22. Channel

Bit Name

Description

7

Reserved This bit is reserved and should be written with zero.

The Channel register (Reg 0x21) is used to determine the Synthesizer frequency. A value of 2 corresponds to a communi-

cation frequency of 2.402 GHz, while a value of 79 corresponds to a frequency of 2.479 GHz. The channels are separated

from each other by 1 MHz intervals.

6:0 Channel

Limit application usage to channels 2–79 to adhere to FCC regulations. FCC regulations require that channels 0 and 1 and

any channel greater than 79 be avoided. Use of other channels may be restricted by other regulatory agencies. The

application MCU must ensure that this register is modified before transmitting data over the air for the first time.

Addr: 0x22

REG_RSSI

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

Valid

RSSI

Figure 7-23. Receive Signal Strength Indicator (RSSI)^[6]

Bit Name

Description

These bits are reserved. This register is read-only.

7:6 Reserved

5

Valid

The Valid bit indicates whether the RSSI value in bits [4:0] are valid. This register is Read Only.

1 = RSSI value is valid

0 = RSSI value is invalid

The Receive Strength Signal Indicator (RSSI) value indicates the strength of the received signal. This is a read only

value with the higher values indicating stronger received signals meaning more reliable transmissions.

4:0 RSSI

Addr: 0x23

REG_PA

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

PA Bias

Figure 7-24. PA Bias

Bit Name

Description

7:3 Reserved

2:0 PA Bias

These bits are reserved and should be written with zeroes.

The Power Amplifier Bias (PA Bias) bits are used to set the transmit power of the IC through increasing (values up to 7)

or decreasing (values down to 0) the gain of the on-chip Power Amplifier. The higher the register value the higher the

transmit power. By changing the PA Bias value signal strength management functions can be accomplished. For general

purpose communication a value of 7 is recommended. See Table 4-1 for typical output power steps based on the PA

Bias bit settings.

Note:

6. The RSSI will collect a single value each time the part is put into receive mode via Control register (Reg 0x03, bit 7=1). See Section 4.7 for more details.

Document #: 38-16008 Rev. *C

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CYWUSB6935

Addr: 0x24

REG_CRYSTAL_ADJ

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

Clock Output

Crystal Adjust

Disable

Figure 7-25. Crystal Adjust

Bit Name

Description

7

6

Reserved

This bit is reserved and should be written with zero.

Clock Output Disable The Clock Output Disable bit disables the 13-MHz clock driven on the X13OUT pin.

1 = No 13-MHz clock driven externally

0 = 13-MHz clock driven externally

If the 13-MHz clock is driven on the X13OUT pin then receive sensitivity will be reduced by –4 dBm on channels

5+13n. By default the 13-MHz clock output pin is enabled. This pin is useful for adjusting the 13-MHz clock, but

it interfere with every 13th channel beginning with 2.405-GHz channel. Therefore, it is recommended that the

13-MHz clock output pin be disabled when not in use.

The Crystal Adjust value is used to calibrate the on-chip parallel load capacitance supplied to the crystal. Each

increment of the Crystal Adjust value typically adds 0.135 pF of parallel load capacitance. The total range is 8.5

pF, starting at 8.65 pF. These numbers do not include PCB parasitics, which can add an additional 1–2 pF.

5:0 Crystal Adjust

Addr: 0x26

REG_VCO_CAL

Default: 0x00

7

6

5

4

3

2

1

0

VCO Slope Enable

Reserved

Figure 7-26. VCO Calibration

Bit Name

Description

7:6 VCO Slope Enable The Voltage Controlled Oscillator (VCO) Slope Enable bits are used to specify the amount of variance automat-

(Write-Only)

ically added to the VCO.

11 = –5/+5 VCO adjust. The application MCU must configure this option during initialization

10 = –2/+3 VCO adjust

01 = Reserved

00 = No VCO adjust

These bits are undefined for read operations.

5:0 Reserved

These bits are reserved and should be written with zeroes.

Document #: 38-16008 Rev. *C

Page 19 of 33

CYWUSB6935

Addr: 0x2E

REG_PWR_CTL

Default: 0x00

7

6

5

4

3

2

1

0

Reg Power

Reserved

Control

Figure 7-27. Reg Power Control

Bit Name

Description

7

Reg Power When set, this bit disables unused circuitry and saves radio power. The user must set Reg 0x20, bit 6=1 to enable

Control

writes to Reg 0x2E. The application MCU must set this bit during initialization.

These bits are reserved and should be written with zeroes.

6:0 Reserved

Addr: 0x2F

REG_CARRIER_DETECT

Default: 0x00

7

6

5

4

3

2

1

0

Carrier Detect

Override

Reserved

Figure 7-28. Carrier Detect

Bit Name

Description

7

Carrier Detect Override When set, this bit overrides carrier detect. The user must set Reg 0x20, bit 6=1 to enable writes to Reg 0x2F.

6:0 Reserved

These bits are reserved and should be written with zeroes.

Addr: 0x32

REG_CLOCK_MANUAL

Default: 0x00

7

6

5

4

3

2

1

0

Manual Clock Overrides

Figure 7-29. Clock Manual

Bit Name

Description

7:0 Manual Clock Overrides This register must be written with 0x41 after reset for correct operation

Addr: 0x33

REG_CLOCK_ENABLE

Default: 0x00

7

6

5

4

3

2

1

0

Manual Clock Enables

Figure 7-30. Clock Enable

Bit Name

Description

7:0 Manual Clock Enables This register must be written with 0x41 after reset for correct operation

Document #: 38-16008 Rev. *C

Page 20 of 33

CYWUSB6935

Addr: 0x38

REG_SYN_LOCK_CNT

Default: 0x64

7

6

5

4

3

2

1

0

Count

Figure 7-31. Synthesizer Lock Count

Bit Name Description

Determines the length of delay in 2-µs increments for the synthesizer to lock when auto synthesizer is enabled via Control

7:0 Count

register (0x03, bit 1=0) and not using the PLL lock signal. The default register setting is typically sufficient.

Addr: 0x3C-3F

REG_MID

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Address 0x3F Address 0x3E Address 0x3D

Address 0x3C

Figure 7-32. Manufacturing ID

Bit

Name

Description

31:30 Address[31:30] These bits are read back as zeroes.

29:0 Address[29:0] These bits are the Manufacturing ID (MID) for each IC. The contents of these bits cannot be read unless the MID

Read Enable bit (bit 5) is set in the Analog Control register (Reg 0x20). Enabling the Manufacturing ID register (Reg

0x3C-0x3F) consumes power. The MID Read Enable bit in the Analog Control register (Reg 0x20, bit 5) should only

be set when reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F). This register is read-only.

Document #: 38-16008 Rev. *C

Page 21 of 33

CYWUSB6935

8.0

Pin Descriptions

Table 8-1. Pin Description Table

Pin QFN

Name

Type

Default

Description

Analog RF

46

5

RFIN

RFOUT

Input

Output

Input

N/A

RF Input. Modulated RF signal received.

RF Output. Modulated RF signal to be transmitted.

Crystal / Power Control

38

35

26

33

X13

Input

Output/Hi-Z

Input

N/A

Crystal Input. (refer to Section 4.6).

X13IN

X13OUT

PD

Output System Clock. Buffered 13-MHz system clock.

N/A

Power Down. Asserting this input (low), will put the IC in the Suspend

Mode (X13OUT is 0 when PD is Low).

14

34

RESET

PACTL

Input

I/O

N/A

Input

Active LOW Reset. Device reset.

PACTL. External Power Amplifier control. Pull-down or make output.

SERDES Bypass Mode Communications/Interrupt

20

19

21

DIO

DIOVAL

IRQ

I/O

Input

Data Input/Output. SERDES Bypass Mode Data Transmit/Receive.

Data I/O Valid. SERDES Bypass Mode Data Transmit/Receive Valid.

Output /Hi-Z

Output IRQ. Interrupt and SERDES Bypass Mode DIOCLK.

SPI Communications

23

24

25

22

MOSI

MISO

SCK

SS

Input

Output/Hi-Z

Input

N/A

Hi-Z

N/A

Master-Output-Slave-Input Data. SPI data input pin.

Master-Input-Slave-Output Data. SPI data output pin.

SPI Input Clock. SPI clock.

Input

Slave Select Enable. SPI enable.

Power and Ground

V

_CC= 2.7V to 3.6V.

6, 9, 16,

28, 29, 32,

VCC

GND

H

L

41, 42, 44,

45

Ground = 0V.

13

GND

Must be tied to Ground.

1,2,3,4,7,

8, 10, 11,

12, 15, 17,

18, 27, 30, NC

31, 36, 37,

39, 40, 43,

47, 48

N/A

L

Must be tied to Ground.

Exposed GND

paddle

GND

Document #: 38-16008 Rev. *C

Page 22 of 33

CYWUSB6935

Top View*

NC

1

2

3

4

5

6

7

8

9

36 NC

35 X13IN

34 PACTL

33 PD

NC

RFOUT

V_CC

32 V_CC

31 NC

CYWUSB6935

48 QFN

NC

30 NC

NC

V_CC

29

28

V_CC

NC 10

NC 11

NC 12

27 NC

26 X13OUT

25 SCK

* E-PAD BOTTOM SIDE

Figure 8-1. CYWUSB6935, 48 QFN – Top View

Document #: 38-16008 Rev. *C

Page 23 of 33

CYWUSB6935

9.0

Absolute Maximum Ratings

10.0

Operating Conditions

Storage Temperature ..................................–65°C to +150°C

Ambient Temperature with Power Applied..–55°C to +125°C

Supply Voltage on V_CCrelative to VSS.......... –0.3V to +3.9V

DC Voltage to Logic Inputs^[7]..................–0.3V to V_CC+0.3V

V_CC(Supply Voltage)..........................................2.7V to 3.6V

T_A(Ambient Temperature Under Bias)....... -40°C to +85°C^[9]

T_A(Ambient Temperature Under Bias).........0°C to +70°C^[10]

Ground Voltage ................................................................. 0V

DC Voltage applied to

F_OSC(Oscillator or Crystal Frequency) ..................... 13 MHz

Outputs in High-Z State...........................–0.3V to V_CC+0.3V

Static Discharge Voltage (Digital)^[8]...........................>2000V

Static Discharge Voltage (RF)^[8].................................... 500V

Latch-up Current..................................... +200 mA, –200 mA

11.0

DC Characteristics (Over the Operating Range)

Description

Parameter

Conditions

Min.

Typ.^[12]Max. Unit

V_CC

Supply Voltage

2.7

3.0

V_CC

3.0

3.6

V

V_OH1

Output High Voltage condition 1

Output High Voltage condition 2

Output Low Voltage

At I_OH= –100.0 µA V_CC– 0.1

V_OH2

At I_OH= –2.0 mA

At I_OL= 2.0 mA

2.4

V

V_OL

0.0

0.4

V

[11]

V_IH

Input High Voltage

2.0

–0.3

–1

V_CC

V

V_IL

Input Low Voltage

0.8

+1

10

15

V

I_IL

Input Leakage Current

0 < V_IN< V_CC

0.26

3.5

µA

pF

µA

mA

µA

mA

C_IN

Pin Input Capacitance (except X13, X13IN, RFIN)

Current consumption during power-down mode PD = LOW

I_Sleep

0.24

3

IDLE I_CC

STARTUP I_CC

TX AVG I_CC

RX I_{CC (PEAK)}

TX I_{CC (PEAK)}

Current consumption without synthesizer

ICC from PD high to oscillator stable.

Average transmitter current consumption^[13]

Current consumption during receive

Current consumption during transmit

PD = HIGH

1.8

1.4

57.7

69.1

28.7

SYNTH SETTLE Current consumption with Synthesizer on, No

I_CC

Transmit or Receive

Notes:

7. It is permissible to connect voltages above V to inputs through a series resistor limiting input current to 1 mA. This can’t be done during power down mode.

CC

AC timing not guaranteed.

8. Human Body Model (HBM).

9. Industrial temperature operating range.

10. Commercial temperature operating range.

11. It is permissible to connect voltages above V to inputs through a series resistor limiting input current to 1 mA.

CC

12. Typ. values measured with V = 3.0V @ 25°C

CC

13. Average I when transmitting a 10-byte packet every 15 minutes using the WirelessUSB N:1 protocol.

CC

Document #: 38-16008 Rev. *C

Page 24 of 33

CYWUSB6935

12.0

AC Characteristics ^[14]

Table 12-1. SPI Interface^[16]

Parameter

Description

Min.

476

238

158

Typ.

Max.

Unit

ns

t_{SCK_CYC}

t_{SCK_HI (BURST READ)}

t_{SCK_HI}

t_{SCK_LO}

t_{DAT_SU}

t_{DAT_HLD}

t_{DAT_VAL}

t_{SS_SU}

SPI Clock Period

[15]

SPI Clock High Time

SPI Clock Low Time

SPI Input Data Set-up Time

SPI Input Data Hold Time

SPI Output Data Valid Time

10

97^[16]

77^[16]

174^[16]

SPI Slave Select Set-up Time before first positive edge of SCK^[17]250

t_{SS_HLD}

SPI Slave Select Hold Time after last negative edge of SCK

80

t_{SCK_CYC}

t_{SCK_HI}

t_{SCK_LO}

SCK

t_{SS_SU}

t_{DAT_SU}

t_{SS_HLD}

SS

M O SI

M ISO

t_{DAT_HLD}

data from m cu

data to m cu

data

t_{DAT_VAL}

data to m cu

Figure 12-1. SPI Timing Diagram

t_{SCK_CYC}

t_{SCK_HI}

t_{SCK_LO}

t_{SCK_HI (BURST READ)}

every 8^thSCK_HI

every 9^thSCK_HI

every 10^thSCK_HI

SCK

SS

data to mcu

data

MISO

t_{DAT_VAL}

Figure 12-2. SPI Burst Read Every 9th SCK HI Stretch Timing Diagram

Notes:

14. AC values are not guaranteed if voltages on any pin exceed V

.

CC

15. This stretch only applies to every 9th SCK HI pulse for SPI Burst Reads only.

16. For F

= 13 MHz, 3.3v @ 25°C.

OSC

17. SCK must start low, otherwise the success of SPI transactions are not guaranteed.

Document #: 38-16008 Rev. *C

Page 25 of 33

CYWUSB6935

Table 12-2. DIO Interface

Parameter

Transmit

Description

Min.

Typ.

Max.

Unit

t_{TX_DIOVAL_SU}

t_{TX_DIO_SU}

t_{TX_DIOVAL_HLD}

t_{TX_DIO_HLD}

t_{TX_IRQ_HI}

DIOVAL Set-up Time

2.1

0

µs

DIO Set-up Time

DIOVAL Hold Time

DIO Hold Time

Minimum IRQ High Time – 32 chips/bit DDR

Minimum IRQ High Time – 32 chips/bit

Minimum IRQ High Time – 64 chips/bit

Minimum IRQ Low Time – 32 chips/bit DDR

Minimum IRQ Low Time – 32 chips/bit

Minimum IRQ Low Time – 64 chips/bit

0

8

16

32

8

16

32

t_{TX_IRQ_LO}

Receive

t_{RX_DIOVAL_VLD}

DIOVAL Valid Time – 32 chips/bit DDR

DIOVAL Valid Time – 32 chips/bit

DIOVAL Valid Time – 64 chips/bit

DIO Valid Time – 32 chips/bit DDR

DIO Valid Time – 32 chips/bit

DIO Valid Time – 64 chips/bit

Minimum IRQ High Time – 32 chips/bit DDR

Minimum IRQ High Time – 32 chips/bit

Minimum IRQ High Time – 64 chips/bit

Minimum IRQ Low Time – 32 chips/bit DDR

Minimum IRQ Low Time – 32 chips/bit

Minimum IRQ Low Time – 64 chips/bit

–0.01

6.1

8.2

16.1

6.1

8.2

16.1

µs

t_{RX_DIO_VLD}

t_{RX_IRQ_HI}

t_{RX_IRQ_LO}

1

8

16

32

t_{RX_IRQ_HI}

t_{RX_IRQ _LO}

IRQ

DIO /

data

DIO VAL

t_{RX_DIO _VLD}

t_{RX_DIOVAL_VLD}

Figure 12-3. DIO Receive Timing Diagram

t_{TX_IRQ_HI}

t_{TX_IRQ_LO}

IRQ

DIO/

data

DIOVAL

t_{TX_DIO_SU}

t_{TX_DIOVAL_SU}

t_{TX_DIO_HLD}

t_{TX_DIOVAL_HLD}

Figure 12-4. DIO Transmit Timing Diagram

Document #: 38-16008 Rev. *C

Page 26 of 33

CYWUSB6935

12.1

Table 12-3. Radio Parameters

Parameter Description

RF Frequency Range

Radio Parameters

Conditions

Min.

2.400

Typ.

Max.

2.483

Unit

Note 19

GHz

–3

Radio Receiver (T = 25°C, V = 3.3V, fosc = 13.000 MHz ± 2 ppm, X13OUT off, 64 chips/bit, Threshold Low = 8, Threshold High = 56, BER < 10

)

CC

Sensitivity

Maximum Received Signal

–86

–20

–95

–7

dBm

RSSI value for PWR_in> –40 dBm

RSSI value for PWR_in< –95 dBm

Interference Performance

28–31

0–10

Co-channel Interference rejection Carrier-to-Interference (C/I) C = –60 dBm

6

-5

–33

–45

–35

–41

dB

Adjacent (1 MHz) channel selectivity C/I 1 MHz

Adjacent (2 MHz) channel selectivity C/I 2 MHz

Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz

Image^[21]Frequency Interference, C/I Image

C = –60 dBm

C = –67 dBm

Adjacent (1 MHz) interference to in-band image frequency, C/I C = –67 dBm

image ±1 MHz

Out-of-Band Blocking Interference Signal Frequency

30 MHz–2399 MHz except (FO/N & FO/N±1 MHz)^[18]

2498 MHz–12.75 GHz, except (FO*N & FO*N±1 MHz)

C = –67 dBm

–22

–21

–32

dBm

[18]

Intermodulation

C = –64 dBm

∆f = 5,10 MHz

Spurious Emission

30 MHz–1 GHz

1 GHz–12.75 GHz except (4.8 GHz–5.0 GHz)

4.8 GHz–5.0 GHz

–57

–54

dBm

–40^20]

Radio Transmitter (T = 25°C, V = 3.3V, fosc = 13.000 MHz ± 2 ppm)

CC

Maximum RF Transmit Power

RF Power Control Range

RF Power Range Control Step Size

Frequency Deviation

Zero Crossing Error

PA = 7

-5

–0.4

28.6

4.1

270

320

±75

860

dBm

dB

kHz

ns

seven steps, monotonic

PN Code Pattern 10101010

PN Code Pattern 11110000

Occupied Bandwidth

100-kHz resolution

bandwidth, –6 dBc

500

kHz

Initial Frequency Offset

In-band Spurious

±50

kHz

Second Channel Power (±2 MHz)

> Third Channel Power (>3 MHz)

Non-Harmonically Related Spurs

30 MHz–12.75 GHz

–45

–52

–30

–40

dBm

–54

dBm

Harmonic Spurs

Second Harmonic

Third Harmonic

–28

–25

–42

dBm

Fourth and Greater Harmonics

Notes:

18. FO = Tuned Frequency, N = Integer.

19. Subject to regulation.

20. Antenna matching network and antenna will attenuate the output signal at these frequencies to meet regulatory requirements.

21. Image frequency is +4 MHz from desired channel (2 MHz low IF, high side injection).

Document #: 38-16008 Rev. *C

Page 27 of 33

CYWUSB6935

12.2

Power Management Timing

[26]

Table 12-4. Power Management Timing (The values below are dependent upon oscillator network component selection)

Parameter

t_{PDN_X13}

t_{SPI_RDY}

t_{PWR_RST}

t_RST

t_{PWR_PD}

t_WAKE

t_PD

Description

Time from PD deassert to X13OUT

Time from oscillator stable to start of SPI transactions

Power On to RESET deasserted

Minimum RESET asserted pulse width

Power On to PD deasserted^[22]

PD deassert to clocks running^[23]

Minimum PD asserted pulse width

PD assert to low power mode

PD deassert to IRQ^[24]assert (wake interrupt)^[25]

PD deassert to clock stable

Conditions

Min.

Typ

2000

Max.

Unit

µs

ns

µs

1

1300

1

V_CC@ 2.7V

1300

2000

10

t_SLEEP

50

t_{WAKE_INT}

t_STABLE

t_STABLE2

2000

2100

to within ±10 ppm

IRQ assert (wake interrupt) to clock stable

t_{SPI_RDY}

t_{PDN_X13}

X13OUT

VCC

t_{PW R_RST}

t_{PW R_PD}

t_RST

RESET

PD

Figure 12-5. Power On Reset/Reset Timing

t_WAKE

X13OUT

PD

t_PD

t_STABLE

t_SLEEP

t_{WAKE_INT}

IRQ

t_STABLE2

Figure 12-6. Sleep / Wake Timing

Notes:

22. The PD pin must be asserted at power up to ensure proper crystal startup.

23. When X13OUT is enabled.

24. Both the polarity and the drive method of the IRQ pin are programmable. See page 10 for more details. Figure 12-6 illustrates default values for the Configuration

register (Reg 0x05, bits 1:0).

25. A wakeup event is triggered when the PD pin is deasserted. Figure 12-6 illustrates a wakeup event configured to trigger an IRQ pin event via the Wake Enable

register (Reg 0x1C, bit 0=1).

26. Measured with CTS ATXN6077A crystal.

Document #: 38-16008 Rev. *C

Page 28 of 33

CYWUSB6935

12.3

Typical Operating Characteristics

Receiver Sensitivity

2.440GHz, 3.3v

BER Sensitivityvs Temp

GUID: 0x0ECC7E75

-86

-88

-90

-92

-94

-96

-98

-100

-93.5

-94.0

-94.5

-95.0

-95.5

-96.0

-96.5

-97.0

-97.5

-98.0

Spec Min

Spec Typ

Temp Spec

Typical

3.3

3.7

2.6

-50

0

50

100

-50

-30

-10

10

30

50

70

90

Temperature (°C)

Temp (degC)

BER Sensitivity vs Temp @2.6v

BERSensitivityvsTemp@3.3v

-92.5

-93.0

-93.5

-94.0

-94.5

-95.0

-95.5

-96.0

-96.5

-94.0

-94.5

-95.0

-95.5

-96.0

-96.5

-97.0

-97.5

LR06 0x0ECC7E75

LR07 0x17D34AAD

LR14 0x0DD2E9F8

LR06 0x0ECC7E75

LR07 0x17D34AAD

LR14 0x0DD2E9F8

-50

-30

-10

10

30

50

70

90

-50

-30

-10

10

30

50

70

90

Temperature (°C)

BERSensitivityvsTemp@3.7v

BERSensitivityvsVcc@-45°C

-94.5

-95.0

-95.5

-96.0

-96.5

-97.0

-97.5

-98.0

-95.0

LR06 0x0ECC7E75

LR07 0x17D34AAD

LR14 0x0DD2E9F8

LR06 0x0ECC7E75

LR07 0x17D34AAD

LR14 0x0DD2E9F8

-95.5

-96.0

-96.5

-97.0

-97.5

-98.0

-50

-30

-10

10

30

50

70

90

2.5

2.7

2.9

3.1

3.3

3.5

3.7

3.9

Temperature (°C)

Vcc

Document #: 38-16008 Rev. *C

Page 29 of 33

CYWUSB6935

BERSensitivityvsVcc@90°C

BERSensitivityvsVcc@25°C

-94.0

-94.5

-95.0

-95.5

-96.0

-96.5

-93.0

-93.5

-94.0

-94.5

-95.0

-95.5

LR06 0x0ECC7E75

LR07 0x17D34AAD

LR14 0x0DD2E9F8

LR06 0x0ECC7E75

LR07 0x17D34AAD

LR14 0x0DD2E9F8

2.5

2.7

2.9

3.1

3.3

3.5

3.7

3.9

2.5

2.7

2.9

3.1

3.3

3.5

3.7

3.9

Vcc

Maximum Transmit Output Power

2.440GHz, 3.3v

Tx Ch40 Output Power

LR18 0x17D34E2D

0

-1

-2

-3

-4

-5

-6

0.4

0.2

0

Spec Min

Spec Typ

Temp Spec

Average

2.6

-0.2

-0.4

-0.6

-0.8

-1

3.3

3.7

-50

-30

-10

10

30

50

70

90

-60

-40

-20

0

20

40

60

80

100

Temp (degC)

Tx Ch40 Output Power

LR20 0xDD2E6A8

Tx Ch0 Output Power

LR21 0xECC7E71

0

-0.2

-0.4

-0.6

-0.8

-1

0

-1

-2

-3

-4

-5

-6

2.6

3.3

3.7

Spec Min

Spec Typ

Temp Spec

2.6

3.3

3.7

-1.2

-1.4

-1.6

-1.8

-50

-30

-10

10

30

50

70

90

-60

-40

-20

0

20

40

60

80

100

Temp (degC)

Document #: 38-16008 Rev. *C

Page 30 of 33

CYWUSB6935

12.4

AC Test Loads and Waveforms for Digital Pins

AC Test Loads

DC Test Load

OUTPUT

R1

V

CC

5 pF

30 pF

OUTPUT

INCLUDING

JIG AND

SCOPE

INCLUDING

R2

JIG AND

SCOPE

Max

Typical

ALL INPUT PULSES

90%

10%

V

Parameter

R1

R2

R_TH

V_TH

Unit

Ω

CC

90%

10%

1071

937

500

1.4

GND

Ω

Fall time: 1 V/ns

Ω

Rise time: 1 V/ns

V

THÉ

VENIN EQUIVALENT

Equivalent to:

OUTPUT

V_CC

3.00

R

TH

V

TH

Figure 12-7. AC Test Loads and Waveforms for Digital Pins

13.0

Ordering Information

Part Number

CYWUSB6935-48LFXI

Radio

Transceiver

Package Name

48 QFN

Package Type

48 Quad Flat Package No Leads Lead-Free Industrial

Operating Range

CYWUSB6935-48LFXC Transceiver

48 QFN

48 Quad Flat Package No Leads Lead-Free Commercial

Document #: 38-16008 Rev. *C

Page 31 of 33

CYWUSB6935

14.0

Package Description

0.08

C

6.90

7.10

1.00 MAX.

0.0ꢀ MAX.

0.20 REF.

X

0.80 MAX.

6.70

6.80

0.23 0.0ꢀ

PIN1 ID

N

0.20 R.

N

1

2

0.4ꢀ

0.80 DIA.

6.90

7.10

E-PAD

6.70

6.80

ꢀ.4ꢀ

ꢀ.ꢀꢀ

Y

0.30-0.4ꢀ

0.42 0.18

0°-12°

0.ꢀ0

(4X)

ꢀ.4ꢀ

ꢀ.ꢀꢀ

C

SEATING

PLANE

TOP VIEW

SIDE VIEW

BOTTOM VIEW

E-PAD SIZE PADDLE SIZE

(X, Y MAX.)

DIMENSIONS IN mm MIN.

MAX.

ꢀ.1 X ꢀ.1

3.8 X 3.8

ꢀ.3 X ꢀ.3

4.0 X 4.0

REFERENCE JEDEC MO-220

PKG. WEIGHT 0.13 gms

51-85152-*B

Figure 14-1. 48-pin Lead-Free QFN 7 × 7 mm LY48

The recommended dimension of the PCB pad size for the

E-PAD underneath the QFN is 209 mils × 209 mils (width x

length).

This document is subject to change, and may be found to contain errors of omission or changes in parameters. For feedback or

technical support regarding Cypress WirelessUSB products please contact Cypress at www.cypress.com. WirelessUSB, PSoC,

and enCoRe are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the

trademarks of their respective holders.

Document #: 38-16008 Rev. *C

Page 32 of 33

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CYWUSB6935

Document History Page

Document Title: CYWUSB6935 WirelessUSB LR™ 2.4-GHz DSSS Radio SoC

Document Number: 38-16008

Orig. of

REV.

**

*A

ECN NO. Issue Date Change

Description of Change

207428

275349

See ECN

TGE

ZTK

New data sheet

Updated REG_DATA_RATE (0x04), 111 - Not Valid

Changed AVCC annotation to VCC

Removed SOIC package option

Corrected Figure 3-1, Figure 6-1 and Figure 6-2

Updated ordering information section

Added Table 4-1 Internal PA Output Power Step Table

Corrected Figure 14-1 caption

Updated Radio Parameters

Added commercial temperature operating range in section 10

Updated average transmitter current consumption number

*B

*C

291015

335774

See ECN

ZTK

TGE

Added t_STABLE2parameter to Table 12-4 and Figure 12-6

Removed Addr 0x01 and 0x02–unused

Corrected Figure 6-1 - swap RFIN / RFOUT

Corrected REG_CONTROL - bit 1 description

Added Section 12.3 - Typical Operating Characteristics

Document #: 38-16008 Rev. *C

Page 33 of 33

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