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CYW255OXC

型号：

CYW255OXC

描述：

200 - MHz的24 -输出缓冲器4 DDR或3 SDRAM DIMM，[ 200-MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS ]

品牌：

CYPRESS[ CYPRESS ]

页数：

10 页

PDF大小：

256 K

下载PDF手册
W255  
200-MHz 24-Output Buffer for 4 DDR  
or 3 SDRAM DIMMS  
Features  
Functional Description  
• One input to 24-output buffer/driver  
• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS  
• One additional output for feedback  
• SMBus interface for individual output control  
• Low skew outputs (< 100 ps)  
• Supports 266-, 333-, and 400-MHz DDR SDRAM  
• Dedicated pin for power management support  
• Space-saving 48-pin SSOP package  
The W255 is a 3.3V/2.5V buffer designed to distribute  
high-speed clocks in PC applications. The part has 24 outputs.  
Designers can configure these outputs to support four unbuf-  
fered DDR DIMMS or to support three unbuffered standard  
SDRAM DIMMs and two DDR DIMMS. The W255 can be used  
in conjunction with the W250 or similar clock synthesizer for  
the VIA Pro 266 chipset.  
The W255 also includes an SMBus interface which can enable  
or disable each output clock. On power-up, all output clocks  
are enabled (internal pull up).  
Block Diagram  
Pin Configuration[1]  
FBOUT  
DDR0T_SDRAM10  
DDR0C_SDRAM11  
SSOP  
Top View  
BUF_IN  
1
2
3
4
5
6
7
8
FBOUT  
VDD3.3_2.5  
48  
47  
SEL_DDR*  
VDD2.5  
GND  
DDR1T_SDRAM0  
DDR1C_SDRAM1  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
GND  
DDR2T_SDRAM2  
DDR0T_SDRAM10  
DDR11T  
DDR11C  
DDR10T  
DDR10C  
VDD2.5  
GND  
DDR2C_SDRAM3 DDR0C_SDRAM11  
DRR1T_SDRAM0  
DDR3T_SDRAM4  
DDR1C_SDRAM1  
DDR3C_SDRAM5  
SDATA  
VDD3.3_2.5  
DDR4T_SDRAM6  
DDR4C_SDRAM7  
9
SMBus  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
DDR2T_SDRAM2  
DDR9T  
DDR9C  
VDD2.5  
PWR_DWN#*  
GND  
DDR8T  
DDR8C  
VDD2.5  
GND  
Decoding  
DDR5T_SDRAM8  
DDR2C_SDRAM3  
SCLOCK  
DDR5C_SDRAM9  
VDD3.3_2.5  
BUF_IN  
DDR6T  
GND  
DDR6C  
DDR3T_SDRAM4  
DDR7T  
DDR3C_SDRAM5  
DDR7C  
VDD3.3_2.5  
DDR8T  
DDR8C  
DDR9T  
GND  
DDR4T_SDRAM6  
DDR7T  
DDR7C  
DDR6T  
DDR6C  
GND  
DDR4C_SDRAM7  
DDR5T_SDRAM8  
DDR9C  
DDR5C_SDRAM9  
DDR10T  
DDR10C  
VDD3.3_2.5  
Power Down Control  
PWR_DWN#  
SEL_DDR  
SDATA  
SCLK  
Note:  
DDR11T  
1. Internal 100K pull-up resistors present on inputs marked  
with *. Design should not rely solely on internal pull-up resistor  
to set I/O pins HIGH.  
DDR11C  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-07255 Rev. *D  
Revised April 28, 2005  
W255  
Pin Summary  
Pin Name  
Pins  
Pin Description  
SEL_DDR  
48  
Input to configure for DDR-ONLY mode or STANDARD SDRAM  
mode.  
1 = DDR-ONLY mode.  
0 = STANDARD SDRAM mode.  
When SEL_DDR is pulled HIGH or configured for DDR-ONLY mode, pin  
4, 5, 6, 7, 10, 11,15, 16, 19, 20, 21, 22, 27, 28, 29, 30, 33, 34, 38, 39,  
42, 43, 44 and 45 will be configured as DDR outputs.  
Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode.  
When SEL_DDR is pulled LOW or configured for STANDARD SDRAM  
output, pin 4, 5, 6, 7, 10, 11, 15, 16, 19 and 20, 21, 22 will be configured  
as STANDARD SDRAM outputs.Pin 27, 28, 29, 30, 33, 34, 38, 39, 42,  
43, 44 and 45 will be configured as DDR outputs.  
Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM  
mode.  
SCLK  
SDATA  
BUF_IN  
25  
24  
13  
SMBus clock input  
SMBus data input  
Reference input from chipset. 2.5V input for DDR-ONLY mode; 3.3V  
input for STANDARD SDRAM mode.  
FBOUT  
1
Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V.  
PWR_DWN#  
36  
Active LOW input to enable power-down mode; all outputs will be  
pulled LOW.  
DDR[6:11]T  
DDR[6:11]C  
28, 30, 34, 39, 43, 45  
27, 29, 33, 38, 42, 44  
Clock outputs. These outputs provide copies of BUF_IN.  
Clock outputs. These outputs provide complementary copies of  
BUF_IN.  
DDR[0:5]T_SDRAM 4, 6, 10, 15, 19, 21  
[10,0,2,4,6,8]  
Clock outputs. These outputs provide copies of BUF_IN. Voltage swing  
depends on VDD3.3_2.5 power supply.  
DDR[0:5]C_SDRAM 5, 7, 11, 16, 20, 22  
[11,1,3,5,7,9]  
Clock outputs. These outputs provide complementary copies of  
BUF_IN when SEL_DDR is active. These outputs provide copies of  
BUF_IN when SEL_DDR is inactive. Voltage swing depends on  
VDD3.3_2.5 power supply.  
VDD3.3_2.5  
2, 8, 12, 17, 23  
32, 37, 41, 47  
Connect to 2.5V power supply when W255 is configured for  
DDR-ONLY mode. Connect to 3.3V power supply, when W255 is  
configured for standard SDRAM mode.  
2.5V voltage supply  
VDD2.5  
GND  
3, 9, 14, 18, 26, 31, 35, 40, 46 Ground  
Document #: 38-07255 Rev. *D  
Page 2 of 10  
W255  
Serial Configuration Map  
Byte 7: Outputs Active/Inactive Register  
(1 = Active, 0 = Inactive), Default = Active  
• The serial bits will be read by the clock driver in the following  
order:  
Bit  
Pin #  
Description  
DDR7T, DDR7C  
DDR6T, DDR6C  
DDR5T_SDRAM8,  
DDR5C_SDRAM9  
Default  
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0  
Bit 7 30, 29  
Bit 6 28, 27  
Bit 5 21, 22  
1
1
1
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0  
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0  
• Reserved and unused bits should be programmed to “0.”  
• SMBus Address for the W255 is:  
Bit 4 19, 20  
Bit 3 15,16  
Bit 2 10, 11  
Bit 1 6, 7  
DDR4T_SDRAM6,  
DDR4C_SDRAM7  
DDR3T_SDRAM4,  
DDR3C_SDRAM5  
DDR2T_SDRAM2,  
DDR2C_SDRAM3  
DDR1T_SDRAM0,  
DDR1C_SDRAM1  
1
1
1
1
1
A6  
A5  
A4  
A3  
A2  
A1  
A0  
R/W  
1
1
0
1
0
0
1
----  
Byte 6: Outputs Active/Inactive Register  
(1 = Active, 0 = Inactive), Default = Active  
Bit Pin #  
Description  
Reserved, drive to 0  
Reserved, drive to 0  
Reserved, drive to 0  
FBOUT  
Default  
Bit 0 4, 5  
DDR0T_SDRAM10,  
DDR0C_SDRAM11  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
–
–
–
1
0
0
0
1
1
1
1
1
Bit 3 45,44 DDR11T, DDR11C  
Bit 2 43, 42 DDR10T, DDR10C  
Bit 1 39, 38 DDR9T, DDR9C  
Bit 0 34, 33 DDR8T, DDR8C  
Document #: 38-07255 Rev. *D  
Page 3 of 10  
W255  
Storage Temperature.................................. –65°C to +150°C  
Maximum Ratings  
Supply Voltage to Ground Potential..................–0.5 to +7.0V  
DC Input Voltage (except BUF_IN)............–0.5V to VDD+0.5  
Static Discharge Voltage...........................................> 2000V  
(per MIL-STD-883, Method 3015)  
Operating Conditions[2]  
Parameter  
VDD3.3  
VDD2.5  
TA  
COUT  
CIN  
Description  
Min.  
3.135  
2.375  
0
Typ.  
Max.  
3.465  
2.625  
70  
Unit  
V
V
°C  
pF  
pF  
Supply Voltage  
Supply Voltage  
Operating Temperature (Ambient Temperature)  
Output Capacitance  
6
5
Input Capacitance  
Electrical Characteristics Over the Operating Range  
Parameter  
VIL  
VIH  
IIL  
IIH  
Description  
Input LOW Voltage  
Input HIGH Voltage  
Input LOW Current  
Input HIGH Current  
Output HIGH Current  
Test Conditions  
For all pins except SMBus  
Min.  
Typ.  
Max.  
0.8  
Unit  
V
V
µA  
µA  
mA  
2.0  
VIN = 0V  
VIN = VDD  
VDD = 2.375V  
VOUT = 1V  
50  
50  
IOH  
–18  
26  
–32  
35  
IOL  
Output LOW Current  
VDD = 2.375V  
mA  
V
OUT = 1.2V  
VOL  
VOH  
IDD  
Output LOW Voltage[3]  
Output HIGH Voltage[3]  
Supply Current[3]  
(DDR-only mode)  
IOL = 12 mA, VDD = 2.375V  
IOH = –12 mA, VDD = 2.375V  
Unloaded outputs, 133 MHz  
0.6  
V
V
mA  
1.7  
400  
500  
IDD  
Supply Current  
Loaded outputs, 133 MHz  
PWR_DWN# = 0  
mA  
(DDR-only mode)  
IDDS  
Supply Current  
100  
µA  
VOUT  
Output Voltage Swing  
See test circuity (refer to  
0.7  
VDD +0.6  
V
Figure 1)  
VOC  
Output Crossing Voltage  
(VDD/2) –  
0.1  
VDD/2  
(VDD/2) +  
0.1  
V
INDC  
Input Clock Duty Cycle  
48  
52  
%
[4]  
Switching Characteristics  
Parameter  
Name  
Operating Frequency  
Duty Cycle[3, 5] = t2 ÷ t1  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
–
–
66  
INDC  
5%  
200  
INDC  
5%  
MHz  
%
Measured at 1.4V for 3.3V outputs  
Measured at VDD/2 for 2.5V outputs  
Measured between 0.4V and 2.4V  
Measured between 2.4V and 0.4V  
–
+
t3  
t4  
t3d  
SDRAM Rising Edge Rate[3]  
SDRAM Falling Edge Rate[3]  
DDR Rising Edge Rate[3]  
1.0  
1.0  
0.5  
2.75  
2.75  
1.50  
V/ns  
V/ns  
V/ns  
Measured between 20% to 80% of  
output (refer to Figure 1)  
Notes:  
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.  
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.  
4. All parameters specified with loaded outputs.  
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.  
Document #: 38-07255 Rev. *D  
Page 4 of 10  
W255  
Switching Characteristics (continued)[4]  
Parameter  
Name  
Test Conditions  
Min.  
0.5  
Typ.  
Max.  
1.50  
Unit  
V/ns  
t4d  
DDR Falling Edge Rate[3]  
Measured between 20% to 80% of  
output (refer to Figure 1)  
t5  
t6  
Output to Output Skew for DDR[3] All outputs equally loaded  
100  
150  
ps  
ps  
Output to Output Skew for  
All outputs equally loaded  
SDRAM[3]  
t7  
t8  
SDRAM Buffer LH Prop. Delay[3] Input edge greater than 1 V/ns  
SDRAM Buffer HL Prop. Delay[3] Input edge greater than 1 V/ns  
5
5
10  
10  
ns  
ns  
Switching Waveforms  
Duty Cycle Timing  
t
1
t
2
All Outputs Rise/Fall Time  
3.3V  
0V  
2.4V  
0.4V  
2.4V  
0.4V  
OUTPUT  
t
3
t
4
Output-Output Skew  
OUTPUT  
OUTPUT  
t
5
SDRAM Buffer HH and LL Propagation Delay  
1.5V  
INPUT  
1.5V  
OUTPUT  
t6  
t7  
Document #: 38-07255 Rev. *D  
Page 5 of 10  
W255  
Figure 1 shows the differential clock directly terminated by a 120Ω resistor.  
VCC  
VCC  
VTR  
60W  
Device  
Under  
Test  
)
)
Out  
RT =120Ω  
60W  
Receiver  
Out  
VCP  
Figure 1. Differential Signal Using Direct Termination Resistor  
Ordering Information  
Ordering Code  
W255H  
Package Type  
Operating Range  
Commercial  
Commercial  
48-pin SSOP  
W255HT  
48-pin SSOP–Tape and Reel Option  
Lead-free  
CYW255OXC  
CYW255OXCT  
48-pin SSOP  
48-pin SSOP–Tape and Reel Option  
Commercial  
Commercial  
Document #: 38-07255 Rev. *D  
Page 6 of 10  
W255  
Layout Example for DDR 2.5V Only  
+2.5V Supply  
FB  
VDDQ2  
10 mF  
C40.005 mF  
C3  
G
G
1
G
V
48  
47  
46  
45  
V
G
G
G
2
3
4
G
5
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
6
7
8
9
G
G
G
G
V
G
V
G
G
G
10  
G
V
G
11 G  
V
12  
13 G  
G
14  
15  
G
16  
G
V
G
G
V
G
17  
G
18  
19  
20  
21  
G
28  
27  
26  
25  
G
22  
G
G
V
23  
G
24  
FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) or TDK ACB 2012L-120  
µF  
µF  
C4 = 0.005  
V = VIA to respective supply plane layer  
Ceramic Caps C3 = 10–22  
= VIA to GND plane layer  
G
Note: Each supply plane or strip should have a ferrite bead and capacitors  
All bypass caps = 0.1 µF ceramic  
Document #: 38-07255 Rev. *D  
Page 7 of 10  
W255  
Layout Example SDRAM (Mixed Voltage)  
+2.5V Supply  
FB  
+3.3V Supply  
FB  
VDDQ2  
VDDQ3  
10 mF  
0.005 mf  
10 mF  
C40.005 mF  
C1  
C2  
C3  
G
G
G
G
1
48  
47  
46  
45  
G
V
G
V
G
G
2
3
4
5
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
6
7
8
9
G
V
G
V
G
G
G
G
10  
11  
12  
G
G
V
G
V
G
G
13 G  
G
G
14  
15  
G
G
16  
V
G
V
17  
G
G
18  
19  
20  
21  
22  
G
28  
27  
26  
25  
G
G
V
23  
G
24  
FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) or TDK ACB 2012L-120  
µF  
µFC2 & C4 = 0.005  
C6 = 0.1 µF  
Ceramic Caps C1 and C3 = 10–22  
= VIA to GND plane layer  
V = VIA to respective supply plane layer  
G
Note: Each supply plane or strip should have a ferrite bead and capacitors  
All bypass caps = 0.1 µF ceramic  
Document #: 38-07255 Rev. *D  
Page 8 of 10  
W255  
Package Diagram  
48-lead Shrunk Small Outline Package O48  
51-85061-*C  
VIA is a trademark of VIA Technologies, Inc. All product and company names mentioned in this document are the trademarks of  
their respective holders.  
Document #: 38-07255 Rev. *D  
Page 9 of 10  
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
W255  
Document History Page  
Document Title: W255 200MHz 24 Output Buffer for 4 DDR or 3 SDRAM DIMMs  
Document Number: 38-07255  
Issue  
Date  
Orig. of  
Change  
SZV  
REV.  
**  
*A  
*B  
*C  
ECN NO.  
110520  
112154  
114554  
122857  
358457  
Description of Change  
Change from Spec number: 38-01082 to 38-07255  
Added 333 MHz for DDR SDRAM  
Added 400 MHz for DDR SDRAM  
Power up requirements added to Operating Conditions Information  
Added Lead-free devices  
12/04/01  
03/01/02  
05/07/02  
12/14/02  
See ECN  
IKA  
INA  
RBI  
RGL  
*D  
Document #: 38-07255 Rev. *D  
Page 10 of 10  
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