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CYW255OXC

型号：

CYW255OXC

描述：

200 MHz的24 -输出缓冲器4 DDR或3 SDRAM DIMM，[ 200 MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS ]

品牌：

SPECTRALINEAR[ SPECTRALINEAR INC ]

页数：

9 页

PDF大小：

196 K

下载PDF手册
W255  
200 MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS  
Features  
Functional Description  
• One input to 24 output buffer/driver  
The W255 is a 3.3V/2.5V buffer designed to distribute  
high-speed clocks in PC applications. The part has 24 outputs.  
Designers can configure these outputs to support four unbuf-  
fered DDR DIMMS or to support three unbuffered standard  
SDRAM DIMMs and two DDR DIMMS. The W255 can be used  
in conjunction with the W250 or similar clock synthesizer for  
the VIA Pro 266 chipset.  
• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS  
• One additional output for feedback  
• SMBus interface for individual output control  
• Low skew outputs (< 100 ps)  
• Supports 266-, 333-, and 400 MHz DDR SDRAM  
• Dedicated pin for power management support  
• Space-saving 48-pin SSOP package  
The W255 also includes an SMBus interface which can enable  
or disable each output clock. On power-up, all output clocks  
are enabled (internal pull up).  
Block Diagram  
Pin Configuration[1]  
FBOUT  
SSOP  
BUF_IN  
DDR0T_SDRAM10  
DDR0C_SDRAM11  
Top View  
1
FBOUT  
VDD3.3_2.5  
GND  
48  
47  
SEL_DDR*  
VDD2.5  
GND  
DDR1T_SDRAM0  
DDR1C_SDRAM1  
2
3
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
4
DDR2T_SDRAM2  
DDR0T_SDRAM10  
DDR2C_SDRAM3 DDR0C_SDRAM11  
DDR11T  
DDR11C  
DDR10T  
DDR10C  
VDD2.5  
GND  
DDR9T  
DDR9C  
VDD2.5  
PWR_DWN#*  
GND  
5
6
DRR1T_SDRAM0  
DDR3T_SDRAM4  
DDR1C_SDRAM1  
7
DDR3C_SDRAM5  
SDATA  
8
VDD3.3_2.5  
DDR4T_SDRAM6  
9
SMBus  
Decoding  
GND  
DDR2T_SDRAM2  
DDR2C_SDRAM3  
DDR4C_SDRAM7  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
DDR5T_SDRAM8  
DDR5C_SDRAM9  
VDD3.3_2.5  
SCLOCK  
BUF_IN  
DDR6T  
GND  
DDR6C  
DDR3T_SDRAM4  
DDR8T  
DDR8C  
DDR7T  
DDR3C_SDRAM5  
DDR7C  
VDD3.3_2.5  
VDD2.5  
GND  
DDR8T  
GND  
DDR4T_SDRAM6  
DDR4C_SDRAM7  
DDR5T_SDRAM8  
DDR5C_SDRAM9  
VDD3.3_2.5  
SDATA  
DDR8C  
DDR7T  
DDR7C  
DDR6T  
DDR6C  
GND  
DDR9T  
DDR9C  
DDR10T  
Power Down Control  
PWR_DWN#  
SCLK  
DDR10C  
Note:  
DDR11T  
1. Internal 100K pull-up resistors present on inputs marked  
with *. Design should not rely solely on internal pull-up resistor  
to set I/O pins HIGH.  
DDR11C  
SEL_DDR  
Rev 1.0, November 25, 2006  
Page 1 of 9  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  
W255  
Pin Summary  
Pin Name  
Pins  
Pin Description  
SEL_DDR  
48  
Input to configure for DDR-ONLY mode or STANDARD SDRAM  
mode.  
1 = DDR-ONLY mode.  
0 = STANDARD SDRAM mode.  
When SEL_DDR is pulled HIGH or configured for DDR-ONLY mode, pin  
4, 5, 6, 7, 10, 11,15, 16, 19, 20, 21, 22, 27, 28, 29, 30, 33, 34, 38, 39,  
42, 43, 44 and 45 will be configured as DDR outputs.  
Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode.  
When SEL_DDR is pulled LOW or configured for STANDARD SDRAM  
output, pin 4, 5, 6, 7, 10, 11, 15, 16, 19 and 20, 21, 22 will be configured  
as STANDARD SDRAM outputs.Pin 27, 28, 29, 30, 33, 34, 38, 39, 42,  
43, 44 and 45 will be configured as DDR outputs.  
Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM  
mode.  
SCLK  
25  
24  
13  
SMBus clock input  
SMBus data input  
SDATA  
BUF_IN  
Reference input from chipset. 2.5V input for DDR-ONLY mode; 3.3V  
input for STANDARD SDRAM mode.  
FBOUT  
1
Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V.  
PWR_DWN#  
36  
Active LOW input to enable power-down mode; all outputs will be  
pulled LOW.  
DDR[6:11]T  
DDR[6:11]C  
28, 30, 34, 39, 43, 45  
27, 29, 33, 38, 42, 44  
Clock outputs. These outputs provide copies of BUF_IN.  
Clock outputs. These outputs provide complementary copies of  
BUF_IN.  
DDR[0:5]T_SDRAM 4, 6, 10, 15, 19, 21  
[10,0,2,4,6,8]  
Clock outputs. These outputs provide copies of BUF_IN. Voltage swing  
depends on VDD3.3_2.5 power supply.  
DDR[0:5]C_SDRAM 5, 7, 11, 16, 20, 22  
[11,1,3,5,7,9]  
Clock outputs. These outputs provide complementary copies of  
BUF_IN when SEL_DDR is active. These outputs provide copies of  
BUF_IN when SEL_DDR is inactive. Voltage swing depends on  
VDD3.3_2.5 power supply.  
VDD3.3_2.5  
2, 8, 12, 17, 23  
32, 37, 41, 47  
Connect to 2.5V power supply when W255 is configured for  
DDR-ONLY mode. Connect to 3.3V power supply, when W255 is  
configured for standard SDRAM mode.  
VDD2.5  
GND  
2.5V voltage supply  
3, 9, 14, 18, 26, 31, 35, 40, 46 Ground  
Rev 1.0,November 25, 2006  
Page 2 of 9  
W255  
Serial Configuration Map  
Byte 7: Outputs Active/Inactive Register  
(1 = Active, 0 = Inactive), Default = Active  
• The serial bits will be read by the clock driver in the following  
order:  
Bit  
Pin #  
Description  
DDR7T, DDR7C  
Default  
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0  
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0  
Bit 7 30, 29  
Bit 6 28, 27  
Bit 5 21, 22  
1
1
1
.
DDR6T, DDR6C  
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0  
DDR5T_SDRAM8,  
DDR5C_SDRAM9  
• Reserved and unused bits should be programmed to “0.”  
• SMBus Address for the W255 is:  
Bit 4 19, 20  
Bit 3 15,16  
Bit 2 10, 11  
Bit 1 6, 7  
DDR4T_SDRAM6,  
DDR4C_SDRAM7  
1
1
1
1
1
Table 1.  
DDR3T_SDRAM4,  
DDR3C_SDRAM5  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
R/W  
DDR2T_SDRAM2,  
DDR2C_SDRAM3  
1
1
0
1
0
0
1
----  
DDR1T_SDRAM0,  
DDR1C_SDRAM1  
Byte 6: Outputs Active/Inactive Register  
(1 = Active, 0 = Inactive), Default = Active  
Bit 0 4, 5  
DDR0T_SDRAM10,  
DDR0C_SDRAM11  
Bit Pin #  
Description  
Reserved, drive to 0  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
–
–
–
1
0
0
0
1
1
1
1
1
Reserved, drive to 0  
Reserved, drive to 0  
FBOUT  
Bit 3 45,44 DDR11T, DDR11C  
Bit 2 43, 42 DDR10T, DDR10C  
Bit 1 39, 38 DDR9T, DDR9C  
Bit 0 34, 33 DDR8T, DDR8C  
Rev 1.0,November 25, 2006  
Page 3 of 9  
W255  
Storage Temperature...................................–65°C to +150°C  
Maximum Ratings  
Static Discharge Voltage .......................................... > 2000V  
(per MIL-STD-883, Method 3015)  
Supply Voltage to Ground Potential..................–0.5 to +7.0V  
DC Input Voltage (except BUF_IN)............ –0.5V to VDD+0.5  
Operating Conditions[2]  
Parameter  
VDD3.3  
Description  
Min.  
3.135  
2.375  
0
Typ.  
Max.  
3.465  
2.625  
70  
Unit  
V
Supply Voltage  
Supply Voltage  
VDD2.5  
TA  
V
Operating Temperature (Ambient Temperature)  
Output Capacitance  
°C  
pF  
pF  
COUT  
CIN  
6
5
Input Capacitance  
Electrical Characteristics Over the Operating Range  
Parameter  
VIL  
Description  
Input LOW Voltage  
Input HIGH Voltage  
Input LOW Current  
Input HIGH Current  
Output HIGH Current  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
V
For all pins except SMBus  
0.8  
VIH  
IIL  
2.0  
V
VIN = 0V  
50  
50  
PA  
PA  
mA  
IIH  
VIN = VDD  
IOH  
VDD = 2.375V  
VOUT = 1V  
–18  
26  
–32  
35  
IOL  
Output LOW Current  
VDD = 2.375V  
VOUT = 1.2V  
mA  
VOL  
VOH  
IDD  
Output LOW Voltage[3]  
Output HIGH Voltage[3]  
IOL = 12 mA, VDD = 2.375V  
IOH = –12 mA, VDD = 2.375V  
Unloaded outputs, 133 MHz  
0.6  
V
V
1.7  
Supply Current[3]  
(DDR-only mode)  
400  
500  
mA  
IDD  
Supply Current  
(DDR-only mode)  
Loaded outputs, 133 MHz  
PWR_DWN# = 0  
mA  
IDDS  
Supply Current  
100  
PA  
VOUT  
Output Voltage Swing  
See test circuity (refer to  
Figure 1)  
0.7  
VDD +0.6  
V
VOC  
Output Crossing Voltage  
(VDD/2) –  
0.1  
VDD/2  
(VDD/2) +  
0.1  
V
INDC  
Input Clock Duty Cycle  
48  
52  
%
[4]  
Switching Characteristics  
Parameter  
Name  
Operating Frequency  
Duty Cycle[3, 5] = t2 yꢀt1  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
–
–
66  
200  
MHz  
%
Measured at 1.4V for 3.3V outputs  
Measured at VDD/2 for 2.5V outputs  
INDC  
5%  
–
INDC  
5%  
+
t3  
SDRAM Rising Edge Rate[3]  
SDRAM Falling Edge Rate[3]  
DDR Rising Edge Rate[3]  
Measured between 0.4V and 2.4V  
Measured between 2.4V and 0.4V  
1.0  
1.0  
0.5  
2.75  
2.75  
1.50  
V/ns  
V/ns  
V/ns  
t4  
t3d  
Measured between 20% to 80% of  
output (refer to Figure 1)  
Notes:  
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.  
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.  
4. All parameters specified with loaded outputs.  
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.  
Rev 1.0,November 25, 2006  
Page 4 of 9  
W255  
Switching Characteristics (continued)[4]  
Parameter  
Name  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
t4d  
DDR Falling Edge Rate[3]  
Measured between 20% to 80% of  
output (refer to Figure 1)  
0.5  
1.50  
V/ns  
t5  
t6  
Output to Output Skew for DDR[3] All outputs equally loaded  
100  
150  
ps  
ps  
Output to Output Skew for  
SDRAM[3]  
All outputs equally loaded  
t7  
t8  
SDRAM Buffer LH Prop. Delay[3] Input edge greater than 1 V/ns  
SDRAM Buffer HL Prop. Delay[3] Input edge greater than 1 V/ns  
5
5
10  
10  
ns  
ns  
Switching Waveforms  
Duty Cycle Timing  
t
1
t
2
All Outputs Rise/Fall Time  
3.3V  
0V  
2.4V  
2.4V  
0.4V  
OUTPUT  
0.4V  
t
3
t
4
Output-Output Skew  
OUTPUT  
OUTPUT  
t
5
SDRAM Buffer HH and LL Propagation Delay  
1.5V  
INPUT  
1.5V  
OUTPUT  
t6  
t7  
Rev 1.0,November 25, 2006  
Page 5 of 9  
W255  
Figure 1 shows the differential clock directly terminated by a 120:ꢀresistor.  
VCC  
VCC  
VTR  
60W  
Device  
Under  
Test  
)
Out  
RT =120:  
60W  
Receiver  
Out  
)
VCP  
Figure 1. Differential Signal Using Direct Termination Resistor  
Rev 1.0,November 25, 2006  
Page 6 of 9  
W255  
Layout Example for DDR 2.5V Only  
+2.5V Supply  
FB  
VDDQ2  
0.005 mF 10 mF  
C3  
C4  
G
G
1
G
V
48  
47  
46  
45  
V
G
G
2
3
4
G
G
5
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
6
7
8
9
G
G
G
V
V
G
G
G
10  
11  
12  
G
V
G
V
G
G
G
13 G  
14  
G
15  
16  
17  
18  
19  
20  
21  
22  
23  
G
G
V
G
V
G
G
G
G
28  
27  
26  
25  
G
G
G
V
G
24  
FB = Dale ILB1206 - 300 (300:ꢀ@ 100 MHz) or TDK ACB 2012L-120  
PF  
PF  
C4 = 0.005  
V = VIA to respective supply plane layer  
Ceramic Caps C3 = 10–22  
= VIA to GND plane layer  
G
Note: Each supply plane or strip should have a ferrite bead and capacitors  
All bypass caps = 0.1ꢀPF ceramic  
Rev 1.0,November 25, 2006  
Page 7 of 9  
W255  
Layout Example SDRAM (Mixed Voltage)  
+2.5V Supply  
FB  
+3.3V Supply  
FB  
VDDQ2  
VDDQ3  
10 mF  
0.005 mf  
10 mF  
C40.005 mF  
C1  
C2  
C3  
G
G
G
G
1
48  
47  
46  
45  
G
V
G
V
G
2
3
4
G
5
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
6
7
8
9
G
V
G
G
V
G
G
10  
11  
12  
G
G
V
G
V
G
13 G  
G
G
G
G
14  
15  
16  
G
V
G
V
G
17  
18 G  
19  
G
G
20  
21  
22  
23  
28  
27  
26  
25  
G
G
V
G
24  
FB = Dale ILB1206 - 300 (300:ꢀ@ 100 MHz) or TDK ACB 2012L-120  
PF  
PFC2 & C4 = 0.005  
C6 = 0.1ꢀPF  
Ceramic Caps C1 and C3 = 10–22  
= VIA to GND plane layer  
V = VIA to respective supply plane layer  
G
Note: Each supply plane or strip should have a ferrite bead and capacitors  
All bypass caps = 0.1ꢀPF ceramic  
Rev 1.0,November 25, 2006  
Page 8 of 9  
W255  
Ordering Information  
Ordering Code  
W255H  
Package Type  
Operating Range  
Commercial  
48-pin SSOP  
W255HT  
48-pin SSOP–Tape and Reel Option  
Commercial  
Lead-free  
CYW255OXC  
CYW255OXCT  
48-pin SSOP  
Commercial  
Commercial  
48-pin SSOP–Tape and Reel Option  
Package Drawing and Dimensions  
48-lead Shrunk Small Outline Package O48  
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-  
cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in  
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-  
tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional  
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any  
circuitry or specification without notice.  
Rev 1.0, November 25, 2006  
Page 9 of 9  
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