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CYW311OXCT

型号：

CYW311OXCT

描述：

FTG的VIA ™PRO -266 DDR芯片组[ FTG for VIA⑩ Pro-266 DDR Chipset ]

品牌：

CYPRESS[ CYPRESS ]

页数：

19 页

PDF大小：

372 K

下载PDF手册
W311  
FTG for VIA™ Pro-266 DDR Chipset  
• Supports Intel® Celeron® and Pentium® III class  
Features  
processor  
• Maximized EMI Suppression using Cypress’s Spread  
• Three copies of CPU output  
• Nine copies of PCI output  
• One 48-MHz output for USB  
• One 24-MHz or 48-MHz output for SIO  
• Two buffered reference outputs  
• Three copies of APIC output  
• Supports frequencies up to 200MHz  
• SMBus Interface for programming  
• Power management control inputs  
• Available in 48-pin SSOP  
Spectrum Technology  
• System frequency synthesizer for VIA Pro-2000  
• Programmable clock output frequency with less than 1  
MHz increment  
• Integrated fail-safe Watchdog Timer for system  
recovery  
• Automatically switch to HW selected or SW  
programmed clock frequency when Watchdog Timer  
time-out  
• Capable of generate system RESET after a Watchdog  
Timer time-out occurs or a change in output frequency  
via SMBus interface  
Key Specifications  
• Support SMBus byte read/write and block read/ write  
operations to simplify system BIOS development  
CPU Cycle-to-cycle Jitter: ..........................................250 ps  
CPU to CPU Output Skew...........................................175 ps  
PCI Cycle-to-cycle Jitter:.............................................500 ps  
PCI to PCI Output Skew:.............................................500 ps  
• Vendor ID and Revision ID support  
• Programmable drive strength for CPU and PCI output  
clocks  
• ProgrammableoutputskewbetweenCPU, AGPandPCI  
Block Diagram  
Pin Configuration[1]  
Note:  
1. Signals marked with * have internal pull-up resistors  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-07703 Rev. **  
Revised March 14, 2005  
W311  
Pin Definitions  
Pin  
Pin Name  
Pin No.  
Type  
Pin Description  
RST#  
32  
O
System Reset Output: Open-drain system reset output.  
CPU1:3  
39, 38, 35  
(open CPU Clock Output: Frequency is set by the FS0:4 input or through serial input  
drain) interface. The CPU1:3 outputs are gated by the CLK_STOP# input.  
O
CPU_STOP#  
PCI1:8  
34  
I
O
CPU Output Control: 3.3V LVTTL-compatible input that stop CPU1:3.  
PCI Clock Outputs 1 through 8: Frequency is set by FS0:4 inputs or through  
serial input interface; see Table 5 for details. PCI1:8 outputs are gated by the  
PCI_STOP# input.  
10, 11, 13,  
14, 16, 17,  
18, 20  
PCI_STOP#  
PCI_F  
33  
9
O
O
PCI_STOP# Input: 3.3V LVTTL-compatible input that stops PCI1:8.  
Free-Running PCI Clock Output: Frequency is set by FS0:4 inputs or through  
serial input interface; see Table 5 for details.  
FS0:1  
21, 22  
I
Frequency Selection Inputs: Selects CPU clock frequency as shown in Table 1.  
AGP Clock Output: This pin serves as the select strap to determine device  
operating frequency as described in Table 5.  
AGP0:2  
23, 26, 27  
O
APIC0:2  
45, 44, 42  
6
O
APIC Clock Output: APIC clock outputs.  
48MHz/FS3  
I/O  
48-MHz Output/Frequency Select 3: 48 MHz is provided in normal operation.  
In standard PC systems, this output can be used as the reference for the Universal  
Serial Bus host controller. This pin also serves as a power-on strap option to  
determine device operating frequency as described in Table 5.  
24_48MHz/  
FS2  
7
I/O  
I/O  
24_48-MHz Output/Frequency Select 2: In standard PC systems, this output  
can be used as the clock input for a Super I/O chip. The output frequency is  
controlled by Configuration Byte 3 bit[6]. The default output frequency is 24 MHz.  
This pin also serves as a power-on strap option to determine device operating  
frequency as described in Table 5.  
47  
REF1/FS4  
Reference Clock Output 1/Frequency Select 4: 3.3V 14.318-MHz output clock.  
This pin also serves as a power-on strap option to determine device operating  
frequency as described in Table 5.  
REF0  
SCLK  
SDATA  
X1  
48  
28  
29  
3
O
I
I/O  
I
Reference Clock Output 0: 3.3V 14.318-MHz output clock.  
Clock pin for SMBus circuitry.  
Data pin for SMBus circuitry.  
Crystal Connection or External Reference Frequency Input: This pin has dual  
functions. It can be used as an external 14.318-MHz crystal connection or as an  
external reference frequency input.  
X2  
41  
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If  
using an external reference, this pin must be left unconnected.  
VDD_REF,  
VDD_48MHz,  
VDD_PCI,  
1, 5,15, 24,  
31  
Power Connection: Power supply for core logic, PLL circuitry, PCI outputs,  
P
reference outputs, 48-MHz output, and 24-48 MHz output, connect to 3.3V supply.  
VDD_AGP,  
VDD_CORE  
VDD_CPU,  
VDD_APIC  
41, 46, 37  
P
Power Connection: Power supply for APIC and CPU output buffers, connect to  
2.5V.  
Document #: 38-07703 Rev. **  
Page 2 of 19  
W311  
Serial Data Interface  
The W311 features a two-pin, serial data interface that can be  
used to configure internal register settings that control  
particular device functions.  
controller. For block write/read operation, the bytes must be  
accessed in sequential order from lowest to highest byte with  
the ability to stop after any complete byte has been trans-  
ferred. For byte/word write and byte read operations, system  
controller can access individual indexed byte. The offset of the  
indexed byte is encoded in the command code.  
Data Protocol  
The definition for the command code is defined in Table 2.  
The clock driver serial protocol supports byte/word write,  
byte/word read, block write and block read operations from the  
Table 1.  
Bit  
Descriptions  
7
0 = Block read or block write operation  
1 = Byte/Word read or byte/word write operation  
6:0  
Byte offset for byte/word read or write operation. For block read or write operations, these bits  
need to be set at ‘0000000’.  
Table 2. Block Read and Block Write Protocol  
Block Write Protocol  
Block Read Protocol  
Description  
Bit  
1
Description  
Bit  
1
Start  
Start  
2:8  
9
Slave address – 7 bits  
Write  
2:8  
9
Slave address – 7 bits  
Write  
10  
Acknowledge from slave  
10  
Acknowledge from slave  
11:18  
Command Code – 8 bits  
11:18  
Command Code – 8 bits  
‘00000000’ stands for block operation  
‘00000000’ stands for block operation  
19  
20:27  
28  
29:36  
37  
38:45  
46  
...  
Acknowledge from slave  
Byte Count – 8 bits  
Acknowledge from slave  
Data byte 0 – 8 bits  
Acknowledge from slave  
Data byte 1 – 8 bits  
Acknowledge from slave  
Data Byte N/Slave Acknowledge...  
Data Byte N – 8 bits  
Acknowledge from slave  
Stop  
19  
20  
21:27  
28  
29  
30:37  
38  
39:46  
47  
48:55  
56  
Acknowledge from slave  
Repeat start  
Slave address – 7 bits  
Read  
Acknowledge from slave  
Byte count from slave – 8 bits  
Acknowledge  
Data byte from slave – 8 bits  
Acknowledge  
...  
...  
...  
Data byte from slave – 8 bits  
Acknowledge  
...  
...  
...  
Data bytes from slave/Acknowledge  
Data byte N from slave – 8 bits  
Not Acknowledge  
...  
Stop  
Document #: 38-07703 Rev. **  
Page 3 of 19  
W311  
Table 3. Word Read and Word Write Protocol  
Word Write Protocol  
Word Read Protocol  
Description  
Bit  
1
Description  
Bit  
1
Start  
Start  
2:8  
9
Slave address – 7 bits  
Write  
2:8  
9
Slave address – 7 bits  
Write  
10  
11:18  
Acknowledge from slave  
10  
11:18  
Acknowledge from slave  
Command Code – 8 bits  
Command Code – 8 bits  
‘1xxxxxxx’ stands for byte or word operation  
bit[6:0] of the command code represents the  
offset of the byte to be accessed  
‘1xxxxxxx’ stands for byte or word operation  
bit[6:0] of the command code represents the  
offset of the byte to be accessed  
19  
20:27  
28  
29:36  
37  
Acknowledge from slave  
Data byte low – 8 bits  
Acknowledge from slave  
Data byte high –- 8 bits  
Acknowledge from slave  
Stop  
19  
20  
21:27  
28  
29  
30:37  
38  
Acknowledge from slave  
Repeat start  
Slave address – 7 bits  
Read  
Acknowledge from slave  
Data byte low from slave – 8 bits  
Acknowledge  
38  
39:46  
47  
48  
Data byte high from slave – 8 bits  
NOT acknowledge  
Stop  
Table 4. Byte Read and Byte Write Protocol  
Byte Write Protocol  
Byte Read Protocol  
Description  
Bit  
1
Description  
Bit  
1
Start  
Start  
2:8  
9
Slave address – 7 bits  
Write  
2:8  
9
Slave address – 7 bits  
Write  
10  
Acknowledge from slave  
10  
Acknowledge from slave  
11:18  
Command Code – 8 bits  
11:18  
Command Code – 8 bits  
‘1xxxxxxx’ stands for byte operation  
bit[6:0] of the command code represents the  
offset of the byte to be accessed  
‘1xxxxxxx’ stands for byte operation  
bit[6:0] of the command code represents the  
offset of the byte to be accessed  
19  
20:27  
28  
Acknowledge from slave  
Data byte – 8 bits  
Acknowledge from slave  
Stop  
19  
20  
21:27  
28  
Acknowledge from slave  
Repeat start  
Slave address – 7 bits  
Read  
29  
29  
30:37  
38  
Acknowledge from slave  
Data byte from slave – 8 bits  
Not Acknowledge  
Stop  
39  
Document #: 38-07703 Rev. **  
Page 4 of 19  
W311  
2. All unused register bits (reserved and N/A) should be  
W311 Serial Configuration Map  
written to a “0” level.  
1. The serial bits will be read by the clock driver in the following  
3. All register bits labeled “Initialize to 0" must be written to  
order:  
zero during initialization.  
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0  
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0  
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0  
Byte 0: Control Register 0  
Bit  
Pin#  
–
Name  
Reserved  
Default  
0
Description  
Bit 7  
Reserved  
Bit 6  
Bit 5  
Bit 4  
–
–
–
SEL2  
SEL1  
SEL0  
0
0
0
See Table 5  
See Table 5  
See Table 5  
Bit 3  
–
FS_Override  
0
0 = Select operating frequency by FS[4:0] input pins  
1 = Select operating frequency by SEL[4:0] settings  
Bit 2  
Bit 1  
Bit 0  
–
–
–
SEL4  
SEL3  
Reserved  
1
0
0
See Table 5  
See Table 5  
Reserved  
Byte 1: Control Register 1  
Bit  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Pin#  
Name  
Reserved  
Spread Select2  
Spread Select1  
Spread Select0  
Default  
Description  
-
-
-
-
0
0
0
0
Reserved  
‘000’ = Normal (spread off)  
‘001’ = Test Mode  
‘010’ = Reserved  
‘011’ = Three-Stated  
‘100’ = –0.5%  
‘101’ = ± 0.5%  
‘110’ = ± 0.25%  
‘111’ = ± 0.38%  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
35  
38  
39  
42  
CPU3  
CPU2  
CPU1  
APIC2  
1
1
1
1
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
Byte 2: Control Register 2  
Bit Pin#  
Name  
PC8  
PCI7  
PCI6  
PCI5  
PCI4  
PCI3  
PCI2  
PCI1  
Default  
Description  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
20  
18  
17  
16  
14  
13  
11  
10  
1
1
1
1
1
1
1
1
Document #: 38-07703 Rev. **  
Page 5 of 19  
W311  
Byte 3: Control Register  
Bit  
Bit 7  
Bit 6  
Pin#  
--  
7
Name  
Reserved  
SEL_48MHz  
Default  
Description  
0
0
Reserved  
0 = Select 24 MHz as output  
1 = Select 48 MHz as output (default).  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
6
7
9
27  
26  
23  
48MHz  
24_48MHz  
PCI_F  
AGP2  
AGP1  
1
1
1
1
1
1
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
AGP0  
Byte 4: Watchdog Timer Register  
Bit  
Pin#  
Name  
Default  
Description  
Bit 7  
-
PCI_Skew1  
0
PCI skew control  
00 = Normal  
01 = –500 ps  
10 = Reserved  
11 = +500 ps  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
-
PCI_Skew0  
0
These bits store the time-out value of the Watchdog  
Timer. The scale of the timer is determine by the pre  
scaler.  
-
-
-
-
WD_TIMER4  
WD_TIMER3  
WD_TIMER2  
WD_TIMER1  
1
1
1
1
The timer can support a value of 150 ms to 4.8 sec  
when the pre-scalar is set to 150 ms. If the pre-scaler  
is set to 2.5 sec, it can support a value from 2.5 sec  
to 80 sec.  
When the Watchdog Timer reaches to “0”, it will set  
the WD_To_STATUS bit and generate Reset if  
RST_EN_WD is enabled  
Bit 0  
-
WD_TIMER0  
1
0 = 150 ms  
1 = 2.5 sec  
Byte 5: Control Register 5  
Bit  
Pin#  
6
7
44  
45  
-
-
47  
48  
Name  
48Mhz_DRV  
24_48MHz_DRV  
APIC1  
Default  
Description  
0 = Norm, 1 = High Drive  
0 = Norm, 1 = High Drive  
(Active/Inactive)  
(Active/Inactive)  
Reserved  
Reserved  
(Active/Inactive)  
(Active/Inactive)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
1
1
1
1
0
0
1
1
APIC0  
Reserved  
Reserved  
REF1  
REF0  
Document #: 38-07703 Rev. **  
Page 6 of 19  
W311  
Byte 6: Reserved Register  
Bit  
Name  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Default  
Pin Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
1
1
1
1
1
1
1
1
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Byte 7: Reserved Register  
Bit Name  
Default  
Pin Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
1
1
1
1
1
1
1
1
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Byte 8: Vendor ID and Revision ID Register (Read Only)  
Bit  
Name  
Revision_ID3  
Revision_ID2  
Revision_ID1  
Revision_ID0  
Vendor_ID3  
Vendor_ID2  
Vendor _ID1  
Vendor _ID0  
Default  
Pin Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
1
0
0
0
Revision ID bit[3]  
Revision ID bit[2]  
Revision ID bit[1]  
Revision ID bit[0]  
Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only.  
Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only.  
Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only.  
Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only.  
Document #: 38-07703 Rev. **  
Page 7 of 19  
W311  
Byte 9: System Reset and Watchdog Timer Register  
Bit  
Name  
Reserved  
PCI_DRV  
Default  
Pin Description  
Bit 7  
Bit 6  
0
0
Reserved  
PCI clock output drive strength  
0 = Normal  
1 = High Drive  
Bit 5  
Bit 4  
Reserved  
RST_EN_WD  
0
0
Reserved  
This bit will enable the generation of a Reset pulse when a watchdog timer  
time-out occurs.  
0 = Disabled  
1 = Enabled  
Bit 3  
RST_EN_FC  
0
This bit will enable the generation of a Reset pulse after a frequency change  
occurs.  
0 = Disabled  
1 = Enabled  
Bit 2  
Bit 1  
WD_TO_STATU  
S
0
0
Watchdog Timer Time-out Status bit  
0 = No time-out occurs (READ); Ignore (WRITE)  
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)  
WD_EN  
0 = Stop and re-load Watchdog Timer  
1 = Enable Watchdog Timer. It will start counting down after a frequency  
change occurs.  
Note: W311 will generate system reset, reload a recovery frequency, and lock  
itself into a recovery frequency mode after a watchdog timer time-out occurs.  
Under recovery frequency mode, W311 will not respond to any attempt to  
change output frequency via the SMBus control bytes. System software can  
unlock W311 from its recovery frequency mode by clearing the WD_EN bit.  
Bit 0  
Reserved  
0
Reserved  
Byte 10: Skew Control Register  
Bit  
Name  
CPU_Skew2  
CPU_Skew1  
CPU_Skew0  
Default  
Description  
Bit 7  
Bit 6  
Bit 5  
0
0
0
CPU skew control  
000 = Normal  
001 = –150 ps  
010 = –300 ps  
011 = –450 ps  
100 = +150 ps  
101 = +300 ps  
110 = +450 ps  
111 = +600 ps  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
AGP_Skew1  
AGP_Skew0  
0
0
0
0
0
Reserved  
Reserved  
Reserved  
AGP skew control  
00 = Normal  
01 = –150 ps  
10 = +150 ps  
11 = +300 ps  
Document #: 38-07703 Rev. **  
Page 8 of 19  
W311  
Byte 11: Recovery Frequency N - Value Register  
Bit  
Name  
Default  
Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
ROCV_FREQ_N7  
ROCV_FREQ_N6  
ROCV_FREQ_N5  
ROCV_FREQ_N4  
ROCV_FREQ_N3  
ROCV_FREQ_N2  
ROCV_FREQ_N1  
ROCV_FREQ_N0  
0
0
0
0
0
0
0
0
If ROCV_FREQ_SEL is set, W311 will use the values programmed in  
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery  
CPU output frequency.when a Watchdog Timer time-out occurs.  
The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM,  
AGP and SDRAM. When it is cleared, W311 will use the same frequency ratio  
stated in the Latched FS[4:0] register. When it is set, W311 will use the  
frequency ratio stated in the SEL[4:0] register.  
W312 supports programmable CPU frequency ranging from 50 MHz to 248  
MHz.  
W311 will change the output frequency whenever there is an update to either  
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended  
to use Word or Block write to update both registers within the same SMBus bus  
operation.  
Byte 12: Recovery Frequency M- Value Register  
Bit  
Name  
Default  
Pin Description  
Bit 7  
ROCV_FREQ_SEL  
0
ROCV_FREQ_SEL determines the source of the recover frequency when a  
Watchdog Timer time-out occurs. The clock generator will automatically  
switch to the recovery CPU frequency based on the selection on  
ROCV_FREQ_SEL.  
0 = From latched FS[4:0]  
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
ROCV_FREQ_M6  
ROCV_FREQ_M5  
ROCV_FREQ_M4  
ROCV_FREQ_M3  
ROCV_FREQ_M2  
ROCV_FREQ_M1  
ROCV_FREQ_M0  
0
0
0
0
0
0
0
If ROCV_FREQ_SEL is set, W311 will use the values programmed in  
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery  
CPU output frequency.when a Watchdog Timer time-out occurs.The setting  
of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and  
SDRAM. When it is cleared, W311 will use the same frequency ratio stated in  
the Latched FS[4:0] register. When it is set, W311 will use the frequency ratio  
stated in the SEL[4:0] register. W311 supports programmable CPU frequency  
ranging from 50 MHz to 248 MHz.  
Byte 13: Programmable Frequency Select N-Value Register  
Bit  
Name  
Default  
Pin Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
CPU_FSEL_N7  
CPU_FSEL_N6  
CPU_FSEL_N5  
CPU_FSEL_N4  
CPU_FSEL_N3  
CPU_FSEL_N2  
CPU_FSEL_N1  
CPU_FSEL_N0  
0
0
0
0
0
0
0
0
If Prog_Freq_EN is set, W311 will use the values programmed in  
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output  
frequency. The new frequency will start to load whenever CPU_FSELM[6:0]  
is updated.  
The setting of FS_Override bit determines the frequency ratio for CPU,  
SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same  
frequency ratio stated in the Latched FS[4:0] register. When it is set, W311  
will use the frequency ratio stated in the SEL[4:0] register. W311 supports  
programmable CPU frequency ranging from 50 MHz to 248 MHz.  
Document #: 38-07703 Rev. **  
Page 9 of 19  
W311  
Byte 14: Programmable Frequency Select N-Value Register  
Bit  
Name  
Default  
Description  
Bit 7  
Pro_Freq_EN  
0
Programmable output frequencies enabled  
0 = disabled  
1 = enabled  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
CPU_FSEL_M6  
CPU_FSEL_M5  
CPU_FSEL_M4  
CPU_FSEL_M3  
CPU_FSEL_M2  
CPU_FSEL_M1  
CPU_FSEL_M0  
0
0
0
0
0
0
0
If Prog_Freq_EN is set, W311 will use the values programmed in  
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output  
frequency. The new frequency will start to load whenever CPU_FSELM[6:0]  
is updated.  
The setting of FS_Override bit determines the frequency ratio for CPU,  
SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same  
frequency ratio stated in the Latched FS[4:0] register. When it is set, W311  
will use the frequency ratio stated in the SEL[4:0] register.  
Byte 15: Reserved Register  
Bit Pin#  
Name  
Default  
Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
47  
6
7
21  
22  
-
Latched FS4 input  
Latched FS3 input  
Latched FS2 input  
Latched FS1 input  
Latched FS0 input  
Vendor test mode  
Vendor test mode  
Vendor test mode  
X
X
X
X
X
0
Latched FS[4:0] inputs. These bits are read only.  
Reserved. Write with ‘0’  
Reserved. Write with ‘1’  
Reserved. Write with ‘1’  
-
-
1
1
Byte 16: Reserved Register  
Bit Pin#  
Name  
Default  
Description  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
-
-
-
-
-
-
-
-
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
0
0
0
0
0
0
0
0
Byte 17: Reserved Register  
Bit  
Pin#  
Name  
Default  
Description  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
-
-
-
-
-
-
-
-
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
0
0
0
0
0
0
0
0
Document #: 38-07703 Rev. **  
Page 10 of 19  
W311  
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes  
Input Conditions  
Output Frequency  
PLL Gear  
FS4  
SEL4  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS3  
SEL3  
0
FS2  
SEL2  
0
FS1  
SEL1  
0
FS0  
SEL0  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Constants  
(G)  
CPU  
200.0  
190.0  
180.0  
170.0  
166.0  
160.0  
150.0  
145.0  
140.0  
136.0  
130.0  
124.0  
66.6  
100.0  
118.0  
133.3  
66.8  
100.2  
115.0  
133.6  
66.8  
100.2  
110.0  
133.6  
105.0  
90.0  
85.0  
78.0  
66.6  
100.0  
75.0  
3V66  
66.6  
76.0  
72.0  
68.0  
66.4  
64.0  
75.0  
72.5  
70.0  
68.0  
65.0  
62.0  
66.6  
66.6  
78.7  
66.6  
66.8  
66.8  
76.7  
66.8  
66.8  
66.8  
73.3  
66.8  
70.0  
60.0  
56.7  
78.0  
66.6  
66.6  
75.0  
66.6  
PCI  
33.3  
38.0  
36.0  
34.0  
33.2  
32.0  
37.5  
36.3  
35.0  
34.0  
32.5  
31.0  
33.3  
33.3  
39.3  
33.3  
33.4  
33.4  
38.3  
33.4  
33.4  
33.4  
36.7  
33.4  
35.0  
30.0  
28.3  
39.0  
33.3  
33.3  
37.5  
33.3  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
48.00741  
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
133.3  
Programmable Output Frequency, Watchdog Timer and  
Recovery Output Frequency Functional Description  
The Programmable Output Frequency feature allows users to  
generate any CPU output frequency from the range of 50 MHz  
to 248 MHz. Cypress offers the most dynamic and the simplest  
programming interface for system developers to utilize this  
feature in their platforms.  
The Watchdog Timer and Recovery Output Frequency  
features allow users to implement a recovery mechanism  
when the system hangs or getting unstable. System BIOS or  
other control software can enable the Watchdog timer before  
they attempt to make a frequency change. If the system hangs  
and a Watchdog timer time-out occurs, a system reset will be  
generated and a recovery frequency will be activated.  
All of the related registers are summarized inTable 7.  
Document #: 38-07703 Rev. **  
Page 11 of 19  
W311  
Table 6. Register Summary  
Name  
Description  
Pro_Freq_EN  
Programmable output frequencies enabled  
0 = Disabled (default)  
1 = Enabled  
When it is disabled, the operating output frequency will be determined by either the latched value of  
FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs  
will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used.  
When it is enabled, the CPU output frequency will be determined by the programmed value of  
CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0]  
or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between  
CPU and other frequency outputs.  
FS_Override  
When Pro_Freq_EN is cleared or disabled,  
0 = Select operating frequency by FS input pins (default)  
1 = Select operating frequency by SEL bits in SMBus control bytes  
When Pro_Freq_EN is set or enabled,  
0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are  
based on the latched value of FS input pins (default)  
1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are  
based on the programmed value of SEL bits in SMBus control bytes  
CPU_FSEL_N,  
CPU_FSEL_M  
When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and  
CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load  
whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recom-  
mended to use Word or Block write to update both registers within the same SMBus bus operation.  
The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PCI. When  
FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins.  
When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in  
SMBus control bytes.  
ROCV_FREQ_SEL  
ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer timeout  
occurs. The clock generator will automatically switch to the recovery CPU frequency based on the  
selection on ROCV_FREQ_SEL.  
0 = From latched FS[4:0]  
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]  
ROCV_FREQ_N[7:0], When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and  
ROCV_FREQ_M[6:0] ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog  
Timer time-out occurs  
The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PCI. When it is cleared,  
the same frequency ratio stated in the Latched FS[4:0] register will be used.  
When it is set, the frequency ratio stated in the SEL[4:0] register will be used.  
The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and  
ROCV_FREQ_M[6:0]. Therefore, it is recommended to use word or block write to update both registers  
within the same SMBus bus operation.  
WD_EN  
0 = Stop and reload Watchdog Timer  
1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs.  
Pro_Freq_EN  
Programmable output frequencies enabled  
0 = Disabled (default)  
1 = Enabled  
When it is disabled, the operating output frequency will be determined by either the latched value of  
FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs  
will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used.  
When it is enabled, the CPU output frequency will be determined by the programmed value of  
CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0]  
or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between  
CPU and other frequency outputs.  
Document #: 38-07703 Rev. **  
Page 12 of 19  
W311  
Table 6. Register Summary (continued)  
Name  
Description  
FS_Override  
When Pro_Freq_EN is cleared or disabled,  
0 = Select operating frequency by FS input pins (default)  
1 = Select operating frequency by SEL bits in SMBus control bytes  
When Pro_Freq_EN is set or enabled,  
0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are  
based on the latched value of FS input pins (default)  
1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are  
based on the programmed value of SEL bits in SMBus control bytes  
CPU_FSEL_N,  
CPU_FSEL_M  
When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and  
CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load  
whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recom-  
mended to use Word or Block write to update both registers within the same SMBus bus operation.  
The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PCI. When  
FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins.  
When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in  
SMBus control bytes.  
ROCV_FREQ_SEL  
ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer timeout  
occurs. The clock generator will automatically switch to the recovery CPU frequency based on the  
selection on ROCV_FREQ_SEL.  
0 = From latched FS[4:0]  
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]  
WD_PRE_SCALER  
RST_EN_WD  
0 = 150 ms  
1 = 2.5 sec  
This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs.  
0 = Disabled  
1 = Enabled  
RST_EN_FC  
This bit will enable the generation of a Reset pulse after a frequency change occurs.  
0 = Disabled  
1 = Enabled  
How to Program CPU Output Frequency  
When the programmable output frequency feature is enabled  
(Pro_Freq_EN bit is set), the CPU output frequency is deter-  
mined by the following equation:  
“G” stands for the PLL Gear Constant, which is determined by  
the programmed value of FS[4:0] or SEL[4:0]. The value is  
listed in Table 5. The ratio of (N+3) and (M+3) need to be  
greater than “1” [(N+3)/(M+3) > 1].  
Table 7 lists set of N and M values for different frequency  
output ranges.This example use a fixed value for the M-Value  
Register and select the CPU output frequency by changing the  
value of the N-Value Register.  
Fcpu = G * (N+3)/(M+3)  
“N” and “M” are the values programmed in Programmable  
Frequency Select N-Value Register and M-Value Register,  
respectively.  
Table 7. Examples of N and M Value for Different CPU Frequency Range  
Fixed Value for  
Range of N-Value Register  
for Different CPU Frequency  
Frequency Ranges  
50 MHz–129 MHz  
130 MHz–248 MHz  
Gear Constants  
48.00741  
M-Value Register  
93  
97–255  
127–245  
48.00741  
45  
Document #: 38-07703 Rev. **  
Page 13 of 19  
W311  
Absolute Maximum Ratings[2]  
Stresses greater than those listed in this table may cause  
permanent damage to the device. These represent a stress  
tions above those specified in the operating sections of this  
specification is not implied. Maximum conditions for extended  
periods may affect reliability.  
rating only. Operation of the device at these or any other condi-  
.
Parameter  
DD, VIN  
TSTG  
TB  
TA  
ESDPROT  
Description  
Voltage on any pin with respect to GND  
Storage Temperature  
Ambient Temperature under Bias  
Operating Temperature  
Rating  
–0.5 to +7.0  
–65 to +150  
–55 to +125  
0 to +70  
Unit  
V
°C  
°C  
°C  
kV  
V
Input ESD Protection  
2 (min.)  
DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% and 2.5V±5%  
Parameter  
Description  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
Supply Current  
IDD  
IDD  
Logic Inputs  
3.3V Supply Current  
2.5V Supply Current  
CPU [1:3]=133 MHz[3]  
–
–
260  
25  
–
–
mA  
mA  
VIL  
VIH  
IIL  
Input Low Voltage  
Input High Voltage  
Input Low Current[4]  
Input High Current[4]  
GND – 0.3  
–
–
–
–
0.8  
VDD + 0.3  
–25  
V
V
µA  
µA  
2.0  
–
–
IIH  
10  
Clock Outputs  
VOL  
VOH  
VOH  
Output Low Voltage  
Output High Voltage  
Output Low Voltage CPUT[1:3]  
APIC[0:2]  
IOL = 1 mA  
IOH = –1 mA  
IOH = –1 mA  
–
3.1  
2.2  
–
–
–
50  
–
–
mV  
V
V
IOL  
Output Low Current CPU1:3  
VOL = 1.25V  
VOL = 1.5V  
VOL = 1.25V  
VOL = 1.25V  
VOL = 1.5V  
VOL = 1.5V  
VOL = 1.5V  
VOH = 1.25V  
VOH = 1.5V  
VOL = 1.25V  
VOH = 1.5V  
VOH = 1.5V  
VOH = 1.5V  
27  
20.5  
40  
40  
25  
25  
25  
25  
31  
40  
27  
27  
25  
57  
53  
85  
85  
37  
37  
37  
55  
55  
85  
44  
44  
37  
97  
139  
140  
140  
76  
76  
76  
97  
139  
140  
94  
94  
76  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
PCI_F, PCI1:8  
AGP0:2  
APIC0:2  
REF0:1  
48-MHz  
24-MHz  
IOH  
Output High Current CPU1:3  
PCI_F, PCI1:8  
AGP0:2  
APIC0:1  
48-MHz  
24-MHz  
Notes:  
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.  
3. All clock outputs loaded with 6" 60Ω transmission lines with 22-pF capacitors.  
4. Inputs have internal pull-up resistors  
Document #: 38-07703 Rev. **  
Page 14 of 19  
W311  
DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% and 2.5V±5% (continued)  
Parameter  
Description  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
Crystal Oscillator  
VTH  
CLOAD  
X1 Input Threshold Voltage[5]  
VDD = 3.3V  
–
–
1.65  
18  
–
–
V
pF  
Load Capacitance, Imposed on  
External Crystal[6]  
CIN,X1  
X1 Input Capacitance[7]  
Pin X2 unconnected  
Except X1 and X2  
–
28  
–
pF  
Pin Capacitance/Inductance  
CIN Input Pin Capacitance  
COUT  
LIN  
–
–
–
–
–
–
5
6
7
pF  
pF  
nH  
Output Pin Capacitance  
Input Pin Inductance  
AC Electrical Characteristics  
TA = 0°C to +70°C, VDD = 3.3V±5%, VDD = 2.5V±5%fXTL = 14.31818 MHz  
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the  
clock output; Spread Spectrum is disabled.  
CPU Clock Outputs (Lump Capacitance Test Load = 20 pF)  
CPU = 66.6 MHz CPU = 100 MHz CPU = 133 MHz  
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit  
Test Condition  
Parameter  
tP  
Description  
Period  
/Comments  
Measuredonrisingedgeat 15  
–
–
–
–
–
–
–
15.5 10  
–
–
–
–
–
–
–
10.5 7.5  
–
–
–
–
–
–
–
8.0  
ns  
1.25  
tH  
tL  
High Time  
Low Time  
Duration of clock cycle  
above 2.0V  
Duration of clock cycle  
below 0.4V  
Measured from 0.4V to  
2.0V  
5.2  
5.0  
1
–
–
3.0  
2.8  
1
–
–
1.87  
1.67  
1
–
ns  
–
ns  
tR  
tF  
Output Rise Edge  
Rate  
Output Fall Edge  
Rate  
4
4
4
V/ns  
V/ns  
%
Measured from 2.0V to  
0.4V  
1
4
1
4
1
4
tD  
tJC  
Duty Cycle  
Measured on rising and  
falling edge at 1.25V  
45  
–
55  
250  
45  
–
55  
250  
45  
–
55  
250  
Jitter,  
Measuredonrisingedgeat  
1.25V. Maximum  
ps  
Cycle-to-Cycle  
difference of cycle time  
between two adjacent  
cycles.  
tSK  
fST  
Output Skew  
Measuredonrisingedgeat  
1.25V  
–
–
–
–
175  
3
–
–
–
–
175  
3
–
–
–
–
175  
3
ps  
Frequency  
Assumes full supply  
ms  
Stabilization from  
voltage reached within  
Power-up (cold start) 1 ms from power-up. Short  
cycles exist prior to  
frequency stabilization.  
Zo  
AC Output  
Impedance  
Average value during  
switching transition. Used  
for determining series  
termination value.  
–
20  
–
–
20  
–
–
20  
–
Ω
Notes:  
5. X1 input threshold voltage (typical) is 3.3V/2  
6. The W311 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF;  
this includes typical stray capacitance of short PCB traces to crystal.  
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).  
Document #: 38-07703 Rev. **  
Page 15 of 19  
W311  
PCI Clock Outputs (Lump Capacitance Test Load = 30 pF)  
Parameter  
Description  
Period  
High Time  
Test Condition/Comments  
Measured on rising edge at 1.5V  
Duration of clock cycle above 2.4V  
Duration of clock cycle below 0.4V  
Measured from 0.4V to 2.4V  
Min.  
30  
12  
12  
1
1
45  
–
Typ.  
–
–
–
–
–
–
–
Max.  
–
–
–
4
4
55  
500  
Unit  
ns  
ns  
tP  
tH  
tL  
tR  
tF  
Low Time  
ns  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
V/ns  
V/ns  
%
Measured from 2.4V to 0.4V  
Measured on rising and falling edge at 1.5V  
tD  
tJC  
Jitter, Cycle-to-Cycle  
Measured on rising edge at 1.5V. Maximum  
ps  
difference of cycle time between two adjacent cycles.  
tSK  
tO  
Output Skew  
Measured on rising edge at 1.5V  
–
1.5  
–
–
500  
4
ps  
ns  
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising  
edge at 1.5V. CPU leads PCI output.  
fST  
Frequency Stabilization  
from Power-up (cold  
start)  
Assumes full supply voltage reached within 1 ms  
from power-up. Short cycles exist prior to frequency  
stabilization.  
Average value during switching transition. Used for  
determining series termination value.  
–
–
–
3
–
ms  
Zo  
AC Output Impedance  
30  
Ω
AGP Clock Outputs (Lump Capacitance Test Load = 30 pF)  
Parameter  
Description  
Test Condition/Comments  
Measured on rising edge at 1.5V  
Duration of clock cycle above 2.4V  
Duration of clock cycle below 0.4V  
Measured from 0.4V to 2.4V  
Measured from 2.4V to 0.4V  
Measured on rising and falling edge at 1.5V  
Measured on rising edge at 1.5V. Maximum  
difference of cycle time between two adjacent  
cycles.  
Min.  
Typ.  
–
–
–
–
–
–
–
Max. Unit  
tP  
tH  
tL  
tR  
tF  
Period  
15  
5.25  
5.05  
1
1
45  
–
–
–
ns  
ns  
High Time  
Low Time  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
–
ns  
4
4
55  
500  
V/ns  
V/ns  
%
tD  
tJC  
Jitter, Cycle-to-Cycle  
ps  
tSK  
fST  
Output Skew  
Measured on rising edge at 1.5V  
–
–
–
–
250  
3
ps  
ms  
FrequencyStabilizationfrom Assumes full supply voltage reached within  
Power-up (cold start)  
AC Output Impedance  
1 ms from power-up. Short cycles exist prior to  
frequency stabilization.  
Average value during switching transition. Used  
for determining series termination value.  
Zo  
–
30  
–
Ω
APIC Clock Output (Lump Capacitance Test Load = 20 pF)  
Parameter  
f
tR  
tF  
tD  
fST  
Description  
Frequency, Actual  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
Test Condition/Comments  
Frequency generated from PCI divided by 2  
Measured from 0.4V to 2.4V  
Measured from 2.4V to 0.4V  
Measured on rising and falling edge at 1.5V  
Assumes full supply voltage reached within 1 ms  
Min.  
Typ.  
PCI/2  
Max. Unit  
MHz  
0.5  
0.5  
45  
2
2
55  
3
V/ns  
V/ns  
%
Frequency Stabilization  
ms  
from Power-up (cold start) from power-up. Short cycles exist prior to  
frequency stabilization.  
Zo  
AC Output Impedance  
Average value during switching transition. Used  
for determining series termination value.  
40  
Ω
Document #: 38-07703 Rev. **  
Page 16 of 19  
W311  
REF Clock Output (Lump Capacitance Test Load = 20 pF)  
Parameter  
f
tR  
tF  
tD  
fST  
Description  
Frequency, Actual  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
Test Condition/Comments  
Frequency generated by crystal oscillator  
Measured from 0.4V to 2.4V  
Measured from 2.4V to 0.4V  
Measured on rising and falling edge at 1.5V  
Assumes full supply voltage reached within 1 ms  
Min.  
Typ.  
14.318  
Max. Unit  
MHz  
0.5  
0.5  
45  
–
–
–
–
–
2
2
55  
3
V/ns  
V/ns  
%
Frequency Stabilization  
ms  
from Power-up (cold start) from power-up. Short cycles exist prior to  
frequency stabilization.  
Zo  
AC Output Impedance  
Average value during switching transition. Used  
for determining series termination value.  
–
40  
–
Ω
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)  
Parameter  
f
fD  
m/n  
tR  
tF  
tD  
fST  
Description  
Frequency, Actual  
Deviation from 48 MHz  
PLL Ratio  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
Test Condition/Comments  
Determined by PLL divider ratio (see m/n below)  
(48.008 – 48)/48  
(14.31818 MHz x 57/17 = 48.008 MHz)  
Measured from 0.4V to 2.4V  
Measured from 2.4V to 0.4V  
Measured on rising and falling edge at 1.5V  
Assumes full supply voltage reached within 1 ms  
Min.  
Typ.  
48.008  
+167  
57/17  
Max. Unit  
MHz  
ppm  
0.5  
0.5  
45  
–
–
–
–
–
2
2
55  
3
V/ns  
V/ns  
%
Frequency Stabilization  
ms  
from Power-up (cold start) from power-up. Short cycles exist prior to  
frequency stabilization.  
Zo  
AC Output Impedance  
Average value during switching transition. Used  
for determining series termination value.  
–
40  
–
Ω
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)  
Parameter  
f
fD  
m/n  
tR  
tF  
tD  
fST  
Description  
Frequency, Actual  
Deviation from 24 MHz  
PLL Ratio  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
Test Condition/Comments  
Determined by PLL divider ratio (see m/n below)  
(24.004 – 24)/24  
(14.31818 MHz x 57/34 = 24.004 MHz)  
Measured from 0.4V to 2.4V  
Measured from 2.4V to 0.4V  
Measured on rising and falling edge at 1.5V  
Assumes full supply voltage reached within 1 ms  
Min.  
Typ.  
24.004  
+167  
57/34  
Max. Unit  
MHz  
ppm  
0.5  
0.5  
45  
–
–
–
–
–
2
2
55  
3
V/ns  
V/ns  
%
Frequency Stabilization  
ms  
from Power-up (cold start) from power-up. Short cycles exist prior to  
frequency stabilization.  
Zo  
AC Output Impedance  
Average value during switching transition. Used  
for determining series termination value.  
–
40  
–a  
Ω
Ordering Information  
Ordering Code  
W311H  
Package Type  
Product Flow  
Commercial, 0°C to 70°C  
48-pin SSOP  
W311HT  
48-pin SSOP - Tape and Reel  
Commercial, 0°C to 70°C  
Lead-free  
CYW311OXC  
CYW311OXCT  
48-pin SSOP  
48-pin SSOP - Tape and Reel  
Commercial, 0°C to 70°C  
Commercial, 0°C to 70°C  
Document #: 38-07703 Rev. **  
Page 17 of 19  
W311  
Package Drawing and Dimension  
48-Lead Shrunk Small Outline Package O48  
51-85061-*C  
Intel, Pentium, and Celeron are registered trademarks of Intel Corporation. VIA is a trademark of VIA Technologies, Inc. All product  
and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-07703 Rev. **  
Page 18 of 19  
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
W311  
Document History Page  
Document Title: W311 FTG for VIA™ Pro-266 DDR Chipset  
Document Number: 38-07703  
Orig. of  
REV.  
ECN NO. Issue Date Change  
Description of Change  
**  
334735  
See ECN  
RGL  
New Data sheet  
Document #: 38-07703 Rev. **  
Page 19 of 19  
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