W320-03
ability to stop after any complete byte has been transferred.
Serial Data Interface (SMBus)
Indexed bytes are not allowed.
To enhance the flexibility and function of the clock synthesizer,
a two signal SMBus interface is provided according to the
SMBus specification. Through the Serial Data Interface (SDI),
various device functions such as individual clock output
buffers, etc can be individually enabled or disabled. W320-03
support both block read and block write operations.
The registers associated with the SDI initialize to their default
setting upon power-up, and therefore use of this interface is
optional. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power
management functions.
A block write begins with a slave address and a WRITE
condition. The R/W bit is used by the SMBus controller as a
data direction bit. A zero indicates a WRITE condition to the
clock device. The slave receiver address is 11010010 (D2h).
A command code of 0000 0000 (00h) and the byte count bytes
are required for any transfer. After the command code, the
core logic issues a byte count which describes number of
additional bytes required for the transfer, not including the
command code and byte count bytes. For example, if the host
has 20 data bytes to send, the first byte would be the number
20 (14h), followed by the 20 bytes of data. The byte count byte
is required to be a minimum of one byte and a maximum of 32
bytes It may not be 0. Figure 1 shows an example of a block
write.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte, (most significant bit first) with the
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller.
Start Slave Address R/W
bit 1 1 0 1 0 0 1 0 0/1
A
1
Command
Code
A ByteCount= A Data Byte 0
N
A
1
. . .
Data Byte N-1 A Stop
bit
0 0 0 0 0 0 0 0
1 bit
7 bits
1
8 bits
1
8 bits
1
8 bits
8 bits
1
1 bit
From Master to Slave
From Slave to Master
Figure 1. An Example of a Block Write
Data Byte Configuration Map
Data Byte 0: Control Register (0 = Enable, 1 = Disable)
Power On
Default
Bit
Affected Pin#
Name
Description
Type
Bit 7
5, 6, 7, 10, 11, PCI [0:6]
Spread Spectrum Enable
R/W
0
12, 13, 16, 17, CPU[2:0]
0 = Spread Off, 1 = Spread On
18, 33, 35
–
3V66[1:0]
TBD
Bit 6
Bit 5
TBD
R
R/W
0
0
35
3V66_1/VCH
VCH Select 66 MHz/48 MHz
0 = 66 MHz, 1 = 48 MHz
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
44, 45, 48, 49, CPU [2:0]
51, 52 CPU# [2:0]
CPU_STOP#
R
N/A
N/A
N/A
N/A
N/A
Reflects the current value of the external CPU_STOP# pin
10, 11, 12, 13, PCI [6:0]
PCI_STOP#
R/W
R
16, 17, 18
(Does not affect PCI_F [2:0] pins)
–
–
–
–
–
–
S2
Reflects the value of the S2 pin sampled on Power-up
S1
R
Reflects the value of the S1 pin sampled on Power-up
S0
R
Reflects the value of the S1 pin sampled on Power-up
Document #: 38-07248 Rev. *C
Page 4 of 18
