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CYW2338

型号：

CYW2338

描述：

双串行输入锁相环与2.5和1.1 - GHz的预分频器[ Dual Serial Input PLL with 2.5- and 1.1-GHz Prescalers ]

品牌：

CYPRESS[ CYPRESS ]

页数：

12 页

PDF大小：

254 K

下载PDF手册
12338\CYW2338  
PRELIMINARY  
CYW2338  
Dual Serial Input PLL with 2.5- and 1.1-GHz Prescalers  
Features  
Applications  
• Operating voltage 2.7V to 5.5V  
• Operating frequency to 2.5 GHz on PLL1 and 1.1 GHz  
on PLL2 with prescaler ratios of 64/65 and 128/129  
The Cypress CYW2338 is a dual serial input PLL frequency  
synthesizer designed for high performance dual conversion  
TV, VCR, and Set-top tuner sections, as well as downstream  
receivers for cable modems. The CYW2338 is also well suited  
for high-volume, low-cost wireless communications applica-  
tions. One 2.5-GHz and 1.1-GHz prescaler, each with pulse  
swallow capability are included. The device operates from  
2.7V and dissipates only 27 mW.  
• Lock detect feature  
µA typical at 3.0V  
• Power-down mode ICC < 1  
• Serial data input accepts data clock rates as low as  
1 kHz  
• Low power/voltage operation with low current standby  
mode  
• On-chip reference oscillator  
• Available in a 20-pin TSSOP (Thin Shrink Small Outline  
Package)  
• Available in a 24-pin CSP (Chip Scale Package)  
• Available in a 20-pin MLF  
(Mirco Lead Frame Package)  
Dual PLL Block Diagram  
GND (4)  
GND (7)  
VCC1 (1)  
VCC2 (20)  
VP1 (2)  
FIN1 (5)  
Prescaler  
64/65 or  
128/129  
fp1  
Binary 7-Bit  
Swallow Counter  
Binary 11-Bit  
Programmable Counter  
DOPLL1 (3)  
Phase  
Detector  
Charge  
Pump  
FIN1# (6)  
19-Bit  
Latch  
Pwr-dwn  
PLL1  
OSC_IN (8)  
fr fp  
fr1  
fr2  
15-Bit  
Monitor  
Output  
Selector  
Reference Counter  
OSC_OUT (9)  
FO/LD (10)  
20-Bit Latch  
Latch  
Selector  
LE (13)  
DATA (12)  
20-Bit Latch  
Power  
Control  
15-Bit  
Reference Counter  
22-Bit  
Shift  
Cntrl  
Reg.  
CLOCK (11)  
19-Bit  
Latch  
Pwr-dwn  
PLL2  
Phase  
Detector  
Charge  
Pump  
F
IN2 (16)  
Prescaler  
64/65 or  
128/129  
Binary 4-Bit  
Swallow Counter  
Binary 11-Bit  
Programmable Counter  
DOPLL2 (18)  
fp2  
FIN2# (15)  
GND (14)  
GND (17)  
VP2 (19)  
Pin Configuration  
V
1
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
2
CC  
21  
20  
1
CC  
NC  
NC  
V 1  
V 2  
P
2
3
4
5
6
7
8
9
DoPLL2  
Vp1  
DoPLL1  
GND  
P
19  
18  
17  
16  
15  
14  
13  
GND  
Fin2  
Fin2#  
GND  
LE  
D PLL1  
3
D PLL2  
O
O
1
2
3
4
5
15  
14  
DoPLL1  
GND  
GND  
Fin2  
Fin2#  
GND  
LE  
GND  
4
GND  
(Top View)  
Fin1  
F
1
5
F
F
2
IN  
IN  
IN  
(Top View)  
13  
12  
11  
Fin1  
Fin1#  
GND  
F
1#  
6
2#  
Fin1#  
GND  
IN  
GND  
OSC_IN  
7
GND  
LE  
DATA  
NC  
OSC_IN  
NC  
8
OSC_OUT  
9
DATA  
CLOCK  
F /LD  
10  
O
CSP  
MLF  
TSSOP  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
February 6, 2001, rev. **  
PRELIMINARY  
CYW2338  
Pin Definitions  
Pin  
No.  
(TSSOP)  
Pin  
No.  
(CSP)  
Pin  
No.  
Pin  
Type  
Pin Name  
(MLF)  
Pin Description  
V
CC1  
1
2
3
24  
19  
20  
1
P
P
O
Power Supply Connection for PLL1 and PLL2: When pow-  
er is removed from both the VCC1 and VCC2 pins, all latched  
data is lost.  
VP1  
2
PLL1 Charge Pump Rail Voltage: This voltage accommo-  
dates VCO circuits with tuning voltages higher than the VCC  
of PLL1.  
DOPLL1  
3
PLL1 Charge Pump Output: The phase detector gain is  
IP/2π. Sense polarity can be reversed by setting the FC bit in  
software (via the Shift Register).  
FIN1  
5
6
5
6
3
4
I
I
Input to PLL1 Prescaler: Maximum frequency 2.5 GHz.  
FIN1#  
Complementary Input to PLL1 Prescaler: A bypass capac-  
itor should be placed as close as possible to this pin and must  
be connected directly to the ground plane.  
OSC_IN  
8
8
6
I
Oscillator Input: This input has a VCC/2 threshold and CMOS  
logic level sensitivity.  
OSC_OUT  
FO/LD  
9
10  
11  
7
8
O
O
Oscillator Output  
10  
Lock Detect Pin of PLL1 Section: This output is HIGH when  
the loop is locked. It is multiplexed to the output of the pro-  
grammable counters or reference dividers in the test program  
mode. (Refer to Table 3 for configuration.)  
CLOCK  
11  
12  
9
I
Data Clock Input: One bit of data is loaded into the Shift  
Register on the rising edge of this signal.  
DATA  
LE  
12  
13  
14  
15  
10  
11  
I
I
Serial Data Input  
Load Enable: On the risingedge of this signal, thedatastored  
in the Shift Register is latched into the reference counter and  
configuration controls, PLL1 or PLL2 depending on the state  
of the control bits.  
FIN2#  
15  
17  
13  
I
Complementary Input to PLL2 Prescaler: A bypass capac-  
itor should be placed as close as possible to this pin and must  
be connected directly to the ground plane.  
FIN2  
16  
18  
18  
20  
14  
16  
I
Input to PLL2 Prescaler: Maximum frequency 1.1 GHz.  
DOPLL2  
O
PLL2 Charge Pump Output: The phase detector gain is  
IP/2π. Sense polarity can be reversed by setting the FC bit in  
software (via the Shift Register).  
VP2  
19  
20  
22  
23  
17  
18  
P
P
PLL2 Charge Pump Rail Voltage: This voltage accommo-  
dates VCO circuits with tuning voltages higher than the VCC  
of PLL2.  
VCC  
2
Power Supply Connections for PLL1 and PLL2: When  
power is removed from both the VCC1 and VCC2 pins, all  
latched data is lost.  
GND  
N/C  
4, 7, 14,  
17  
4,7,16, 2,5,12,  
G
Analog and Digital Ground Connections: This pin must be  
grounded.  
19  
15  
N/A  
1,9,13,  
21  
N/A  
N/C  
No Connect.  
2
PRELIMINARY  
CYW2338  
only. Operation of the device at these or any other conditions  
above those specified in the operating sections of this specifi-  
cation is not implied. Maximum conditions for extended peri-  
ods may affect reliability.  
Absolute Maximum Ratings  
Stresses greater than those listed in this table may cause per-  
manent damage to the device. These represent a stress rating  
Parameter  
VCC or VP  
VOUT  
Description  
Power Supply Voltage  
Rating  
–0.5 to +6.5  
–0.5 to VCC+0.5  
±15  
Unit  
V
Output Voltage  
V
IOUT  
Output Current  
mA  
°C  
°C  
TL  
Lead Temperature  
Storage Temperature  
+260  
TSTG  
–55 to +150  
Always turn off power before adding or removing devices from  
system.  
Handling Precautions  
Devices should be transported and stored in antistatic con-  
tainers.  
Protect leads with a conductive sheet when handling or trans-  
porting PC boards with devices.  
These devices are static sensitive. Ensure that equipment and  
personnel contacting the devices are properly grounded.  
If devices are removed from the moisture protective bags for  
more than 36 hours, they should be baked at 85°C in a mois-  
ture free environment for 24 hours prior to assembly in less  
than 24 hours.  
Cover workbenches with grounded conductive mats.  
Recommended Operating Conditions  
Parameter  
Description  
Power Supply Voltage  
Test Condition  
Rating  
Unit  
VCC1  
,
2.7 to 5.5  
V
VCC2  
VP  
TA  
Charge Pump Voltage  
Operating Temperature  
VCC to +5.5  
–40 to +85  
V
Ambient air at 0 CFM flow  
°C  
3
PRELIMINARY  
CYW2338  
Electrical Characteristics: VCC = VP = 2.7V to 5.5V, TA = –40°C to +85°C, Unless otherwise specified  
Parameter  
Description  
Test Condition  
Pin  
Min.  
Typ.  
Max.  
Unit  
ICC  
Power Supply Current  
PLL1 + PLL2  
VCC1 = VCC2 = 3.0V  
VCC1,  
10  
mA  
VCC  
VCC1,  
VCC  
2
µA  
IPD  
Power-down Current  
Power-down, VCC = 3.0V  
1
25  
2
FIN1  
FIN2  
FOSC  
Operating Frequency  
PLL1  
PLL2  
FIN1  
100  
45  
5
2500  
1100  
45  
25  
10  
4
MHz  
MHz  
MHz  
MHz  
MHz  
dBm  
dBm  
dBm  
VP–P  
µA  
FIN2  
Oscillator Input Frequency No load on OSC_OUT  
With OSC_OUT loaded  
OSC_IN  
5
Fφ  
Phase Detector Frequency  
PFIN1  
Input Sensitivity  
VCC = 2.7V  
FIN1  
–15  
–10  
–10  
0.5  
VCC = 5.5V  
4
PFIN2  
VOSC  
IIH, IIL  
VCC = 2.7V to 5.5V  
VCC = 3.0V  
FIN2  
4
Oscillator Input Sensitivity  
OSC_IN  
High/Low Level Input  
Current  
-100  
100  
V
CC = 3.0V  
VIH  
High Level Input Voltage  
Low Level Input Voltage  
High Level Input Current  
Low Level Input Current  
High level Output Voltage  
Low Level Output Voltage  
IDO High, Source Current  
IDO Low, Source Current  
IDO High, Sink Current  
IDO Low, Sink Current  
DATA,  
CLOCK,  
LE  
VCC * 0.8  
V
V
VIL  
VCC * 0.2  
µA  
µA  
V
IIH  
–10  
–10  
0.5  
0.5  
10  
10  
IIL  
VOH  
VCC = 3.0V, IOH = -1 mA  
VCC = 3.0V, IOL = 1 mA  
FO/LD  
VCC * 0.8  
VOL  
VCC * 0.2  
V
IDOH(SO)  
IDOL(SO)  
IDOH(SI)  
IDOL(SI)  
∆IDO  
VCC = VP = 3.0V,  
DO = VP/2  
DOPLL1  
DOPLL2  
–3.8  
–1  
3.8  
1
mA  
mA  
mA  
mA  
%
IDO Charge Pump Sink and VCC = VP = 3.0V,  
3
15  
Source Mismatch  
[IIDO(SI)I – IIDO(SO)I]/  
[1/2*{IIDO(SI)]I+IIDO(SO)I}]*100%  
–40°C<T<85°C VDO = VP/2[1]  
5
%
IDO vs T  
Charge Pump Current  
Variation vs. Temperature  
nA  
IOFF  
Charge Pump High-Imped- VCC = VP = 3.0V,  
ance Leakage Current  
±2.5  
Note:  
1. IDOvs T; Charge pump current variation vs. temperature.  
[IIDO(SI)@TI - IIDO(SI)@25° CI]/IIDO(SI)@25°CI * 100% and  
[IIDO(SO)@TI - IIDO(SO)@25°CI]/IIDO(SO)@25°CI *100%.  
4
PRELIMINARY  
CYW2338  
Timing Waveforms  
Key:  
FC Bit HIGH  
FC Bit LOW  
Increasing  
Voltage  
(Refer to Table 2 for meaning of FC bit.)  
Increasing Frequency  
VCO Characteristics  
Phase Comparator Sense  
Phase Detector Output Waveform  
F
F
R
P
tw  
tw  
LD  
DO Charge Pump Output Current Waveform  
F
F
R
P
tw  
tw  
D
o
ID  
O
Hi-Impedance State  
5
PRELIMINARY  
CYW2338  
Timing Waveforms (continued)  
Serial Data Input Timing Waveform[2, 3, 4, 5]  
//  
//  
//  
//  
PD = MSB  
PRE  
B1  
A7  
CNT2  
CNT1 = LSB  
DATA  
//  
//  
CLOCK  
t5  
t4  
t3  
t2  
t1  
//  
//  
//  
//  
LE  
t6  
Serial Data Input  
Data is input serially using the DATA, CLOCK, and LE pins. Two control bits direct data as described in Table 1.  
Table 1. Control Configuration  
CNT1  
CNT2  
Function  
0
0
Program Reference 2: R = 3 to 32767, set PLL2 (low frequency) phase detector  
polarity, set current in PLL2, set PLL2 to Hi-Impedance state, set monitor selector to PLL2.  
0
1
1
1
0
1
Program Reference 1: R = 3 to 32767, set PLL1 (high frequency) phase detector  
polarity, set current in PLL1, set PLL1 to Hi-Impedance state, set monitor selector to PLL1  
Program Counter for PLL2: A = 0 to 127, B = 3 to 2047, set PLL2 prescaler ratio, set  
PLL2 to power-down.  
Program Counter for PLL1: A = 0 to 127, B = 3 to 2047, set PLL1 prescaler ratio, set  
PLL1 to power-down.  
Notes:  
2. t1–t6 = t > 50 ns  
3. CLOCK may remain HIGH after latching in data.  
4. DATA is shifted in with the MSB first.  
5. For DATA definitions, refer to Table 2.  
6
PRELIMINARY  
CYW2338  
Table 2. Shift Register Configuration[6]  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22  
Reference Counter and Configuration Bits  
CNT1CNT2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 FC IDO TS LD FO  
Programmable Counter bits  
CNT1CNT2 A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 PRE PD  
Bit(s) Name  
CNT1, CNT2  
R1–R15  
FC  
Function  
Control Bits: Directs programming data to PLL1 (high frequency) or PLL2 (low frequency).  
Reference Counter Setting Bits: 15 bits, R = 3 to 32767.[7]  
Phase Sense of the Phase Detector: Set to match the VCO polarity, H = + (Positive VCO transfer function).  
Charge Pump Setting Bit: IDO HIGH = 3.8 mA, IDO LOW = 1 mA at VP = 3V.  
Hi-Impedance State Bit: Makes DO Hi-Impedance for PLL1 and PLL2 when HIGH.  
IDO  
TS  
LD  
Lock Detect: Directs the lock detect signal source pin 10. Pin 10 is HIGH with narrow low excursions when  
locked. When not locked, this pin is LOW.  
FO  
Frequency Out: This bit can be set to read out reference or programmable divider at the LD pin for test purposes.  
PRE  
Prescaler Divide Bit: For PLL1: LOW = 64/65 and HIGH = 128/129. For PLL2: LOW = 64/65 and HIGH =  
128/129.  
PD  
Power-down: LOW = power-up and HIGH = power-down. FIN is at a high-impedance state, respective B counter  
is disabled, forces DO outputs to Hi-Impedance and phase comparators are disabled. The reference counter is  
disabled and the OSC input is high-impedance after both PLLs are powered down. Data can be input and latched  
in the power-down state.  
A1–A7  
Swallow Counter Divide Ratio: A = 0 to 127 for PLL1 and PLL2.  
Programmable Counter Divide Ratio: B = 3 to 2047.[7]  
B1–B11  
Table 3. FO/LD Pin Truth Table  
FO (Bit 22)  
LD (Bit 21)  
PLL1  
PLL2  
PLL1  
PLL2  
FO/LD Pin Output State  
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
0
1
0
1
1
1
0
0
1
1
X
X
X
X
0
1
1
0
1
0
1
0
0
1
1
1
0
1
Disable  
PLL2 Lock Detect  
PLL1 Lock Detect  
PLL1/PLL2 Lock Detect  
PLL2 Reference Divider Output  
PLL1 Reference Divider Output  
PLL2 Programmable Divider Output  
PLL1 Programmable Divider Output  
PLL2 Counter Reset  
PLL1 Counter Reset  
PLL1/PLL2 Counter Reset  
Notes:  
6. The MSB is loaded in first.  
7. Low count ratios may violate frequency limits of the phase detector.  
7
PRELIMINARY  
CYW2338  
Table 4. 7-Bit Swallow Counter (A) Truth Table[8]  
Divide Ratio A  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
PLL1 (High Frequency)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
126  
127  
1
1
1
1
1
1
1
PLL2 (Low Frequency)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
126  
127  
1
1
1
1
1
1
1
Table 5. 11-Bit Programmable Counter (B) Truth Table[9]  
Divide Ratio B  
B11  
0
B10  
0
B9  
0
B8  
0
B7  
0
B6  
0
B5  
0
B4  
0
B3  
B2  
1
B1  
1
3
4
0
1
0
0
0
0
0
0
0
0
0
0
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
2046  
2047  
1
1
1
1
1
1
1
1
1
1
1
Table 6. 15-Bit Programmable Reference Counter (for PLL1 and PLL2) Truth Table[9]  
Divide Ratio R  
R15 R14 R13 R12 R11 R10  
R9  
0
R8  
0
R7  
0
R6  
0
R5  
R4  
0
R3  
0
R2  
1
R1  
3
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
32766  
32767  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Ordering Information[10]  
Package  
Name  
Ordering Code  
Package Type  
Tape and Reel Option  
ZI  
BCI  
LFI  
20-pin Thin Shrink Small Outline Package (0.173” wide)  
24-pin Chip Scale Package (3.5 mm X 4.5 mm)  
20-pin Micro Lead Frame (4 mm x 4 mm)  
CYW2338  
TR  
Document #: 38-01004-*A  
Notes:  
8. B is greater than or equal to A.  
9. Divide ratio less than 3 is prohibited. The divide ratio can be calculated using the following equation:  
fvco = {(P * B) + A} * fosc / R where (A < B)  
fvco: Output frequency of the external VCO.  
fosc: The crystal reference oscillator frequency.  
A: Preset divide ratio of the 7-bit swallow counter (0 to 127).  
B: Preset ratio of the 11-bit programmable counter (3 to 2047).  
P: Preset divide ratio of the dual modulus prescaler (64/65 or 128/129).  
R: Preset ratio of the 15-bit programmable reference counter (3 to 32767).  
The divide ratio N = (P * B) + A.  
10. Operating temperature range: –40°C to +85°C.  
8
PRELIMINARY  
CYW2338  
Typical Performance Characteristics  
Charge Pump Current vs Do Voltage  
Icp=Low  
Charge Pump Current vs Do Voltage  
Icp=High  
1.5  
1
6
4
Vp=5V  
Vp=3V  
Vp=5V  
Vp=3V  
2
0.5  
0
0
Vp=3V  
Vp = 5V  
-2  
-4  
-6  
-0.5  
-1  
Vp=3V  
Vp  
= 5V  
3
4
5
1
2
-1.5  
0
Do Voltage (V)  
2
3
4
5
0
1
Do Voltage (V)  
Figure 3.  
Figure 1.  
Do Output Current High Mode  
Do Output Current Low Mode  
ATTEN  
RL  
10dB  
VAVG  
10dB/  
100  
MKR  
-85.50dB  
-2.5dBm  
100.0kHz  
85 dB c  
1
START  
RBW  
835.8505MHz  
STOP  
836.1505MHz  
SWP 84.0ms  
3.0kHz  
VBW  
3.0kHz  
2
4
3
Figure 3. PLL Reference Spurs  
PLL Reference Spurious Level is –85.5 dBc  
Marker Reference  
Number  
Input  
Frequency  
Real Imaginary  
Marker 1  
623  
21  
-823  
-120  
-55  
100 MHz  
Marker 2  
Marker 3  
Marker 4  
1 GHz  
1.8 GHz  
2.2 GHz  
14  
13  
-39  
Figure 4.  
Input Impedance FIN1, FIN2  
VCC = 2.7 to 5.5V, FIN = 75 MHz to 2.6 GHz  
9
PRELIMINARY  
CYW2338  
Package Diagram  
20-Pin Thin Shrink Small Outline Package (TSSOP, 0.173” wide)  
10  
PRELIMINARY  
CYW2338  
Package Diagram  
24-Pin Chip Scale Package (CSP 3.5 mm X 4.5 mm)  
f
0.10  
Z
d
0.20  
X
4X  
Z
3.50  
PIN 1 PAD CORNER  
d
0.10  
Z
4.50  
1.04±0.10  
0.70±0.05  
Y
TOP VIEW  
SIDE VIEW  
PIN 1 PAD CORNER  
22  
24  
21  
1
0.45 X 0.25 TYP  
j
0.15  
m
Z
X Y  
0.50  
ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y14.5M-1994.  
UNLESS OTHERWISE SPECIFIED  
4X 0.25  
13  
9
12  
10  
0.50  
4X 1.25  
BOTTOM VIEW  
11  
PRELIMINARY  
CYW2338  
Package Diagram  
20-Pin Micro Lead Frame Package (MLF 4 mm X 4 mm)  
2X  
0.25  
C A  
A
D
10  
D/2  
4
0.05  
C
4X P  
M
b
0.10  
D2/2  
C A  
B
D1  
A
R
A1  
A3  
D2  
D1/2  
A2  
2X  
8.  
N
N
0.25  
C B  
4X P  
5
6
1
2
3
1
2
3
E1/2  
E/2  
0.50 DIA.  
(Ne-1)Xe  
REF.  
4X Q  
E1  
E
B
E2  
E2/2  
L
0.20  
C B  
0
2X  
e
C
0.20  
C A  
SEATING  
PLANE  
2X  
(Nd-1)Xe  
REF.  
TOP VIEW  
C
C
BOTTOM VIEW  
11  
C
C
A1  
L
L
b
4
SECTION "C-C"  
SCALE: NONE  
e
e
TERMINAL TIP  
FOR ODD TERMINAL/SIDE  
FOR EVEN TERMINAL/SIDE  
S
Y
1. DIE THICKNESS ALLOWABLE IS 0.305mm MAXIMUM(.012 INCHES MAXIMUM)  
2. DIMENSIONING & TOLERANCES CONFORM TO ASME Y14.5M. - 1994.  
COMMON  
NOTES:  
M
B
O
N
DIMENSIONS  
O
T
E
L
MIN.  
NOM.  
MAX.  
1.00  
0.05  
3. N IS THE NUMBER OF TERMINALS.  
Nd IS THE NUMBER OF TERMINALS IN X-DIRECTION &  
-
0.00  
-
0.85  
A
A1  
A2  
A3  
0.01  
0.65  
0.20 REF.  
11  
0.80  
Ne IS THE NUMBER OF TERMINALS IN Y-DIRECTION.  
4. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED  
BETWEEN 0.20 AND 0.25mm FROM TERMINAL TIP.  
D
D1  
E
E1  
4.00 BSC  
3.75 BSC  
4.00 BSC  
3.75 BSC  
5. THE PIN #1 IDENTIFIER MUST BE EXISTED ON THE TOP SURFACE OF THE  
PACKAGE BY USING INDENTATION MARK OR OTHER FEATURE OF PACKAGE BODY.  
6. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.  
7. ALL DIMENSIONS ARE IN MILLIMETERS.  
12  
0.60  
0
P
0.24  
0.13  
0.42  
0.17  
0.50 BSC  
20  
0.23  
R
e
N
Nd  
Ne  
L
8. THE SHAPE SHOWN ON FOUR CORNERS ARE NOT ACTUAL I/O.  
9. PACKAGE WARPAGE MAX 0.05mm.  
3
3
3
5
5
10. APPLIED FOR EXPOSED PAD AND TERMINALS.  
EXCLUDE EMBEDDING PART OF EXPOSED  
PAD FROM MEASURING.  
0.50  
0.18  
0.30  
1.55  
1.55  
0.60  
0.23  
0.40  
1.70  
1.70  
0.75  
0.30  
0.65  
1.85  
1.85  
b
Q
4
D2  
E2  
11. APPLIED ONLY FOR TERMINALS.  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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