CYV15G0404RB-BGC,PDF,CYV15G0404RB-BGC PDF资料,Datasheet,下载CYV15G0404RB-BGC技术资料

PRELIMINARY

CYV15G0404RB

Independent Clock Quad HOTLink II™ Reclocking

Deserializer

channels are independent and can simultaneously operate at

different rates. Each receive channel accepts serial data and

Features

• Quad channel video reclocking deserializer

— 195- to 1500-Mbps serial data signaling rate

— Simultaneous operation at different signaling rates

• Second-generation HOTLink^®technology

converts it to 10-bit parallel characters and presents these

characters to an Output Register. The received serial data can

also be reclocked and retransmitted through the reclocker

serial outputs. Figure 1 illustrates typical connections between

independent video co-processors and corresponding

• Compliant to SMPTE 292M and SMPTE 259M video

CYV15G0404RB

Reclocking

Deserializer

and

standards

CYV15G0403TB Serializer chips.

• Supports reception of either 1.485 or 1.485/1.001 Gbps

data rate with the same training clock

The CYV15G0404RB satisfies the SMPTE-259M and

SMPTE-292M compliance as per SMPTE EG34-1999 Patho-

logical Test Requirements.

• Supports half-rate and full-rate clocking

• Internal phase-locked loops (PLLs) with no external

As

a

second-generation

HOTLink

device,

the

PLL components

CYV15G0404RB extends the HOTLink family with enhanced

levels of integration and faster data rates, while maintaining

serial-link compatibility (data and BIST) with other HOTLink

devices.

• Selectable differential PECL-compatible serial inputs

— Internal DC-restoration

• Synchronous LVTTL parallel interface

• JTAG boundary scan

Each channel of the CYV15G0404RB Quad HOTLink II device

accepts a serial bit-stream from one of two selectable PECL-

compatible differential line receivers, and using a completely

integrated Clock and Data Recovery PLL, recovers the timing

information necessary for data reconstruction. The recovered

bit-stream is reclocked and retransmitted through the

reclocker serial outputs. Also, the recovered serial data is

deserialized and presented to the destination host system.

Each channel contains an independent BIST pattern checker.

This BIST hardware allows at-speed testing of the high-speed

serial data paths in each receive section of this device, each

transmit section of a connected HOTLink II device, and across

the interconnecting links.

• Built-In Self-Test (BIST) for at-speed link testing

• Link Quality Indicator

—Analog signal detect

—Digital signal detect

• Low-power 3W @ 3.3V typical

• Single 3.3V supply

• Thermally enhanced BGA

• 0.25µ BiCMOS technology

Functional Description

The CYV15G0404RB Independent Clock Quad HOTLink II™

Deserializing Reclocker is a point-to-point or point-to-multi-

point communications building block enabling transfer of data

over a variety of high-speed serial links including SMPTE 292

and SMPTE 259 video applications. It supports signaling rates

in the range of 195 to 1500 Mbps per serial link. The four

The CYV15G0404RB is ideal for SMPTE applications where

different data rates and serial interface standards are

necessary for each channel. Some applications include multi-

format routers, switchers, format converters, SDI monitors,

and camera control units.

Reclocked

Outputs

10

Independent

Channel

10

Independent

Channel

CYV15G0404RB

Reclocking Deserializer

CYV15G0403TB

Serializer

Serial Links

10

Reclocked

Outputs

Figure 1. HOTLink II™ System Connections

3901 North First Street San Jose, CA 95134

Cypress Semiconductor Corporation

•

408-943-2600

Document #: 38-02102 Rev. **

Revised July 21, 2004

CYV15G0404RB

PRELIMINARY

CYV15G0404RB Deserializing Reclocker Logic Block Diagram

x10

Deserializer

RX

Reclocker

Document #: 38-02102 Rev. **

Page 2 of 26

CYV15G0404RB

PRELIMINARY

=

Internal Signal

Reclocking Deserializer Path Block Diagram

RESET

TRST

TRGRATEA

JTAG

Boundary

Scan

TMS

TCLK

TDI

x2

TRGCLKA

Controller

SDASEL[2..1]A[1:0]

TDO

LDTDEN

INSELA

LFIA

Receive

Signal

Monitor

10

RXDA[9:0]

BISTSTA

10

INA1+

INA1–

INA2+

INA2–

Clock &

Data

Recovery

PLL

RXCLKA+

RXCLKA–

÷2

ULCA

SPDSELA

RXBISTA[1:0]

RXRATEA

RXPLLPDA

Recovered Serial Data

Recovered Character Clock

ROE[2..1]A

Reclocker

ROUTA1+

ROUTA1–

ROE[2..1]A

Output PLL

Clock Multiplier A

ROUTA2+

ROUTA2–

RECLKOA

REPDOA

Character-Rate Clock A

TRGRATEB

x2

TRGCLKB

LDTDEN

SDASEL[2..1]B[1:0]

LFIB

Receive

Signal

INSELB

Monitor

10

RXDB[9:0]

BISTSTB

10

INB1+

INB1–

INB2+

INB2–

Clock &

Data

Recovery

PLL

RXCLKB+

RXCLKB–

÷2

ULCB

SPDSELB

RXBISTB[1:0]

RXRATEB

RXPLLPDB

Recovered Serial Data

Recovered Character Clock

ROE[2..1]B

Reclocker

ROUTB1+

ROUTB1–

ROE[2..1]B

Output PLL

Clock Multiplier B

ROUTB2+

ROUTB2–

RECLKOB

REPDOB

Character-Rate Clock B

Document #: 38-02102 Rev. **

Page 3 of 26

CYV15G0404RB

PRELIMINARY

Reclocking Deserializer Path Block Diagram (Continued)

=

Internal Signal

TRGRATEC

x2

TRGCLKC

SDASEL[2..1]C[1:0]

LDTDEN

INSELC

LFIC

Receive

Signal

Monitor

10

RXDC[9:0]

BISTSTC

10

INC1+

INC1–

INC2+

INC2–

Clock &

Data

Recovery

PLL

RXCLKC+

RXCLKC–

÷2

ULCC

SPDSELC

RXBISTC[1:0]

RXRATEC

RXPLLPDC

Recovered Serial Data

Recovered Character Clock

ROE[2..1]C

Reclocker

ROUTC1+

ROUTC1–

ROE[2..1]C

Output PLL

Clock Multiplier C

ROUTC2+

ROUTC2–

RECLKOC

REPDOC

Character-Rate Clock C

TRGRATED

x2

TRGCLKD

SDASEL[2..1]D[1:0]

LDTDEN

INSELD

LFID

Receive

Signal

Monitor

10

RXDD[9:0]

BISTSTD

10

IND1+

IND1–

IND2+

IND2–

Clock &

Data

Recovery

PLL

RXCLKD+

RXCLKD–

÷2

ULCD

SPDSELD

RXBISTD[1:0]

RXRATED

RXPLLPDD

Recovered Serial Data

Recovered Character Clock

ROE[2..1]D

Reclocker

ROUTD1+

ROUTD1–

ROE[2..1]D

Output PLL

Clock Multiplier D

ROUTD2+

ROUTD2–

RECLKOD

REPDOD

Character-Rate Clock D

Document #: 38-02102 Rev. **

Page 4 of 26

CYV15G0404RB

PRELIMINARY

Device Configuration and Control Block Diagram

= Internal Signal

RXBIST[A..D]

RXRATE[A..D]

SDASEL[A..D][1:0]

RXPLLPD[A..D]

ROE[2..1][A..D]

GLEN[11..0]

FGLEN[2..0]

WREN

ADDR[3:0]

DATA[7:0]

Device Configuration

and Control Interface

Document #: 38-02102 Rev. **

Page 5 of 26

CYV15G0404RB

PRELIMINARY

Pin Configuration (Top View)^[1]

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A

B

C

D

E

F

IN

ROUT

C1–

IN

ROUT

C2–

IN

ROUT

D1–

IN

ROUT

D2–

IN

ROUT

A1–

IN

ROUT

A2–

IN

ROUT

B1–

IN

ROUT

B2–

V

GND

V

CC

C1–

C2–

D1–

D2–

A1–

A2–

B1–

B2–

IN

ROUT

C1+

IN

ROUT

C2+

IN

ROUT

D1+

IN

ROUT

D2+

IN

ROUT

A1+

IN

ROUT

A2+

IN

ROUT

B1+

IN

ROUT

B2+

V

GND

V

C1+

C2+

D1+

D2+

A1+

A2+

B1+

B2+

TDI

TMS INSELC INSELB

ULCD ULCC

DATA

[7]

DATA

[5]

DATA

[3]

DATA

[1]

SPD

LDTD TRST

EN

TDO

V

GND

CC

SELD

TCLK RESET INSELD INSELA

ULCA

SPD

DATA

[6]

DATA

[4]

DATA

[2]

DATA

[0]

ULCB

SCAN TMEN3

EN2

GND GND

NC

V

CC

SELC

V

CC

RX

RE

RX

V

CC

DC[8] DC[9]

DB[0] CLKOB DB[1]

G

H

J

WREN

GND

SPD

RX

GND GND

NC

SELB

SELA DB[3]

GND GND GND GND

BIST

STB

RX

DB[2]

DB[7]

DB[4]

K

L

RX

TRG

RX

LFIB

GND GND

DC[4] CLKC–

DB[5]

DB[6]

DB[9]

RX

TRG

LFIC

RX

GND

DC[5] CLKC+

DB[8] CLKB+ CLKB–

M

N

P

R

T

RX

RE

TRG

RE

V

CC

DC[6] DC[7]

PDOC

CLKB+ CLKB– PDOB

GND GND GND GND

RX

DC[3] DC[2] DC[1] DC[0]

BIST

RE

RX

V

CC

STC CLKOC CLKC+ CLKC–

V

CC

U

V

W

Y

RX

ADDR

[0]

TRG

RX

BIST

STA

RX

V

GND GND

GND GND GND

V

CC

DD[4] DD[3]

CLKD–

DA[4]

DA[0]

RX

BIST ADDR

STD [2]

TRG

RE

RX

GND

GND GND

DD[8]

DD[5] DD[1]

CLKD+ CLKOA

DA[9]

DA[5]

DA[2]

DA[1]

LFID

RX

ADDR ADDR

RX

RE

LFIA

TRG

RX

GND GND

CLKD–

DD[6] DD[0]

[3]

[1]

CLKA+ PDOA

CLKA+ DA[6]

DA[3]

RX

RE

NC

RX

RE

TRG

RX

GND

DD[9] CLKD+

DD[7] DD[2]

CLKOD

CLKA–

PDOD CLKA– DA[8]

DA[7]

1. NC = Do not connect.

Document #: 38-02102 Rev. **

Page 6 of 26

CYV15G0404RB

PRELIMINARY

Pin Configuration (Bottom View)^[1]

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ROUT

B2–

IN

ROUT

B1–

IN

ROUT

A2–

IN

ROUT

A1–

IN

ROUT

D2–

IN

ROUT

D1–

IN

ROUT

C2–

IN

ROUT

C1–

IN

V

GND

V

CC

A

B

C

D

E

F

B2–

B1–

A2–

A1–

D2–

D1–

C2–

C1–

ROUT

B2+

IN

ROUT

B1+

IN

ROUT

A2+

IN

ROUT

A1+

IN

ROUT

D2+

IN

ROUT

D1+

IN

ROUT

C2+

IN

ROUT

C1+

IN

V

GND

V

B2+

B1+

A2+

A1+

D2+

D1+

C2+

C1+

TDO

TRST LDTD

EN

SPD

DATA

[1]

DATA

[3]

DATA

[5]

DATA

[7]

ULCC ULCD

INSELB INSELC TMS

TDI

GND

V

CC

SELD

TMEN3 SCAN

EN2

ULCB

DATA

[0]

DATA

[2]

DATA

[4]

DATA

[6]

SPD

ULCA

INSELA INSELD RESET TCLK

V

NC

GND GND

CC

SELC

V

CC

RX

RE

RX

V

CC

DB[1] CLKOB DB[0]

DC[9] DC[8]

RX

SPD

WREN

GND

NC

GND GND

G

H

J

DB[3] SELA

SELB

GND GND GND GND

RX

BIST

STB

DB[4]

DB[7]

DB[2]

LFIB

RX

TRG

RX

GND GND

K

L

DB[9]

DB[6]

DB[5]

CLKC– DC[4]

RX

LFIC

TRG

RX

GND

CLKB– CLKB+ DB[8]

CLKC+ DC[5]

RE

TRG

RE

RX

V

CC

M

N

P

R

T

PDOB CLKB– CLKB+

PDOC

DC[7] DC[6]

GND GND GND GND

RX

DC[0] DC[1] DC[2] DC[3]

RX

RE

BIST

V

CC

CLKC– CLKC+ CLKOC STC

V

CC

RX

BIST

STA

RX

TRG

ADDR

[0]

RX

V

GND GND GND

GND GND

V

CC

U

V

W

Y

DA[0]

DA[4]

CLKD–

DD[3] DD[4]

RX

RE

TRG

ADDR BIST

[2] STD

RX

GND GND

GND

DA[1]

DA[2]

DA[5]

DA[9]

CLKOA CLKD+

DD[1] DD[5]

DD[8]

RX

TRG

LFIA

RE

RX

ADDR ADDR

RX

LFID

GND GND

DA[3]

DA[6] CLKA+

PDOA CLKA+

[1]

[3]

DD[0] DD[6]

CLKD–

RX

TRG

RE

RX

NC

RE

RX

GND

DA[7]

DA[8] CLKA– PDOD

CLKA–

CLKOD

DD[2] DD[7]

CLKD+ DD[9]

Document #: 38-02102 Rev. **

Page 7 of 26

CYV15G0404RB

PRELIMINARY

Pin Definitions

CYV15G0404RB Quad HOTLink II Deserializing Reclocker

Name

I/O Characteristics

Signal Description

Receive Path Data and Status Signals

RXDA[9:0]

RXDB[9:0]

RXDC[9:0]

RXDD[9:0]

LVTTL Output,

Parallel Data Output. RXDx[9:0] parallel data outputs change relative to the

receive interface clock. If RXCLKx± is a full-rate clock, the RXCLKx± clock

outputs are complementary clocks operating at the character rate. The

RXDx[9:0] outputs for the associated receive channels follow rising edge of

RXCLKx+ or falling edge of RXCLKx–. If RXCLKx± is a half-rate clock, the

RXCLKx± clock outputs are complementary clocks operating at half the

character rate. The RXDx[9:0] outputs for the associated receive channels

follow both the falling and rising edges of the associated RXCLKx± clock

outputs.

synchronous to the

RXCLK± output

When BIST is enabled on the receive channel, the BIST status is presented on

the RXDx[1:0] and BISTSTx outputs. See Table 5 for each status reported by

the BIST state machine. Also, while BIST is enabled, the RXDx[9:2] outputs

should be ignored.

BISTSTA

BISTSTB

BISTSTC

BISTSTD

LVTTL Output,

BIST Status Output. When RXBISTx[1:0] = 10, BISTSTx (along with

RXDx[1:0]) displays the status of the BIST reception. See Table 5 for the BIST

status reported for each combination of BISTSTx and RXDx[1:0].

synchronous to the

RXCLKx ± output

When RXBISTx[1:0] ≠ 10, BISTSTx should be ignored.

REPDOA

REPDOB

REPDOC

REPDOD

Asynchronous to

reclocker output

channel

Reclocker Powered Down Status Output. REPDOx is asserted HIGH, when

the associated channel’s reclocker output logic is powered down. This occurs

when ROE2x and ROE1x are both disabled by setting ROE2x = 0 and ROE1x

= 0.

enable / disable

Receive Path Clock Signals

TRGCLKA±

TRGCLKB±

TRGCLKC±

TRGCLKD±

DifferentialLVPECLor CDR PLL Training Clock. TRGCLKx± clock inputs are used as the reference

single-ended

source for the frequency detector (Range Controller) of the associated receive

PLL to reduce PLL acquisition time.

LVTTL input clock

In the presence of valid serial data, the recovered clock output of the receive

CDR PLL (RXCLKx±) has no frequency or phase relationship with TRGCLKx±.

When driven by a single-ended LVCMOS or LVTTL clock source, connect the

clock source to either the true or complement TRGCLKx input, and leave the

alternate TRGCLKx input open (floating). When driven by an LVPECL clock

source, the clock must be a differential clock, using both inputs.

RXCLKA±

RXCLKB±

RXCLKC±

RXCLKD±

LVTTL Output Clock

LVTTL Output

Receive Clock Output. RXCLKx± is the receive interface clock used to control

timing of the RXDx[9:0] parallel outputs. These true and complement clocks are

used to control timing of data output transfers. These clocks are output contin-

uously at either the half-character rate (1/20^ththe serial bit-rate) or character

rate (1/10^ththe serial bit-rate) of the data being received, as selected by

RXRATEx.

Reclocker Clock Output. RECLKOx output clock is synthesized by the

associated reclocker output PLL and operates synchronous to the internal

recovered character clock. RECLKOx operates at either the same frequency as

RXCLKx± (RXRATEx = 0), or at twice the frequency of RXCLKx± (RXRATEx =

1).The reclocker clock outputs have no fixed phase relationship to RXCLKx±.

RECLKOA

RECLKOB

RECLKOC

RECLKOD

Device Control Signals

RESET

LVTTL Input,

Asynchronous Device Reset. RESET initializes all state machines, counters,

and configuration latches in the device to a known state. RESET must be

asserted LOW for a minimum pulse width. When the reset is removed, all state

machines, counters and configuration latches are at an initial state. See Table 3

for the initialize values of the device configuration latches.

asynchronous,

internal pull-up

Document #: 38-02102 Rev. **

Page 8 of 26

CYV15G0404RB

PRELIMINARY

Pin Definitions (continued)

CYV15G0404RB Quad HOTLink II Deserializing Reclocker

Name

I/O Characteristics

Signal Description

LDTDEN

LVTTL Input,

Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal

Level Detector, Range Controller, and Transition Density Detector are all

enabled to determine if the RXPLL tracks TRGCLKx± or the selected input serial

data stream. If the Signal Level Detector, Range Controller, or Transition Density

Detector are out of their respective limits while LDTDEN is HIGH, the RXPLL

locks to TRGCLKx± until such a time they become valid. The SDASEL[A..D][1:0]

inputs are used to configure the trip level of the Signal Level Detector. The

Transition Density Detector limit is one transition in every 60 consecutive bits.

When LDTDEN is LOW, only the Range Controller is used to determine if the

RXPLL tracks TRGCLKx± or the selected input serial data stream. It is recom-

mended to set LDTDEN = HIGH.

internal pull-up

ULCA

ULCB

ULCC

ULCD

LVTTL Input,

Use Local Clock. When ULCx is LOW, the RXPLL is forced to lock to

TRGCLKx± instead of the received serial data stream. While ULCx is LOW, the

LFIx for the associated channel is LOW indicating a link fault.

When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions

on the input data streams. This function is used in applications in which a stable

RXCLKx± is needed. In cases when there is an absence of valid data transitions

for a long period of time, or the high-gain differential serial inputs (INx±) are left

floating, there may be brief frequency excursions of the RXCLKx± outputs from

TRGCLKx±.

internal pull-up

SPDSELA

SPDSELB

SPDSELC

SPDSELD

3-Level Select^[2]

Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate

static control input

range of each channel’s receive PLL.

LOW = 195 – 400 MBd

MID = 400 – 800 MBd

HIGH = 800 – 1500 MBd.

INSELA

INSELB

INSELC

INSELD

LVTTL Input,

asynchronous

Receive Input Selector. The INSELx input determines which external serial bit

stream is passed to the receiver’s Clock and Data Recovery circuit. When

INSELx is HIGH, the Primary Differential Serial Data Input, INx1±, is selected

for the associated receive channel. When INSELx is LOW, the Secondary Differ-

ential Serial Data Input, INx2±, is selected for the associated receive channel.

LFIA

LFIB

LFIC

LFID

LVTTL Output,

asynchronous

Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is

the logical OR of six internal conditions. LFIx is asserted LOW when any of the

following conditions is true:

• Received serial data rate outside expected range

• Analog amplitude below expected levels

• Transition density lower than expected

• Receive channel disabled

• ULCx is LOW

• Absence of TRGCLKx±.

Device Configuration and Control Bus Signals

WREN

LVTTL input,

Control Write Enable. The WREN input writes the values of the DATA[7:0] bus

asynchronous,

internal pull-up

into the latch specified by the address location on the ADDR[3:0] bus.^[3]

ADDR[3:0]

LVTTL input

Control Addressing Bus. The ADDR[3:0] bus is the input address bus used to

configure the device. The WREN input writes the values of the DATA[7:0] bus

into the latch specified by the address location on the ADDR[3:0] bus.^[3]Table 3

lists the configuration latches within the device, and the initialization value of the

latches upon the assertion of RESET. Table 4 shows how the latches are

mapped in the device.

asynchronous,

internal pull-up

Notes:

2. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually

implemented by direct connection to V (ground). The HIGH level is usually implemented by direct connection to V (power). The MID level is usually

SS

CC

implemented by not connecting the input (left floating), which allows it to self bias to the proper level.

3. See Device Configuration and Control Interface for detailed information on the operation of the Configuration Interface.

Document #: 38-02102 Rev. **

Page 9 of 26

CYV15G0404RB

PRELIMINARY

Pin Definitions (continued)

CYV15G0404RB Quad HOTLink II Deserializing Reclocker

Name

I/O Characteristics

Signal Description

DATA[7:0]

LVTTL input

Control Data Bus. The DATA[7:0] bus is the input data bus used to configure

the device. The WREN input writes the values of the DATA[7:0] bus into the latch

specified by address location on the ADDR[3:0] bus.^{[3 ]}Table 3 lists the config-

uration latches within the device, and the initialization value of the latches upon

the assertion of RESET. Table 4 shows how the latches are mapped in the

device.

asynchronous,

internal pull-up

Internal Device Configuration Latches

RXRATE[A..D]

Internal Latch^[4]

Receive Clock Rate Select.

Signal Detect Amplitude Select.

SDASEL[2..1][A..D] Internal Latch^[4]

[1:0]

RXPLLPD[A..D]

RXBIST[A..D][1:0]

ROE2[A..D]

ROE1[A..D]

GLEN[11..0]

Internal Latch^[4]

Receive Channel Power Control.

Receive Bist Disabled.

Reclocker Differential Serial Output Driver 2 Enable.

Reclocker Differential Serial Output Driver 1 Enable.

Global Latch Enable.

FGLEN[2..0]

Force Global Latch Enable.

Factory Test Modes

SCANEN2

LVTTL input,

Factory Test 2. SCANEN2 input is for factory testing only. This input may be left

internal pull-down

as a NO CONNECT, or GND only.

TMEN3

LVTTL input,

Factory Test 3. TMEN3 input is for factory testing only. This input may be left

internal pull-down

as a NO CONNECT, or GND only.

Analog I/O

ROUTA1±

ROUTB1±

ROUTC1±

ROUTD1±

CML Differential

Output

Primary Differential Serial Data Output. The ROUTx1± PECL-compatible

CML outputs (+3.3V referenced) are capable of driving terminated transmission

lines or standard fiber-optic transmitter modules, and must be AC-coupled for

PECL-compatible connections.

ROUTA2±

ROUTB2±

ROUTC2±

ROUTD2±

CML Differential

Output

Secondary Differential Serial Data Output. The ROUTx2± PECL-compatible CML

outputs (+3.3V referenced) are capable of driving terminated transmission lines or

standard fiber-optic transmitter modules, and must be AC-coupled for PECL-

compatible connections.

INA1±

INB1±

INC1±

IND1±

INA2±

INB2±

INC2±

IND2±

Differential Input

Primary Differential Serial Data Input. The INx1± input accepts the serial data

stream for deserialization. The INx1± serial stream is passed to the receive CDR

circuit to extract the data content when INSELx = HIGH.

Secondary Differential Serial Data Input. The INx2± input accepts the serial

data stream for deserialization. The INx2± serial stream is passed to the receiver

CDR circuit to extract the data content when INSELx = LOW.

JTAG Interface

TMS

LVTTL Input,

Test Mode Select. Used to control access to the JTAG Test Modes. If

maintained high for ≥5 TCLK cycles, the JTAG test controller is reset.

internal pull-up

TCLK

TDO

TDI

LVTTL Input,

JTAG Test Clock.

internal pull-down

3-State LVTTL Output Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not

selected.

Test Data In. JTAG data input port.

LVTTL Input,

internal pull-up

TRST

LVTTL Input,

JTAG reset signal. When asserted (LOW), this input asynchronously resets the

internal pull-up

JTAG test access port controller.

Note:

4. See Device Configuration and Control Interface for detailed information on the internal latches.

Document #: 38-02102 Rev. **

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CYV15G0404RB

PRELIMINARY

Pin Definitions (continued)

CYV15G0404RB Quad HOTLink II Deserializing Reclocker

Name

Power

V_CC

I/O Characteristics

Signal Description

+3.3V Power.

GND

Signal and Power Ground for all internal circuits.

CYV15G0404RB HOTLink II Operation

The CYV15G0404RB is a highly configurable, independent

clocking, quad-channel reclocking deserializer designed to

support reliable transfer of large quantities of digital video

data, using high-speed serial links from multiple sources to

multiple destinations. This device supports four 10-bit

channels.

operation with highly attenuated signals, or in high-noise

environments. The analog amplitude level detection is set by

the SDASELx latch via device configuration interface. The

SDASELx latch sets the trip point for the detection of a valid

signal at one of three levels, as listed in Table 1. This control

input affects the analog monitors for all receive channels. The

Analog Signal Detect monitors are active for the Line Receiver

as selected by the associated INSELx input.

CYV15G0404RB Receive Data Path

Serial Line Receivers

Table 1. Analog Amplitude Detect Valid Signal Levels^[5]

SDA-

Two differential Line Receivers, INx1± and INx2±, are

available on each channel for accepting serial data streams.

The active Serial Line Receiver on a channel is selected using

the associated INSELx input. The Serial Line Receiver inputs

are differential, and can accommodate wire interconnect and

filtering losses or transmission line attenuation greater than

16 dB. For normal operation, these inputs should receive a

signal of at least VI_DIFF> 100 mV, or 200 mV peak-to-peak

differential. Each Line Receiver can be DC- or AC-coupled to

+3.3V powered fiber-optic interface modules (any ECL/PECL

family, not limited to 100K PECL) or AC-coupled to +5V

powered optical modules. The common-mode tolerance of

these line receivers accommodates a wide range of signal

termination voltages. Each receiver provides internal DC-

restoration, to the center of the receiver’s common mode

range, for AC-coupled signals.

SEL

00

01

Typical Signal with Peak Amplitudes Above

Analog Signal Detector is disabled

140 mV p-p differential

10

280 mV p-p differential

11

420 mV p-p differential

Transition Density

The Transition Detection logic checks for the absence of

transitions spanning greater than six transmission characters

(60 bits). If no transitions are present in the data received, the

Detection logic for that channel asserts LFIx.

Range Controls

The CDR circuit includes logic to monitor the frequency of the

PLL Voltage Controlled Oscillator (VCO) used to sample the

incoming data stream. This logic ensures that the VCO

operates at, or near the rate of the incoming data stream for

two primary cases:

Signal Detect/Link Fault

Each selected Line Receiver (i.e., that routed to the clock and

data recovery PLL) is simultaneously monitored for

• analog amplitude above amplitude level selected by

SDASELx

• when the incoming data stream resumes after a time in

which it has been “missing.”

• transition density above the specified limit

• when the incoming data stream is outside the acceptable

signaling rate range.

• range controls report the received data stream inside

normal frequency range (±1500ppm^[21]

)

To perform this function, the frequency of the RXPLL VCO is

periodically compared to the frequency of the

TRGCLKx±input. If the VCO is running at a frequency beyond

±1500ppm^[21]as defined by the TRGCLKx± frequency, it is

• receive channel enabled

• Presence of reference clock

• ULCx is not asserted.

All of these conditions must be valid for the Signal Detect block

to indicate a valid signal is present. This status is presented on

the LFIx (Link Fault Indicator) output associated with each

receive channel, which changes synchronous to the receive

interface clock.

periodically forced to the correct frequency (as defined by

TRGCLKx±, SPDSELx, and TRGRATEx) and then released in

an attempt to lock to the input data stream.

The sampling and relock period of the Range Control is calcu-

lated as follows: RANGE_CONTROL_ SAMPLING_PERIOD

= (RECOVERED BYTE CLOCK PERIOD) * (4096).

Analog Amplitude

While most signal monitors are based on fixed constants, the

analog amplitude level detection is adjustable to allow

Note:

5. The peak amplitudes listed in this table are for typical waveforms that have generally 3 – 4 transitions for every ten bits. In a worse case environment the signals

may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase

the values in the table above by approximately 100 mV.

Document #: 38-02102 Rev. **

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CYV15G0404RB

PRELIMINARY

During the time that the Range Control forces the RXPLL VCO

to track TRGCLKx±, the LFIx output is asserted LOW. After a

valid serial data stream is applied, it may take up to one

RANGE CONTROL SAMPLING PERIOD before the PLL

locks to the input data stream, after which LFIx should be

HIGH.

in brief RXCLK± frequency excursions from TRGCLKx±.

However, the validity of the input data stream is indicated by

the LFIx output. The frequency of TRGCLKx± is required to be

within ±1500ppm^[21]of the frequency of the clock that drives

the reference clock input of the remote transmitter to ensure a

lock to the incoming data stream. This large ppm tolerance

allows the CDR PLL to reliably receive a 1.485 or 1.485/1.001

Gbps SMPTE HD-SDI data stream with a constant TRGCLK

frequency.

For systems using multiple or redundant connections, the LFIx

output can be used to select an alternate data stream. When

an LFIx indication is detected, external logic can toggle

selection of the associated INx1± and INx2± input through the

associated INSELx input. When a port switch takes place, it is

necessary for the receive PLL for that channel to reacquire the

new serial stream.

The operating serial signaling-rate and allowable range of

TRGCLK± frequencies are listed in Table 2.

Table 2. Operating Speed Settings

TRGCLKx±

Frequency

(MHz)

Signaling

SPDSELx TRGRATEx

Rate (Mbps)

LOW

MID (Open)

HIGH

1

0

1

0

1

0

reserved

19.5 – 40

20 – 40

40 – 80

40 – 75

195 – 400

400 – 800

800 – 1500

Reclocker

Each receive channel performs a reclocker function on the

incoming serial data. To do this, the Clock and Data Recovery

PLL first recovers the clock from the data. The data is retimed

by the recovered clock and then passed to an output register.

Also, the recovered character clock from the receive PLL is

passed to the reclocker output PLL which generates the bit

clock that is used to clock the retimed data into the output

register. This data stream is then transmitted through the

differential serial outputs.

80 – 150

Receive Channel Enabled

The CYV15G0404RB contains four receive channels that can

be independently enabled and disabled. Each channel can be

enabled or disabled separately through the RXPLLPDx input

latch as controlled by the device configuration interface. When

the RXPLLPDx latch = 0, the associated PLL and analog

circuitry of the channel is disabled. Any disabled channel

indicates a constant link fault condition on the LFIx output.

When RXPLLPDx = 1, the associated PLL and receive

channel is enabled to receive a serial stream.

Note. When a disabled receive channel is reenabled, the

status of the associated LFIx output and data on the parallel

outputs for the associated channel may be indeterminate for

up to 2 ms.

Reclocker Serial Output Drivers

The serial output interface drivers use differential Current

Mode Logic (CML) drivers to provide source-matched drivers

for 50Ω transmission lines. These drivers accept data from the

reclocker output register in the reclocker channel. These

drivers have signal swings equivalent to that of standard PECL

drivers, and are capable of driving AC-coupled optical

modules or transmission lines.

Reclocker Output Channels Enabled

Clock/Data Recovery

Each driver can be enabled or disabled separately via the

The extraction of a bit-rate clock and recovery of bits from each

received serial stream is performed by a separate CDR block

within each receive channel. The clock extraction function is

performed by an integrated PLL that tracks the frequency of

the transitions in the incoming bit stream and align the phase

of the internal bit-rate clock to the transitions in the selected

serial data stream.

Each CDR accepts a character-rate (bit-rate ÷ 10) or half-

character-rate (bit-rate ÷ 20) training clock from the

associated TRGCLKx± input. This TRGCLKx± input is used to

device configuration interface.

When a driver is disabled via the configuration interface, it is

internally powered down to reduce device power. If both

reclocker serial drivers for a channel are in this disabled state,

the associated internal reclocker logic is also powered down.

The deserialization logic and parallel outputs will remain

enabled. A device reset (RESET sampled LOW) disables all

output drivers.

Note. When the disabled reclocker function (i.e., both outputs

disabled) is re-enabled, the data on the reclocker serial

outputs may not meet all timing specifications for up to 250 µs.

• ensure that the VCO (within the CDR) is operating at the

correct frequency (rather than a harmonic of the bit-rate)

Output Bus

• reduce PLL acquisition time

• limit unlocked frequency excursions of the CDR VCO when

there is no input data present at the selected Serial Line

Receiver.

Each receive channel presents a 10-bit data signal (and a

BIST status signal when RXBISTx[1:0] = 10).

Receive BIST Operation

Regardless of the type of signal present, the CDR attempts to

recover a data stream from it. If the signalling rate of the

recovered data stream is outside the limits set by the range

control monitors, the CDR tracks TRGCLKx± instead of the

data stream. Once the CDR output (RXCLK±) frequency

returns back close to TRGCLKx± frequency, the CDR input is

switched back to the input data stream. If no data is present at

the selected line receiver, this switching behavior may result

Each receiver channel contains an internal pattern checker

that can be used to validate both device and link operation.

These pattern checkers are enabled by the associated

RXBISTx[1:0] latch via the device configuration interface.

When enabled, a register in the associated receive channel

becomes a signature pattern generator and checker by

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CYV15G0404RB

PRELIMINARY

logically converting to a Linear Feedback Shift Register

(LFSR). This LFSR generates a 511-character sequence. This

provides a predictable yet pseudo-random sequence that can

be matched to an identical LFSR in the attached Trans-

mitter(s). When synchronized with the received data stream,

the associated Receiver checks each character from the

deserializer with each character generated by the LFSR and

indicates compare errors and BIST status at the RXDx[1:0]

and BISTSTx bits of the Output Register.

The BIST status bus {BISTSTx, RXDx[0], RXDx[1]} indicates

010b or 100b for one character period per BIST loop to

indicate loop completion. This status can be used to check test

pattern progress.

The specific status reported by the BIST state machine is listed

in Table 5. These same codes are reported on the receive

status outputs.

If the number of invalid characters received ever exceeds the

number of valid characters by 16, the receive BIST state

machine aborts the compare operations and resets the LFSR

to look for the start of the BIST sequence again.

Following a device reset, it is necessary to enable the receive

channels used for normal operation. This can be done by

sequencing the appropriate values on the device configuration

interface.^[3]

Device Configuration and Control Interface

The CYV15G0404RB is highly configurable via the configu-

ration interface. The configuration interface allows the device

to be configured globally or allows each channel to be

configured independently. Table 3 lists the configuration

latches within the device including the initialization value of the

latches upon the assertion of RESET. Table 4 shows how the

latches are mapped in the device. Each row in the Table 4

maps to a 8-bit latch bank. There are 16 such write-only latch

banks. When WREN = 0, the logic value in the DATA[7:0] is

latched to the latch bank specified by the values in ADDR[3:0].

The second column of Table 4 specifies the channels

associated with the corresponding latch bank. For example,

the first three latch banks (0,1 and 2) consist of configuration

bits for channel A. The latch banks 12, 13 and 14 consist of

Global configuration bits and the last latch bank (15) is the

Mask latch bank that can be configured to perform bit-by-bit

configuration.

A device reset (RESET sampled LOW) presets the BIST

Enable Latches to disable BIST on all channels.

BIST Status State Machine

Global Enable Function

When a receive path is enabled to look for and compare the

received data stream with the BIST pattern, the {BISTSTx,

RXDx[0], RXDx[1]} bits identify the present state of the BIST

compare operation.

The BIST state machine has multiple states, as shown in

Figure 2 and Table 5. When the receive PLL detects an out-of-

lock condition, the BIST state is forced to the Start-of-BIST

state, regardless of the present state of the BIST state

machine. If the number of detected errors ever exceeds the

number of valid matches by greater than 16, the state machine

is forced to the WAIT_FOR_BIST state where it monitors the

receive path for the first character of the next BIST sequence.

The global enable function, controlled by the GLENx bits, is a

feature that can be used to reduce the number of write opera-

tions needed to setup the latch banks. This function is

beneficial in systems that use a common configuration in

multiple channels. The GLENx bit is present in bit 0 of latch

banks 0 through 11 only. Its default value (1) enables the global

update of the latch bank's contents. Setting the GLENx bit to

0 disables this functionality.

Latch Banks 12, 13, and 14 are used to load values in the

related latch banks in a global manner. A write operation to

latch bank 12 could do a global write to latch banks 0, 3, 6, and

9 depending on the value of GLENx in these latch banks; latch

bank 13 could do a global write to latch banks 1, 4, 7 and 10;

and latch banks 14 could do a global write to latch banks 2, 5,

8 and 11. The GLENx bit cannot be modified by a global write

operation.

Power Control

The CYV15G0404RB supports user control of the powered up

or down state of each transmit and receive channel. The

receive channels are controlled by the RXPLLPDx latch via the

device configuration interface. When RXPLLPDx = 0, the

associated PLL and analog circuitry of the channel is disabled.

The transmit channels are controlled by the OE1x and the

OE2x latches via the device configuration interface. The

reclocker function is controlled by the ROE1x and the ROE2x

latches via the device configuration interface. When a driver is

disabled via the configuration interface, it is internally powered

down to reduce device power. If both serial drivers for a

channel are in this disabled state, the associated internal logic

for that channel is also powered down. When the reclocker

serial drivers are disabled, the reclocker function will be

disabled, but the deserialization logic and parallel outputs will

remain enabled.

Force Global Enable Function

FGLENx forces the global update of the target latch banks, but

does not change the contents of the GLENx bits. If FGLENx =

1 for the associated global channel, FGLENx forces the global

update of the target latch banks.

Mask Function

An additional latch bank (15) is used as a global mask vector

to control the update of the configuration latch banks on a bit-

by-bit basis. A logic 1 in a bit location allows for the update of

that same location of the target latch bank(s), whereas a logic

0 disables it. The reset value of this latch bank is FFh, thereby

making its use optional by default. The mask latch bank is not

maskable. The FGLEN functionality is not affected by the bit 0

value of the mask latch bank.

Device Reset State

When the CYV15G0404RB is reset by assertion of RESET, all

state machines, counters, and configuration latches in the

device are initialized to a reset state. See Table 3 for the

initialize values of the configuration latches.

Latch Types

There are two types of latch banks: static (S) and dynamic (D).

Each channel is configured by 2 static and 1 dynamic latch

banks. The S type contain those settings that normally do not

change for a given application, whereas the D type controls

Document #: 38-02102 Rev. **

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CYV15G0404RB

PRELIMINARY

the settings that could change during the application's lifetime.

The first and second rows of each channel (address numbers

0, 1, 3, 4, 6, 7, 9, and 10) are the static control latches. The

third row of latches for each channel (address numbers 2, 5,

8, and 11) are the dynamic control latches that are associated

with enabling dynamic functions within the device.

Latch Bank 14 is also useful for those users that do not need

the latch-based programmable feature of the device. This

latch bank could be used in those applications that do not need

to modify the default value of the static latch banks, and that

can afford a global (i.e., not independent) control of the

dynamic signals. In this case, this feature becomes available

Table 3. Device Configuration and Control Latch Descriptions

when ADDR[3:0] is left unchanged with a value of “1110” and

WREN is left asserted. The signals present in DATA[7:0] effec-

tively become global control pins, and for the latch banks 2, 5,

8 and 11.

Static Latch Values

There are some latches in the table that have a static value (ie.

1, 0, or X). The latches that have a ‘1’ or ‘0’ must be configured

with their corresponding value each time that their associated

latch bank is configured. The latches that have an ‘X’ are don’t

cares and can be configured with any value

Name

Signal Description

RXRATEA

RXRATEB

RXRATEC

RXRATED

Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx is used to

select the rate of the RXCLKx± clock output.

When RXRATEx = 1, the RXCLKx± clock outputs are complementary clocks that follow the recovered

clock operating at half the character rate. Data for the associated receive channels should be latched

alternately on the rising edge of RXCLKx+ and RXCLKx–.

When RXRATEx = 0, the RXCLKx± clock outputs are complementary clocks that follow the recovered

clock operating at the character rate. Data for the associated receive channels should be latched on the

rising edge of RXCLKx+ or falling edge of RXCLKx–.

SDASEL1A[1:0]

SDASEL1B[1:0]

SDASEL1C[1:0]

SDASEL1D[1:0]

Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the

SDASEL1x[1:0] latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the

INx1± Primary Differential Serial Data Inputs.

When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.

When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140mV.

When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280mV.

When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420mV.

SDASEL2A[1:0]

SDASEL2B[1:0]

SDASEL2C[1:0]

SDASEL2D[1:0]

Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the

SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the

INx2± Secondary Differential Serial Data Inputs.

When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled

When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140mV.

When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280mV.

When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420mV.

TRGRATEA

TRGRATEB

TRGRATEC

TRGRATED

Training Clock Rate Select. The initialization value of the TRGRATEx latch = 0. TRGRATEx is used to

select the clock multiplier for the training clock input to the associated CDR PLL. When TRGRATEx =

0, the associated TRGCLKx± input is not multiplied before it is passed to the CDR PLL. WhenTRGRATEx

= 1, the TRGCLKx± input is multiplied by 2 before it is passed to the CDR PLL. TRGRATEx = 1 and

SPDSELx = LOW is an invalid state and this combination is reserved.

RXPLLPDA

RXPLLPDB

RXPLLPDC

RXPLLPDD

Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects if the

associated receive channel is enabled or powered-down. When RXPLLPDx = 0, the associated receive

PLL and analog circuitry are powered-down. When RXPLLPDx = 1, the associated receive PLL and

analog circuitry are enabled.

RXBISTA[1:0]

RXBISTB[1:0]

RXBISTC[1:0]

RXBISTD[1:0]

Receive Bist Disable / SMPTE Receive Enable. The initialization value of the RXBISTx[1:0] latch =

11. For SMPTE data reception, RXBISTx[1:0] should not remain in this initialization state (11).

RXBISTx[1:0] selects if receive BIST is disabled or enabled and sets the associated channel for SMPTE

data reception. When RXBISTx[1:0] = 01, the receiver BIST function is disabled and the associated

channel is set to receive SMPTE data. When RXBISTx[1:0] = 10, the receive BIST function is enabled

and the associated channel is set to receive BIST data. RXBISTx[1:0] = 00 and RXBISTx[1:0] = 11 are

invalid states.

ROE2A

ROE2B

ROE2C

ROE2D

Reclocker Secondary Differential Serial Data Output Driver Enable. The initialization value of the

ROE2x latch = 0. ROE2x selects if the ROUT2± secondary differential output drivers are enabled or

disabled. When ROE2x = 1, the associated serial data output driver is enabled allowing data to be

transmitted from the transmit shifter. When ROE2x = 0, the associated serial data output driver is

disabled. When a driver is disabled via the configuration interface, it is internally powered down to reduce

device power. If both serial drivers for a channel are in this disabled state, the associated internal logic

for that channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers.

Document #: 38-02102 Rev. **

Page 14 of 26

CYV15G0404RB

PRELIMINARY

Table 3. Device Configuration and Control Latch Descriptions (continued)

ROE1A

ROE1B

ROE1C

ROE1D

Reclocker Primary Differential Serial Data Output Driver Enable. The initialization value of the

ROE1x latch = 0. ROE1x selects if the ROUT1± primary differential output drivers are enabled or

disabled. When ROE1x = 1, the associated serial data output driver is enabled allowing data to be

transmitted from the transmit shifter. When ROE1x = 0, the associated serial data output driver is

disabled. When a driver is disabled via the configuration interface, it is internally powered down to reduce

device power. If both serial drivers for a channel are in this disabled state, the associated internal logic

for that channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers.

GLEN[11..0]

FGLEN[2..0]

Global Enable. The initialization value of the GLENx latch = 1. The GLENx is used to reconfigure several

channels simultaneously in applications where several channels may have the same configuration.

When GLENx = 1 for a given address, that address is allowed to participate in a global configuration.

When GLENx = 0 for a given address, that address is disabled from participating in a global configuration.

Force Global Enable. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a

GLobal ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated

Global channel, FGLEN forces the global update of the target latch banks.

Device Configuration Strategy

permits it. [Optional step if the default settings match the

desired configuration.]

3. Set the dynamic bank of latches for the target channel.

Enable the Receive PLLs and set each channel for SMPTE

data reception (RXBISTx[1:0] = 01) or BIST data reception

(RXBISTx[1:0] = 10). May be performed using a global

operation, if the application permits it. [Required step.]

The following is a series of ordered events needed to load the

configuration latches on a per channel basis:

1. Pulse RESET Low after device power-up. This operation

resets all four channels.

2. Set the static latch banks for the target channel. May be

performed using a global operation, if the application

Document #: 38-02102 Rev. **

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CYV15G0404RB

PRELIMINARY

Table 4. Device Control Latch Configuration Table

Reset

ADDR Channel Type

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

Value

0

A

S

D

S

D

S

D

S

D

S

D

1

0

X

0

RXRATEA

GLEN0

10111111

(0000b)

1

A

SDASEL2A[1] SDASEL2A[0] SDASEL1A[1] SDASEL1A[0]

X

TRGRATEA

X

GLEN1

GLEN2

GLEN3

GLEN4

GLEN5

GLEN6

GLEN7

GLEN8

GLEN9

10101101

10110011

10111111

10101101

10110011

10111111

10101101

10110011

10111111

10101101

10110011

N/A

(0001b)

2

A

RXBISTA[1]

1

RXPLLPDA

0

RXBISTA[0]

X

ROE2A

ROE1A

(0010b)

3

B

0

RXRATEB

TRGRATEB

X

(0011b)

4

B

SDASEL2B[1] SDASEL2B[0] SDASEL1B[1] SDASEL1B[0]

X

(0100b)

5

B

RXBISTB[1]

1

RXPLLPDB

0

RXBISTB[0]

X

ROE2B

ROE1B

(0101b)

6

C

0

RXRATEC

TRGRATEC

X

(0110b)

7

C

SDASEL2C[1] SDASEL2C[0] SDASEL1C[1] SDASEL1C[0]

X

(0111b)

8

C

D

RXBISTC[1]

1

RXPLLPDC

0

RXBISTC[0]

X

ROE2C

ROE1C

(1000b)

9

0

RXRATED

(1001b)

10

D

SDASEL2D[1] SDASEL2D[0] SDASEL1D[1] SDASEL1D[0]

X

TRGRATED GLEN10

GLEN11

(1010b)

11

D

RXBISTD[1]

1

RXPLLPDD

0

RXBISTD[0]

X

ROE2D

ROE1D

X

(1011b)

12

GLOBAL

MASK

0

X

0

X

RXRATEGL FGLEN0

TRGRATEGL FGLEN1

(1100b)

13

SDASEL2GL[1] SDASEL2GL[0] SDASEL1GL[1] SDASEL1GL[0]

N/A

(1101b)

14

RXBISTGL[1]

D7

RXPLLPDGL

D6

RXBISTGL[0]

D5

X

ROE2GL

D3

ROE1GL

D2

X

FGLEN2

D0

N/A

(1110b)

15

D4

D1

11111111

(1111b)

3-Level Select Inputs

JTAG Support

Each 3-Level select inputs reports as two bits in the scan

register. These bits report the LOW, MID, and HIGH state of

the associated input as 00, 10, and 11 respectively

The CYV15G0404RB contains a JTAG port to allow system

level diagnosis of device interconnect. Of the available JTAG

modes, boundary scan, and bypass are supported. This

capability is present only on the LVTTL inputs and outputs and

the TRGCLKx± clock input. The high-speed serial inputs and

outputs are not part of the JTAG test chain.

JTAG ID

The JTAG device ID for the CYV15G0404RB is ‘0C811069’x.

Table 5. Receive BIST Status Bits

Description

{BISTSTx, RXDx[0],

RXDx[1]}

Receive BIST Status

(Receive BIST = Enabled)

000, 001

BIST Data Compare. Character compared correctly.

BIST Last Good. Last Character of BIST sequence detected and valid.

010

011

Reserved.

100

BIST Last Bad. Last Character of BIST sequence detected invalid.

101

BIST Start. Receive BIST is enabled on this channel, but character compares have not yet

commenced. This also indicates a PLL Out of Lock condition.

110

111

BIST Error. While comparing characters, a mismatch was found in one or more of the character bits.

BIST Wait. The receiver is comparing characters. but has not yet found the start of BIST character to

enable the LFSR.

Document #: 38-02102 Rev. **

Page 16 of 26

CYV15G0404RB

PRELIMINARY

Monitor Data

Receive BIST

Received

Detected LOW

RX PLL

{BISTSTx, RXDx[0],

RXDx[1]} =

Out of Lock

BIST_START (101)

{BISTSTx, RXDx[0], RXDx[1]} =

BIST_WAIT (111)

Start of

BIST Detected

No

Yes, {BISTSTx, RXDx[0], RXDx[1]} =

BIST_DATA_COMPARE (000, 001)

Compare

Next Character

Mismatch

{BISTSTx, RXDx[0], RXDx[1]} =

Match

BIST_DATA_COMPARE (000, 001)

Auto-Abort

Condition

Yes

No

End-of-BIST

State

End-of-BIST

State

No

Yes, {BISTSTx, RXDx[0], RXDx[1]} =

BIST_LAST_BAD (100)

Yes, {BISTSTx, RXDx[0], RXDx[1]} =

BIST_LAST_GOOD (010)

No, {BISTSTx, RXDx[0], RXDx[1]} =

BIST_ERROR (110)

Figure 2. Receive BIST State Machine

Document #: 38-02102 Rev. **

Page 17 of 26

CYV15G0404RB

PRELIMINARY

Static Discharge Voltage..........................................> 2000 V

Maximum Ratings

(per MIL-STD-883, Method 3015)

Above which the useful life may be impaired. User guidelines

Latch-up Current.....................................................> 200 mA

only, not tested

Power-up Requirements

Storage Temperature ..................................–65°C to +150°C

The CYV15G0404RB requires one power-supply. The Voltage

on any input or I/O pin cannot exceed the power pin during

power-up.

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential............... –0.5V to +3.8V

Operating Range

DC Voltage Applied to LVTTL Outputs

in High-Z State .......................................–0.5V to V_CC+ 0.5V

Range

Ambient Temperature

V_CC

+3.3V ±5%

Output Current into LVTTL Outputs (LOW)..................60 mA

DC Input Voltage....................................–0.5V to V_CC+ 0.5V

Commercial

0°C to +70°C

CYV15G0404RB DC Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

LVTTL-compatible Outputs

V_OHT

V_OLT

I_OST

I_OZL

Output HIGH Voltage

Output LOW Voltage

Output Short Circuit Current

I_OH= − 4 mA, V_CC= Min.

I_OL= 4 mA, V_CC= Min.

V_OUT= 0V^[6], V_CC= 3.3V

V_OUT= 0V, V_CC

2.4

V

mA

µA

0.4

–100

20

–20

High-Z Output Leakage Current

LVTTL-compatible Inputs

V_IHT

V_ILT

I_IHT

Input HIGH Voltage

Input LOW Voltage

Input HIGH Current

2.0

–0.5

V_CC+ 0.3

0.8

V

TRGCLKx Input, V_IN= V_CC

Other Inputs, V_IN= V_CC

TRGCLKx Input, V_IN= 0.0V

Other Inputs, V_IN= 0.0V

1.5

+40

–1.5

–40

+200

–200

mA

µA

mA

µA

I_ILT

Input LOW Current

I_IHPDT

I_ILPUT

Input HIGH Current with internal pull-down V_IN= V_CC

Input LOW Current with internal pull-up

V_IN= 0.0V

LVDIFF Inputs: TRGCLKx±

[7]

V_DIFF

Input Differential Voltage

400

1.2

0.0

1.0

V_CC

V_CC/2

mV

V

V_IHHP

Highest Input HIGH Voltage

Lowest Input LOW voltage

Common Mode Range

V_ILLP

V_COMREF

[8]

V_CC– 1.2V

V

3-Level Inputs

V_IHH

V_IMM

V_ILL

I_IHH

I_IMM

I_ILL

Three-Level Input HIGH Voltage

Min. ≤ V_CC≤ Max.

V_IN= V_CC

V_IN= V_CC/2

V_IN= GND

0.87 * V_CC

0.47 * V_CC

0.0

V_CC

0.53 * V_CC

0.13 * V_CC

200

V

µA

Three-Level Input MID Voltage

Three-Level Input LOW Voltage

Input HIGH Current

Input MID current

–50

50

–200

Input LOW current

Differential CML Serial Outputs: ROUTA1±, ROUTA2±, ROUTB1±, ROUTB2±, ROUTC1±, ROUTC2±, ROUTD1±,

ROUTD2±

V_OHC

V_OLC

Output HIGH Voltage

(V_ccReferenced)

100Ω differential load

150Ω differential load

100Ω differential load

150Ω differential load

V

_CC– 0.5

V_CC– 0.2

V

V_CC– 0.5

V_CC– 1.4 V_CC– 0.7

Output LOW Voltage

(V_CCReferenced)

6. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.

7. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when

the true (+) input is more positive than the complement (−) input. A logic-0 exists when the complement (−) input is more positive than true (+) input.

8. The common mode range defines the allowable range of TRGCLKx+ and TRGCLKx− when TRGCLKx+ = TRGCLKx−. This marks the zero-crossing between

the true and complement inputs as the signal switches between a logic-1 and a logic-0.

Document #: 38-02102 Rev. **

Page 18 of 26

CYV15G0404RB

PRELIMINARY

CYV15G0404RB DC Electrical Characteristics (continued)

Parameter

Description

Test Conditions

100Ω differential load

150Ω differential load

Min.

450

560

Max.

900

1000

Unit

mV

V_ODIF

Output Differential Voltage

|(OUT+) − (OUT−)|

Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±, INC1±, INC2±, IND1±, IND2±

[7]

V_DIFFs

V_IHE

V_ILE

I_IHE

I_ILE

Input Differential Voltage |(IN+) − (IN−)|

Highest Input HIGH Voltage

Lowest Input LOW Voltage

Input HIGH Current

Input LOW Current

Common Mode input range

100

1200

V_CC

mV

V

µA

V

V_CC– 2.0

V_IN= V_IHEMax.

V_IN= V_ILEMin.

((V_CC– 2.0V)+0.5)min,

1350

+3.1

–700

+1.25

[9]

VI_COM

(V_CC– 0.5V) max.

Power Supply

Typ.

910

Max.

1270

1320

1270

1320

[10,11]

I_CC

Max Power Supply Current

TRGCLKx Commercial

mA

= MAX

Industrial

[10,11]

I_CC

Typical Power Supply Current

TRGCLKx Commercial

900

= 125 MHz

Industrial

AC Test Loads and Waveforms

3.3V

R_L= 100Ω

R

L

R1

R2

R1 = 590Ω

R2 = 435Ω

C_L≤ 7 pF

(Includes fixture and

probe capacitance)

C_L

(b) CML Output Test Load^{Note 12}

(Includes fixture and

probe capacitance)

(a) LVTTL Output Test Load ^{Note 12}

V_IHE

3.0V

V_IHE

V_ILE

2.0V

0.8V

2.0V

0.8V

80%

V_th= 1.4V

20%

GND

V_ILE

≤ 270 ps

≤ 1 ns

(c) LVTTL Input Test Waveform ^{Note 13}

(d) CML/LVPECL Input Test Waveform

CYV15G0404RB AC Electrical Characteristics

Parameter

Description

Min.

Max

Unit

CYV15G0404RB Receiver LVTTL Switching Characteristics Over the Operating Range

f_RS

RXCLKx± Clock Output Frequency

RXCLKx± Period = 1/f_RS

RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate)

RXCLKx± Rise Time

RXCLKx± Fall Time

9.75

6.66

–1.0

0.3

150

102.56

+1.0

1.2

MHz

ns

t_RXCLKP

t_RXCLKD

t_RXCLKR

t_RXCLKF

t_RXDv–

[14]

1.2

[18]

Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)

Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)

5UI–1.8^[19]

5UI–1.3^[19]

ns

Notes:

9. The common mode range defines the allowable range of INPUT+ and INPUT− when INPUT+ = INPUT−. This marks the zero-crossing between the true and

complement inputs as the signal switches between a logic-1 and a logic-0.

10. Maximum I is measured with V = MAX, T = 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and

CC

A

outputs unloaded.

11. Typical I is measured under similar conditions except with V = 3.3V, T = 25°C, with all channels enabled and one Serial Line Driver per transmit channel

CC

A

sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.

12. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.

13. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.

14. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.

Document #: 38-02102 Rev. **

Page 19 of 26

CYV15G0404RB

PRELIMINARY

CYV15G0404RB AC Electrical Characteristics (continued)

Parameter

t_RXDv+

Description

Status and Data Valid Time to RXCLKx± (RXRATEx = 0)

Status and Data Valid Time to RXCLKx± (RXRATEx = 1)

RECLKOx Clock Frequency

RECLKOx Period=1/f_ROS

RECLKOx Duty Cycle centered at 60% HIGH time

Min.

5UI–1.7^[19]

5UI–2.1^[19]

19.5

Max

Unit

ns

MHz

ns

[18]

f_ROS

t_RECLKO

t_RECLKOD

150

51.28

0

6.66

-1.9

CYV15G0404RB TRGCLKx Switching Characteristics Over the Operating Range

f_TRG

TRGCLKx Clock Frequency

TRGCLKx Period = 1/f_REF

19.5

6.6

150

51.28

MHz

ns

%

TRGCLK

t_TRGH

TRGCLKx HIGH Time (TXRATEx = 1)(Half Rate)

TRGCLKx HIGH Time (TXRATEx = 0)(Full Rate)

TRGCLKx LOW Time (TXRATEx = 1)(Half Rate)

TRGCLKx LOW Time (TXRATEx = 0)(Full Rate)

TRGCLKx Duty Cycle

5.9

2.9^[14]

5.9

t_TRGL

2.9^[14]

30

[20]

t_TRGD

70

2

[14, 15, 16,

t_TRGR

TRGCLKx Rise Time (20%–80%)

ns

17]

[14, 15, 16, 17]

[21]

t_TRGF

t_TRGRX

TRGCLKx Fall Time (20%–80%)

TRGCLKx Frequency Referenced to Received Clock Frequency

2

ns

%

–0.15

+0.15

CYV15G0404RB Bus Configuration Write Timing Characteristics Over the Operating Range

t_DATAH

t_DATAS

t_WRENP

Bus Configuration Data Hold

Bus Configuration Data Setup

Bus Configuration WREN Pulse Width

0

10

ns

CYV15G0404RB JTAG Test Clock Characteristics Over the Operating Range

f_TCLK

t_TCLK

JTAG Test Clock Frequency

JTAG Test Clock Period

20

MHz

ns

50

30

CYV15G0404RB Device RESET Characteristics Over the Operating Range

t_RSTDevice RESET Pulse Width

CYV15G0404RB Reclocker Serial Output Characteristics Over the Operating Range

ns

Parameter

Description

Condition

Min.

5128

50

100

180

50

Max.

660

270

500

1000

270

Unit

ps

t_B

Bit Time

[14]

t_RISE

CML Output Rise Time 20−80% (CML Test Load)

CML Output Fall Time 80−20% (CML Test Load)

SPDSELx = HIGH

SPDSELx = MID

SPDSELx =LOW

SPDSELx = HIGH

SPDSELx = MID

SPDSELx =LOW

[14]

t_FALL

100

180

500

1000

Notes:

15. The ratio of rise time to falling time must not vary by greater than 2:1.

16. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.

17. All transmit AC timing parameters measured with 1ns typical rise time and fall time.

18. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.

19. Receiver UI (Unit Interval) is calculated as 1/(f

* 20) (when TRGRATEx = 1) or 1/(f

* 10) (when TRGRATEx = 0). In an operating link this is equivalent to t .

TRG

T

R

G

B

20. The duty cycle specification is a simultaneous condition with the t

cycle cannot be as large as 30%–70%.

and t

parameters. This means that at faster character rates the TRGCLKx± duty

REFH

REFL

21. TRGCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.

TRGCLKx± must be within ±1500PPM(±0.15%) of the transmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver channel

necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be

within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.

Document #: 38-02102 Rev. **

Page 20 of 26

CYV15G0404RB

PRELIMINARY

PLL Characteristics

Min

Parameter

Description

Condition

.

Typ.

Max. Unit

CYV15G0404RB Reclocker Output PLL Characteristics

[14, 22]

t_JRGENSD

Reclocker Jitter Generation - SD Data Rate

Reclocker Jitter Generation - HD Data Rate

TRGCLKx = 27 MHz

133

107

ps

[14, 22]

t_JRGENHD

TRGCLKx = 148.5

MHz

CYV15G0404RB Receive PLL Characteristics Over the Operating Range

t_RXLOCK

Receive PLL lock to input data stream (cold start)

Receive PLL lock to input data stream

Receive PLL Unlock Rate

376k

46

UI

t_RXUNLOCK

Capacitance ^[14]

Parameter

Description

Test Conditions

Max.

Unit

C_INTTL

TTL Input Capacitance

T_A= 25°C, f₀= 1 MHz, V_CC= 3.3V

7

pF

C_INPECL

PECL input Capacitance

T_A= 25°C, f₀= 1 MHz, V_CC= 3.3V

4

pF

Switching Waveforms for the CYV15G0404RB HOTLink II Receiver

Receive Interface

t_RXCLKP

Read Timing

RXRATEx = 0

RXCLKx+

RXCLKx-

RXDx[9:0]

t

RXDV

–

t

RXDV+

Receive Interface

Read Timing

t_RXCLKP

RXRATEx = 1

RXCLKx+

RXCLKx-

t

RXDV

–

RXDx[9:0]

t

RXDV+

Notes:

22. Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide-bandwidth digital sampling oscilloscope. The

measurement was recorded after 10,000 histogram hits, time referenced to REFCLKx± of the transmit channel.

Document #: 38-02102 Rev. **

Page 21 of 26

CYV15G0404RB

PRELIMINARY

CYV15G0404RB HOTLink II Bus Configuration Switching Waveforms

Bus Configuration

Write Timing

ADDR[3:0]

DATA[7:0]

t_WRENP

t_DATAS

WREN

t_DATAH

Document #: 38-02102 Rev. **

Page 22 of 26

CYV15G0404RB

PRELIMINARY

Table 6. Package Coordinate Signal Allocation

Ball

ID

Signal Name

INC1–

ROUTC1–

INC2–

ROUTC2–

VCC

IND1–

ROUTD1–

GND

IND2–

ROUTD2–

INA1–

ROUTA1–

GND

INA2–

ROUTA2–

VCC

INB1–

ROUTB1–

INB2–

ROUTB2–

INC1+

ROUTC1+

INC2+

ROUTC2+

VCC

IND1+

ROUTD1+

GND

IND2+

ROUTD2+

INA1+

ROUTA1+

GND

INA2+

ROUTA2+

VCC

INB1+

ROUTB1+

INB2+

Signal Type

CML IN

CML OUT

CML IN

CML OUT

POWER

CML IN

CML OUT

GROUND

CML IN

CML OUT

CML IN

CML OUT

GROUND

CML IN

CML OUT

POWER

CML IN

CML OUT

CML IN

CML OUT

CML IN

CML OUT

CML IN

CML OUT

POWER

CML IN

CML OUT

GROUND

CML IN

CML OUT

CML IN

CML OUT

GROUND

CML IN

CML OUT

POWER

CML IN

CML OUT

CML IN

ID

Signal Name

ULCC

GND

Signal Type

LVTTL IN PU

GROUND

Signal Name

Signal Type

POWER

LVTTL OUT

GROUND

LVTTL IN PU

GROUND

3-LEVEL SEL

NO CONNECT

3-LEVEL SEL

LVTTL OUT

GROUND

LVTTL OUT

PECL IN

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

C01

C02

C03

C07

C08

C09

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

E01

E02

E03

E04

E17

E18

E19

E20

F01

F17

F18

F19

F20

G01

G02

G03

G04

G17

G18

G19

G20

H01

H02

H03

H04

H17

H18

H19

H20

J01

VCC

RXDB[0]

RECLKOB

RXDB[1]

GND

WREN

GND

SPDSELB

NC

SPDSELA

RXDB[3]

GND

BISTSTB

RXDB[2]

RXDB[7]

RXDB[4]

RXDC[4]

DATA[7]

DATA[5]

DATA[3]

DATA[1]

GND

VCC

SPDSELD

VCC

LDTDEN

TRST

GND

TDO

TCLK

RESET

INSELD

INSELA

VCC

ULCA

SPDSELC

GND

DATA[6]

DATA[4]

DATA[2]

DATA[0]

GND

ULCB

VCC

NC

VCC

LVTTL IN PU

GROUND

POWER

3-LEVEL SEL

POWER

LVTTL IN PU

GROUND

LVTTL 3-S OUT

LVTTL IN PD

LVTTL IN PU

LVTTL IN

POWER

LVTTL IN PU

3-LEVEL SEL

GROUND

LVTTL IN PU

GROUND

LVTTL IN PU

POWER

NO CONNECT

POWER

LVTTL IN PD

POWER

LVTTL OUT

J02

J03

J04

J17

J18

J19

J20

K01

K02 TRGCLKC–

K03

K04

K17

K18

K19

K20

L01

GND

RXDB[5]

RXDB[6]

RXDB[9]

LFIB

GROUND

SCANEN2

TMEN3

VCC

LVTTL OUT

PECL IN

LVTTL OUT

GROUND

LVTTL OUT

VCC

RXDC[8]

RXDC[5]

L02 TRGCLKC+

L03

L04

L17

L18

L19

LFIC

GND

RXDB[8]

RXCLKB+

RXCLKB–

ROUTB2+

TDI

TMS

INSELC

CML OUT

LVTTL IN PU

LVTTL IN

Document #: 38-02102 Rev. **

Page 23 of 26

CYV15G0404RB

PRELIMINARY

Table 6. Package Coordinate Signal Allocation (continued)

Ball

ID

Signal Name

INSELB

VCC

ULCD

VCC

REPDOC

Signal Type

LVTTL IN

POWER

LVTTL IN PU

POWER

LVTTL OUT

PECL IN

ID

Signal Name

RXDC[9]

VCC

Signal Type

LVTTL OUT

POWER

Signal Name

Signal Type

GROUND

LVTTL OUT

POWER

LVTTL OUT

GROUND

LVTTL IN PU

LVTTL OUT

GROUND

POWER

C04

C05

C06

M03

M04

F02

F03

F04

U03

U04

U05

U06

U07

U08

U09

U10

L20

M01

M02

W03

W04

W05

W06

W07

W08

W09

W10

W11

W12

W13

W14

W15

W16

W17

GND

RXDC[6]

RXDC[7]

LFID

RXCLKD–

VCC

RXDD[6]

RXDD[0]

GND

ADDR [3]

ADDR [1]

RXCLKA+

REPDOA

GND

VCC

RXDD[4]

RXDD[3]

GND

ADDR [0]

POWER

M17 TRGCLKB+

M18 TRGCLKB–

LVTTL OUT

GROUND

LVTTL IN PU

PECL IN

GROUND

POWER

LVTTL OUT

POWER

LVTTL OUT

POWER

M19

M20

N01

N02

N03

N04

N17

N18

N19

N20

P01

P02

P03

P04

P17

P18

P19

P20

R01

R02

R03

R04

R17

R18

R19

R20

T01

T02

T03

T04

T17

T18

T19

T20

U01

U02

REPDOB

GND

LVTTL OUT

GROUND

LVTTL OUT

GROUND

LVTTL OUT

POWER

U11 TRGCLKD–

U12

U13

U14

U15

U16

U17

U18

U19

U20

V01

V02

V03

V04

V05

V06

V07

V08

V09

V10

GND

VCC

RXDA[4]

VCC

BISTSTA

RXDA[0]

VCC

GND

VCC

LFIA

GND

POWER

LVTTL OUT

PECL IN

LVTTL OUT

POWER

RXDC[3]

RXDC[2]

RXDC[1]

RXDC[0]

GND

BISTSTC

RECLKOC

RXCLKC+

RXCLKC–

VCC

W18 TRGCLKA+

W19

W20

Y01

Y02

Y03

Y04

Y05

Y06

Y07

Y08

Y09

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

RXDA[6]

RXDA[3]

VCC

POWER

LVTTL OUT

POWER

VCC

POWER

RXDD[9]

RXCLKD+

VCC

RXDD[7]

RXDD[2]

GND

RECLKOD

NC

GND

RXCLKA–

GND

LVTTL OUT

POWER

RXDD[8]

VCC

RXDD[5]

RXDD[1]

GND

LVTTL OUT

GROUND

LVTTL OUT

LVTTL IN PU

PECL IN

LVTTL OUT

GROUND

POWER

LVTTL OUT

GROUND

LVTTL OUT

NO CONNECT

GROUND

LVTTL OUT

GROUND

POWER

LVTTL OUT

PECL IN

LVTTL OUT

BISTSTD

ADDR [2]

VCC

V11 TRGCLKD+

V12

V13

V14

V15

V16

V17

V18

V19

V20

W01

W02

RECLKOA

GND

VCC

RXDA[9]

RXDA[5]

RXDA[2]

RXDA[1]

VCC

GND

VCC

REPDOD

POWER

LVTTL OUT

POWER

Y18 TRGCLKA–

Y19

Y20

RXDA[8]

RXDA[7]

VCC

POWER

VCC

POWER

Document #: 38-02102 Rev. **

Page 24 of 26

CYV15G0404RB

PRELIMINARY

Ordering Information

Operating

Range

Commercial

Speed

Standard

Ordering Code

CYV15G0404RB-BGC

Package Name

BL256

Package Type

256-Ball Thermally Enhanced Ball Grid Array

Package Diagram

256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256

51-85123-*E

HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names

mentioned in this document may be the trademarks of their respective holders.

Document #: 38-02102 Rev. **

Page 25 of 26

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges

CYV15G0404RB

PRELIMINARY

Document History Page

Document Title: CYV15G0404RB Independent Clock Quad HOTLink II™ Deserializing Reclocker

Document Number: 38-02102

ISSUE

ORIG. OF

REV.

ECN NO.

DATE

CHANGE

DESCRIPTION OF CHANGE

**

246850

See ECN

FRE

New Data Sheet

Document #: 38-02102 Rev. **

Page 26 of 26

厂商	型号	描述	页数
CYPRESS	CYV15G0100EQ	准专业型视频电缆均衡器[ Prosumer Video Cable Equalizer ]	10 页
CYPRESS	CYV15G0100EQ-SXC	准专业型视频电缆均衡器[ Prosumer Video Cable Equalizer ]	10 页
CYPRESS	CYV15G0101DXB	单通道的HOTLink收发器[ Single-channel HOTLink Transceiver ]	39 页
CYPRESS	CYV15G0101DXB-BBC	单通道的HOTLink收发器[ Single-channel HOTLink Transceiver ]	39 页
CYPRESS	CYV15G0101DXB-BBI	单通道的HOTLink收发器[ Single-channel HOTLink Transceiver ]	39 页
CYPRESS	CYV15G0101DXB-BBXC	单通道的HOTLink II ™收发器[ Single-channel HOTLink II⑩ Transceiver ]	39 页
CYPRESS	CYV15G0101DXB-BBXI	单通道的HOTLink II ™收发器[ Single-channel HOTLink II⑩ Transceiver ]	39 页
CYPRESS	CYV15G0101EQ	多码率视频电缆均衡器（ SOIC ）[ Multi-Rate Video Cable Equalizer (SOIC) ]	10 页
CYPRESS	CYV15G0101EQ-SXC	多码率视频电缆均衡器（ SOIC ）[ Multi-Rate Video Cable Equalizer (SOIC) ]	10 页
CYPRESS	CYV15G0101EQ_07	多速率视频电缆均衡器[ Multi Rate Video Cable Equalizer ]	10 页