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HYMR1864-653

型号：

HYMR1864-653

品牌：

HYNIX[ HYNIX SEMICONDUCTOR ]

页数：

10 页

PDF大小：

111 K

下载PDF手册
Direct Rambus™ RIMM™ Module  
128 MBytes (64M x 16/18) based on 4Mx16/18  
Key Timing Parameters/Part Numbers  
Overview  
The following table lists the frequency and latency bins  
available from RIMM modules. An optional -LP designator  
is used to indicate low power modules.  
The Direct Rambus™ RIMM™ module is a general purpose  
high-performance memory subsystem suitable for use in a  
broad range of applications including computer memory,  
personal computers, workstations, and other applications  
where high bandwidth and low latency are required.  
I/O Freq. t (Row Access  
Part  
rac  
Organization  
MHz  
Time) ns  
Number  
The 128 MB Direct Rambus RIMM module consists of  
sixteen 64M Direct Rambus DRAM (Direct RDRAM™ )  
devices. These are extremely high-speed CMOS DRAMs  
organized as 4M words by 16 or 18 bits. The use of Rambus  
Signaling Level (RSL) technology permits 600MHz or  
800MHz transfer rates while using conventional system and  
board design technologies. Direct RDRAM devices are  
capable of sustained data transfers at 1.25 ns per two bytes  
(10ns per sixteen bytes).  
64M x 16  
64M x 16  
64M x 16  
64M x 18  
64M x 18  
64M x 18  
600  
800  
800  
600  
800  
800  
53  
45  
40  
53  
45  
40  
HYMR1664-653  
HYMR1664-845  
HYMR1664-840  
HYMR1864-653  
HYMR1864-845  
HYMR1864-840  
Form Factor  
The architecture of the Direct RDRAM allows the highest  
sustained bandwidth for multiple, simultaneous randomly  
addressed memory transactions. The separate control and  
data buses with independent row and column control yield  
over 95% bus efficiency. The Direct RDRAM's sixteen  
banks support up to four simultaneous transactions.  
The Direct Rambus RIMM modules are offered in a 184-pin  
1mm pin pitch form factor suitable for desktop and other  
system applications.  
Features  
184-pin 1mm pin spacing  
Card Size: 133.35mm x 31.75mm x 1.27mm  
(5.25” x 1.25” x 0.050”)  
128 MB Direct RDRAM storage  
Each RDRAM has 16 banks, for 256 banks total on  
module  
Gold plated contacts  
RDRAMs use Chip Scale Package (CSP)  
Serial Presence Detect support  
Operates from a 2.5 volt supply (±5%)  
Low power and powerdown self refresh modes  
Separate Row and Column buses for higher efficiency  
Rev.0.2 / Jan. 99  
1
Preliminary  
HYMR1664/1864 Series  
Pinouts and Pin Names  
Pin  
A1  
Pin Name  
Gnd  
Pin  
B1  
Pin Name  
Gnd  
Pin  
Pin Name  
NC  
Pin  
B47  
Pin Name  
NC  
A47  
A48  
A49  
A50  
A51  
A52  
A53  
A54  
A55  
A56  
A57  
A58  
A59  
A60  
A61  
A62  
A63  
A64  
A65  
A66  
A67  
A68  
A69  
A70  
A71  
A72  
A73  
A74  
A75  
A76  
A77  
A78  
A79  
A80  
A81  
A82  
A83  
A84  
A85  
A86  
A87  
A88  
A89  
A90  
A91  
A92  
A2  
LDQA8  
Gnd  
B2  
LDQA7  
Gnd  
NC  
B48  
B49  
B50  
B51  
B52  
B53  
B54  
B55  
B56  
B57  
B58  
B59  
B60  
B61  
B62  
B63  
B64  
B65  
B66  
B67  
B68  
B69  
B70  
B71  
B72  
B73  
B74  
B75  
B76  
B77  
B78  
B79  
B80  
B81  
B82  
B83  
B84  
B85  
B86  
B87  
B88  
B89  
B90  
B91  
B92  
NC  
A3  
B3  
NC  
NC  
A4  
LDQA6  
Gnd  
B4  
LDQA5  
Gnd  
NC  
NC  
A5  
B5  
Vref  
Vref  
A6  
LDQA4  
Gnd  
B6  
LDQA3  
Gnd  
Gnd  
Gnd  
A7  
B7  
SCL  
SA0  
A8  
LDQA2  
Gnd  
B8  
LDQA1  
Gnd  
Vdd  
Vdd  
A9  
B9  
SDA  
SA1  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
A32  
A33  
A34  
A35  
A36  
A37  
A38  
A39  
A40  
A41  
A42  
A43  
A44  
A45  
A46  
LDQA0  
Gnd  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
B26  
B27  
B28  
B29  
B30  
B31  
B32  
B33  
B34  
B35  
B36  
B37  
B38  
B39  
B40  
B41  
B42  
B43  
B44  
B45  
B46  
LCFM  
Gnd  
SVdd  
SWP  
SVdd  
SA2  
LCTMN  
Gnd  
LCFMN  
Gnd  
Vdd  
Vdd  
RSCK  
Gnd  
RCMD  
Gnd  
LCTM  
Gnd  
NC  
Gnd  
RDQB7  
Gnd  
RDQB8  
Gnd  
NC  
LROW2  
Gnd  
Gnd  
RDQB5  
Gnd  
RDQB6  
Gnd  
LROW1  
Gnd  
LROW0  
Gnd  
RDQB3  
Gnd  
RDQB4  
Gnd  
LCOL4  
Gnd  
LCOL3  
Gnd  
RDQB1  
Gnd  
RDQB2  
Gnd  
LCOL2  
Gnd  
LCOL1  
Gnd  
RCOL0  
Gnd  
RDQB0  
Gnd  
LCOL0  
Gnd  
LDQB0  
Gnd  
RCOL2  
Gnd  
RCOL1  
Gnd  
LDQB1  
Gnd  
LDQB2  
Gnd  
RCOL4  
Gnd  
RCOL3  
Gnd  
LDQB3  
Gnd  
LDQB4  
Gnd  
RROW1  
Gnd  
RROW0  
Gnd  
LDQB5  
Gnd  
LDQB6  
Gnd  
NC  
RROW2  
Gnd  
LDQB7  
Gnd  
LDQB8  
Gnd  
Gnd  
RCTM  
Gnd  
NC  
LSCK  
Vcmos  
SOUT  
Vcmos  
NC  
LCMD  
Vcmos  
SIN  
Gnd  
RCTMN  
Gnd  
RCFMN  
Gnd  
Vcmos  
NC  
RDQA0  
Gnd  
RCFM  
Gnd  
Gnd  
Gnd  
RDQA2  
Gnd  
RDQA1  
Gnd  
NC  
NC  
Vdd  
Vdd  
RDQA4  
Gnd  
RDQA3  
Gnd  
Vdd  
Vdd  
NC  
NC  
RDQA6  
Gnd  
RDQA5  
Gnd  
NC  
NC  
NC  
NC  
RDQA8  
Gnd  
RDQA7  
Gnd  
NC  
NC  
Page 2  
Rev. 0.2 / Jan. 99  
HYMR1664/1864 Series  
Preliminary  
Pin Definition  
Signal  
Pins  
I/O  
Type  
Description  
Gnd  
A1, A3, A5, A7, A9, A11, A13, A15,  
A17, A19, A21, A23, A25, A27, A29,  
A31, A33, A39, A52, A60, A62, A64,  
A66, A68, A70, A72, A74, A76, A78,  
A80, A82, A84, A86, A88, A90, A92,  
B1, B3, B5, B7, B9, B11, B13, B15,  
B17, B19, B21, B23, B25, B27, B29,  
B31, B33, B39, B52, B60, B62, B64,  
B66, B68, B70, B72, B74, B76, B78,  
B80, B82, B84, B86, B88, B90, B92  
Ground reference for RDRAM core and interface. 72  
pins.  
LCFM  
B10  
Clock from master. Interface clock used for receiving  
RSL signals from the Channel. Positive polarity.  
I
I
I
I
I
I
RSL  
RSL  
LCFMN  
LCMD  
B12  
Clock from master. Interface clock used for receiving  
RSL signals from the Channel. Negative polarity.  
B34  
Serial Command Pin. Pin used to read from and write to  
the control registers. Also used for power management.  
V
CMOS  
LCOL4..  
LCOL0  
A20, B20, A22, B22, A24  
Column bus. 5-pin bus containing control and address  
information for column accesses.  
RSL  
LCTM  
A14  
Clock to master. Interface clock used for transmitting  
RSL signals to the Channel. Positive polarity.  
RSL  
RSL  
LCTMN  
A12  
Clock to master. Interface clock used for transmitting  
RSL signals to the Channel. Negative polarity.  
LDQA8..  
LDQA0  
A2, B2, A4, B4, A6, B6, A8, B8, A10  
Data bus A. A 9-pin bus carrying a byte of read or write  
data between the Channel and the RDRAM. LDQA8 is  
non-functional on x16 devices  
I/O  
I/O  
RSL  
LDQB8..  
LDQB0  
B32, A32, B30, A30, B28, A28, B26,  
A26, B24  
Data bus B. A 9-bit bus carrying a byte of read or write  
data between the Channel and the RDRAM. LDQB8 is  
non-functional on x16 devices.  
RSL  
RSL  
LROW2..  
LROW0  
B16, A18, B18  
A34  
Row bus. 3-pin bus containing control and address infor-  
mation for row accesses.  
I
I
LSCK  
Clock input. Pin used to read from and write to the con-  
trol registers.  
V
CMOS  
NC  
A16, B14, A38, B38, A40, B40, A43,  
B43, A44, B44, A45, B45, A46, B46,  
A47, B47, A48, B48, A49, B49, A50,  
B50, A77, B79  
These pins are not connected. These 24 pins are all  
reserved for future use.  
RCFM  
B83  
Clock from master. Interface clock used for receiving  
RSL signals from the Channel. Positive polarity.  
I
I
RSL  
RSL  
RCFMN  
B81  
Clock from master. Interface clock used for receiving  
RSL signals from the Channel. Negative polarity.  
Rev.0.2 / Jan. 99  
Page 3  
Preliminary  
HYMR1664/1864 Series  
Signal  
Pins  
I/O  
I
Type  
Description  
RCMD  
B59  
Serial Command Input. Pin used to read from and write  
to the control registers. Also used for power manage-  
ment.  
V
CMOS  
RCOL4..  
RCOL0  
A73, B73, A71, B71, A69  
Column bus. 5-pin bus containing control and address  
information for column accesses.  
I
I
I
RSL  
RSL  
RSL  
RCTM  
A79  
A81  
Clock to master. Interface clock used for transmitting  
RSL signals to the Channel. Positive polarity.  
RCTMN  
Clock to master. Interface clock used for transmitting  
RSL signals to the Channel. Negative polarity.  
RDQA8..  
RDQA0  
A91, B91, A89, B89, A87, B87, A85,  
B85, A83  
Data bus A. A 9-pin bus carrying a byte of read or write  
data between the Channel and the RDRAM. RDQA8 is  
non-functional on x16 devices.  
I/O  
I/O  
RSL  
RDQB8..  
RDQB0  
B61, A61, B63, A63, B65, A65, B67,  
A67, B69  
Data bus B. A 9-bit bus carrying a byte of read or write  
data between the Channel and the RDRAM. RDQB8 is  
non-functional on x16 devices.  
RSL  
RSL  
RROW2..  
RROW0  
B77, A75, B75  
A59  
Row bus. 3-pin bus containing control and address infor-  
mation for row accesses.  
I
I
RSCK  
Clock input. Pin used to read from and write to the con-  
trol registers.  
V
CMOS  
SA0  
SA1  
SA2  
SCL  
SDA  
SIN  
B53  
B55  
B57  
A53  
A55  
B36  
Serial Presence Detect Address 0.  
Serial Presence Detect Address 1.  
Serial Presence Detect Address 2.  
Serial Presence Detect Clock.  
I
I
SV  
DD  
DD  
DD  
DD  
DD  
SV  
SV  
SV  
SV  
I
I
Serial Presence Detect Data (Open Collector I/O).  
I/O  
Serial I/O. Pin for reading from and writing to the control  
registers. Attaches to SIO0 of the first RDRAM on the  
module.  
I/O  
I/O  
V
V
CMOS  
CMOS  
SOUT  
A36  
Serial I/O. Pin for reading from and writing to the control  
registers. Attaches to SIO1 of the last RDRAM on the  
module.  
SV  
A56, B56  
SPD Voltage. Used for signals SCL, SDA, SWE, SA0,  
SA1 and SA2.  
DD  
SWP  
A57  
Serial Presence Detect Write Protect (active high). When  
low, the SPD can be written as well as read.  
I
SV  
DD  
V
A35, B35, A37, B37  
CMOS I/O Voltage. Used for signals CMD, SCK, SIN,  
SOUT.  
CMOS  
Vdd  
Vref  
A41, A42, A54, A58, B41, B42, B54,  
B58  
Supply voltage for the RDRAM core and interface logic.  
A51, B51  
Logic threshold reference voltage for RSL signals.  
Page 4  
Rev. 0.2 / Jan. 99  
HYMR1664/1864 Series  
Preliminary  
Functional Diagram  
Vdd  
2 per  
RDRAM  
U1  
U2  
SIO0  
SIO1  
SCK  
CMD  
Vref  
0.1mF  
Direct RDRAM (64/72Mb)  
Direct RDRAM (64/72Mb)  
Direct RDRAM (64/72Mb)  
Gnd  
VREF  
1 per  
2 RDRAMs  
Plus one  
Near Connector  
0.1mF  
SIO0  
SIO1  
SCK  
CMD  
Vref  
Gnd  
VCMOS  
1 per  
2 RDRAMs  
0.1 mF  
SIO0  
SIO1  
SCK  
CMD  
Vref  
U3  
Gnd  
.
.
.
.
.
.
SIO0  
SIO1  
SCK  
CMD  
Vref  
U16  
Direct RDRAM (64/72Mb)  
Note 1: Rambus Channel signals form a loop through  
the RIMM module, with the exception of the SIO chain.  
SVDD  
Serial Presence Detect  
SVDD  
Vcc  
A1  
SCL  
WP  
A0  
SDA  
A2  
SCL  
SWP  
SDA  
0.1 mF  
U0  
SA0  
SA1  
SA2  
47K Ohm  
Gnd  
Rev.0.2 / Jan. 99  
Page 5  
Preliminary  
HYMR1664/1864 Series  
Absolute Maximum Ratings  
Symbol  
Parameter  
Min  
Max  
Unit  
V
V
Voltage applied to any RSL or CMOS pin with respect to Gnd  
Voltage on VDD with respect to Gnd  
Storage temperature  
- 0.3  
- 0.5  
- 50  
V
V
+ 0.3  
V
V
I,ABS  
DD  
DD  
+ 1.0  
DD,ABS  
STORE  
T
100  
°C  
DC Recommended Electrical Conditions  
Symbol  
Parameter and Conditions  
Min  
Max  
Unit  
V
V
Supply voltage  
2.50 - 0.13  
2.50 + 0.13  
V
DD  
CMOS I/O pin power supply - 2.5V controllers:  
- for 1.8V controllers:  
2.5 - 0.13  
1.8 - 0.1  
2.5 + 0.25  
1.8 + 0.2  
V
V
CMOS  
V
V
V
V
V
V
V
Reference voltage  
1.4 - 0.2  
1.4 + 0.2  
V
V
REF  
RSL input low voltage  
RSL input high voltage  
CMOS input low voltage  
CMOS input high voltage  
V
- 0.5  
V
- 0.2  
IL  
REF  
REF  
REF  
REF  
V
+ 0.2  
V
+ 0.5  
V
IH  
- 0.3  
0.5V  
- 0.25  
V
IL,CMOS  
IH,CMOS  
OL,CMOS  
OH,CMOS  
CMOS  
0.5V  
+ 0.25  
V
+ 0.3  
V
CMOS  
CMOS  
CMOS output low voltage @ I  
= 1mA  
0.3  
V
OL,CMOS  
CMOS output high voltage @ I  
= -0.25mA  
V
- 0.3  
V
OH,CMOS  
CMOS  
I
I
I
V
current @ V  
REF,MAX  
-160  
-160  
-10.0  
160  
160  
10.0  
mA  
mA  
mA  
REF  
REF  
CMOS input leakage current @ (0 £ V  
CMOS input leakage current @ (0 £ V  
£ V  
£ V  
)
DD  
SCK,CMD  
SIN,SOUT  
CMOS  
CMOS  
)
DD  
AC Electrical Specifications  
Symbol  
Parameter and Conditions  
Min  
Max  
Unit  
Z
Module Impedance  
25.2  
-
30.8  
2.1  
Ohms  
ns  
T
Propagation Delay, all RSL signals  
PD  
a
DT  
DT  
Propagation delay variation of RSL signals with respect to an average clock delay  
-0.01  
-0.1  
0.01  
0.1  
ns  
PD  
Propagation delay variation of SCK and CMD signals with respect to an average clock  
ns  
PD-CMOS  
a
delay  
V /V  
Attenuation Limit  
13.5  
0.8  
1
%
%
%
a
IN  
V
V
/V  
Forward crosstalk coefficient (300ps input risetime 20%-80%)  
Backward crosstalk coefficient (300ps input risetime 20%-80%)  
XF IN  
/V  
XB IN  
a. Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN).  
Page 6  
Rev. 0.2 / Jan. 99  
HYMR1664/1864 Series  
Preliminary  
IDD - VDD Supply Current Profile  
-600  
Max  
-800  
Max  
I
RIMM module power test conditions  
Unit  
DD  
a
I
I
I
I
I
I
I
All RDRAMs in powerdown, self-refresh mode  
All RDRAMs in NAP mode  
TBD/TBD  
TBD  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
DD1  
DD2  
DD3  
DD4  
DD5  
DD6  
DD7  
All RDRAMs in Standby mode, no commands  
All RDRAMs in Active mode, no commands  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
All RDRAMs running refresh cycles, with t = t  
RC  
RC,MIN  
All RDRAMs running refresh cycles, with t = t /# of rows  
RC  
REF  
One RDRAM cycling t = min, 1 bank, no COL packets, remainder of RDRAMs in  
RC  
Standby  
I
One RDRAM cycling t = min, 1 bank, two dualocts per activate (32-byte transfers),  
remainder of RDRAMs in Standby  
TBD  
TBD  
TBD  
TBD  
mA  
mA  
DD8  
DD9  
RC  
I
One RDRAM burst read/write, 1 bank open, full bandwidth, COL address changing every  
dualoct, remainder of RDRAMs in Standby  
a. For modules with a -LP designator.  
ICMOS - VCMOS Supply Current Profile  
I
RIMM module power test conditions  
Max  
Unit  
CMOS  
I
I
I
Current when RDRAMs are in powerdown, self-refresh state  
TBD  
TBD  
TBD  
mA  
mA  
mA  
CMOS1  
CMOS2  
CMOS3  
Current when CMOS pins are used for register read/write operations (f=1MHz)  
Current when CMOS pins are used for power management operations (f=100MHz)  
Rev.0.2 / Jan. 99  
Page 7  
Preliminary  
HYMR1664/1864 Series  
Timing Parameters  
The following timing parameters are from the RDRAMs  
pins, not the RIMM. Please refer to the RDRAM datasheet  
for detailed timing diagrams.  
Min  
-40  
Min  
-45  
Min  
-53  
Parameter Description  
Max  
Units  
-800  
-800  
-600  
t
t
Row Cycle time of RDRAM banks -the interval between ROWA packets  
with ACT commands to the same bank.  
28  
28  
28  
-
-
t
RC  
CYCLE  
RAS-asserted time of RDRAM bank - the interval between ROWA  
packet with ACT command and next ROWR packet with PRER com-  
mand to the same bank.  
20  
20  
20  
t
t
t
RAS  
CYCLE  
t
t
Row Precharge time of RDRAM banks - the interval between ROWR  
8
8
8
8
8
8
-
-
RP  
PP  
CYCLE  
CYCLE  
a
packet with PRER command and next ROWA packet with ACT com-  
mand to the same bank.  
Precharge-to-precharge time of RDRAM device - the interval between  
a
successive ROWR packets with PRER commands to any banks of the  
same device.  
t
t
RAS-to-RAS time of RDRAM device - the interval between successive  
ROWA packets with ACT commands to any banks of the same device.  
8
7
8
9
8
7
-
-
t
t
RR  
CYCLE  
RAS-to-CAS Delay - the interval from ROWA packet with ACT com-  
mand to COLC packet with RD or WR command). Note - the RAS-to-  
RCD  
CYCLE  
CAS delay seen by the RDRAM core (t  
) is equal to t  
RCD,CORE  
RCD,CORE  
= 1 + t  
because of differences in the row and column paths through  
RCD  
the RDRAM interface.  
t
CAS Access delay - the minimum interval from RD command to Q read  
data.  
8
8
8
12  
t
CAC  
CYCLE  
t
t
CAS Write Delay (interval from WR command to D write data.  
6
4
6
4
6
4
6
-
t
t
CWD  
CC  
CYCLE  
CAS-to-CAS time of RDRAM bank - the interval between successive  
COLC commands).  
CYCLE  
t
t
Length of ROWA, ROWR, COLC, COLM or COLX packet.  
4
8
4
8
4
8
4
-
t
t
PACKET  
RTR  
CYCLE  
Interval from COLC packet with WR command to COLC packet which  
causes retire, and to COLM packet with bytemask.  
CYCLE  
t
The interval (offset) from COLC packet with RDA command, or from  
COLC packet with retire command (after WRA automatic precharge), or  
from COLX packet with PREX command to the equivalent ROWR  
packet with PRER.  
4
4
4
4
t
OFFP  
CYCLE  
t
t
Interval from last COLC packet with RD command to ROWR packet  
with PRER.  
4
4
4
4
4
4
-
-
t
t
RDP  
RTP  
CYCLE  
Interval from last COLC packet with automatic retire command to  
ROWR packet with PRER.  
CYCLE  
a. Or equivalent PREC or PREX command.  
Page 8  
Rev. 0.2 / Jan. 99  
HYMR1664/1864 Series  
Preliminary  
Serial Presence Detect Contents  
To be determined  
Layout Drawing  
The following defines the RIMM module dimensions. All units are in millimeters with inches in brackets[ ], where appro-  
priate.  
The maximum height of the module is 31.75mm(1.25”).  
Rev.0.2 / Jan. 99  
Page 9  
Preliminary  
HYMR1664/1864 Series  
Page 10  
Rev. 0.2 / Jan. 99  
厂商 型号 描述 页数 下载

ETC

 		HYM22100S-60 X8快速页模式DRAM模块\n[ x8 Fast Page Mode DRAM Module ] 9 页

ETC

 		HYM22100S-70 X8快速页模式DRAM模块\n[ x8 Fast Page Mode DRAM Module ] 9 页

ETC

 		HYM22100S-80 X8快速页模式DRAM模块\n[ x8 Fast Page Mode DRAM Module ] 9 页

INFINEON

 		HYM321000GS-50 1M ×32位动态RAM模块2M ×16位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module ] 10 页

INFINEON

 		HYM321000GS-60 1M ×32位动态RAM模块2M ×16位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module ] 10 页

INFINEON

 		HYM321000S 1M ×32位动态RAM模块2M ×16位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module ] 10 页

INFINEON

 		HYM321000S-50 1M ×32位动态RAM模块2M ×16位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module ] 10 页

INFINEON

 		HYM321000S-60 1M ×32位动态RAM模块2M ×16位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module ] 10 页

INFINEON

 		HYM321005GS-50 1M ×32位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module ] 10 页

INFINEON

 		HYM321005GS-60 1M ×32位动态RAM模块[ 1M x 32-Bit Dynamic RAM Module ] 10 页

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