1240pin Fully Buffered DDR2 SDRAM DIMMs  
					4.3 SMBus Slave Interface  
					The Advanced Memory Buffer supports an SMBus interface to allow system access to configuration regis-  
					ters independent of the FB-DIMM link. The Advanced Memory Buffer will never be a master on the SMBus,  
					only a slave. Serial SMBus data transfer is supported at 100 kHz. SMBus access to the Advanced Memory  
					Buffer may be a requirement to boot and to set link strength, frequency and other parameters needed to  
					insure robust configurations. It is also required for diagnostic support when the link is down. The SMBus  
					address straps located on the DIMM connector are used by the unique ID.  
					4.4 FBD Channel Latency  
					FB-DIMM channel latency is measured from the time a read request is driven on the FB-DIMM channel pins  
					to the time when the first 16 bytes (2nd chunk) of read completion data is sampled by the memory con-  
					troller. When not using the Variable Read Latency capability, the latency for a specific DIMM on a channel  
					is always equal to the latency for any other DIMM on that channel. However, the latency for each DIMM in  
					a specific configuration with some number of DIMMs installed. As more DIMMs are added to the channel,  
					additional latency is required to read from each DIMM on the channel. Because the channel is based on  
					the point to point interconnection of buffer components between DIMMs, memory requests are required to  
					travel through N-1 buffers before reaching the Nth buffer. The result is that a 4 DIMM channel configura-  
					tion will have greater idle read latency compared to a 1DIMM channel configuration.The Variable Read  
					Latency capability can be used to reduce latency for DIMMs closer to the host. The idle latencies listed in  
					this section are representative of what might be achieved in typical AMB designs. Actual implementations  
					with latencies less than the values listed will have higher application performance and vice versa.  
					4.5 Peak Theoretical Throughput  
					An FB-DIMM channel transfers read completion data on the FBD Northbound data connection. 144 bits of data are  
					transferred for every FBD Northbound data frame. This matches the 18-byte data transfer of an ECC DDR DRAM in a  
					single DRAM command clock. A DRAM burst of 8 from a single channel or a DRAM burst of four from two lock stepped  
					channels provides a total of 72 bytes of data(64 bytes plus 8 bytes ECC)  
					The FBD frame rate matches the DRAM command clock because of the fixed 6:1 ratio of the FBD channel clock to the  
					DRAM command clock. Therefore, the Northbound data connection will exhibit the same peak theoretical throughput  
					as a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical throughput as a single  
					DRAM channel.For example, when using DDR2 533 DRAMs, the peak theoretical bandwidth of the Northbound data  
					connection is 4.276 GB/sec.  
					Write data is transferred on the FBD Southbound command and data connection, via Command+Wdata frames. 72  
					bits of data are transferred for every FBD Command+Wdata frame. Two Command+Wdata frames match the 18-byte  
					data transfer of and ECC DDR DRAM in a single DRAM command clock. A DRAM burst of 8 transfers from a single  
					channel, or a burst of 4 from two lock-step channels provides a total of 72 bytes of data(64 bytes plus & bytes ECC)  
					When the FBD frame rate matches the DRAM command clock, the Southbound command and data connection will  
					exhibit one half the peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533  
					DRAMs, the peak theoretical bandwidth of the Southbound command and data connection is 2.133 GB/sec.  
					The total peak theoretical throughput for a single FBD channel is defined as the sum of the peak theoretical through-  
					put of the Northbound data connection and the Southbound command and data connection. When the FBD frame rate  
					matches the DRAM command clock, this is equal to 1.5 times the peak theoretical throughput of a single DRAM chan-  
					nel. For example, when using DDR2 533 DRAMs, the peak theoretical throughput of a DDR2 533 channel would be  
					4.267 GB/sec, while the peak theoretical throughput of and FBD -/+533 channel would be 6.4 GB/sec.  
					Rev. 0.1 / Aug. 2006  
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