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CYW2330

型号：

CYW2330

描述：

双串行输入锁相环与2.5 - GHz和600 MHz的预分频器[ Dual Serial Input PLL with 2.5-GHz and 600-MHz Prescalers ]

品牌：

CYPRESS[ CYPRESS ]

页数：

13 页

PDF大小：

230 K

下载PDF手册
30  
PRELIMINARY  
CYW2330  
Dual Serial Input PLL with 2.5-GHz and 600-MHz Prescalers  
Features  
Applications  
• Operating voltage: 2.7 V to 5.5 V  
• PLL1 operating frequency:  
— 2.5 GHz with prescaler ratios of 32/33 and 64/65  
The Cypress CYW2330 is a dual serial input PLL frequency  
synthesizer which includes a 2.5-GHz RF and a 600-MHz IF  
dual modulus prescaler to combine the RF and IF mixer fre-  
quency sections of wireless communication systems. The syn-  
thesizer is designed for cordless/cellular telephone systems,  
cable TV tuners, WLANs and other wireless communication  
systems. The device operates from 2.7 V and dissipates only  
24 mW.  
• PLL2 operating frequency:  
— 600 MHz with prescaler ratios of 8/9 and 16/17  
• Lock detect feature  
• Available in a 20-pin TSSOP (Thin Shrink Small Outline  
Package)  
• Available in a 24-pin CSP (Chip Scale Package)  
• Available in a 20-pin MLF  
(Mirco Lead Frame Package)  
CYW2330 Dual Hi-Lo PLL Block Diagram  
GND (4)  
GND (7)  
VCC1 (1)  
VCC2 (20)  
VP1 (2)  
FIN1 (5)  
Prescaler  
32/33 or  
64/65  
fp1  
Binary 6-Bit  
Swallow Counter  
Binary 11-Bit  
Programmable Counter  
DOPLL1 (3)  
Phase  
Detector  
Charge  
Pump  
FIN1# (6)  
19-Bit  
Latch  
Pwr-dwn  
PLL1  
OSC_IN (8)  
fr fp  
fr1  
fr2  
15-Bit  
Monitor  
Output  
Selector  
Reference Counter  
FO/LD (10)  
20-Bit Latch  
Latch  
Selector  
LE (13)  
DATA (12)  
20-Bit Latch  
Power  
Control  
15-Bit  
Reference Counter  
22-Bit  
Shift  
Cntrl  
Reg.  
CLOCK (11)  
19-Bit  
Latch  
Pwr-dwn  
PLL2  
Phase  
Detector  
Charge  
Pump  
FIN2 (16)  
Prescaler  
8/9 or  
16/17  
Binary 4-Bit  
Swallow Counter  
Binary 11-Bit  
Programmable Counter  
DOPLL2 (18)  
fp2  
FIN2# (15)  
GND (14)  
GND (9)  
GND (17)  
VP2 (19)  
Pin Configuration  
V
1
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
2
CC  
CC  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1
2
3
4
5
6
7
8
9
NC  
NC  
Vp1  
V 1  
V 2  
P
P
DoPLL2  
GND  
Fin2  
D PLL1  
3
D PLL2  
O
O
DoPLL1  
GND  
1
15  
DoPLL1  
GND  
GND  
4
GND  
2
3
4
5
GND  
Fin1  
14  
13  
12  
11  
Fin2  
Fin2#  
GND  
LE  
F
1
5
F
F
2
IN  
IN  
IN  
(Top View)  
Fin2#  
GND  
LE  
Fin1  
(Top View)  
F
1#  
6
2#  
Fin1#  
GND  
Fin1#  
GND  
IN  
GND  
OSC_IN  
GND  
7
GND  
LE  
DATA  
NC  
OSC_IN  
NC  
8
9
DATA  
CLOCK  
F /LD  
10  
O
CSP  
3901 North First Street  
MLF  
TSSOP  
Cypress Semiconductor Corporation  
•
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-07239 Rev. **  
Revised September 27, 2001  
PRELIMINARY  
CYW2330  
Pin Definitions  
Pin  
No.  
(TSSOP)  
Pin  
No.  
(CSP)  
Pin  
No.  
Pin  
Type  
Pin Name  
(MLF)  
Pin Description  
VCC  
1
1
2
3
24  
19  
20  
1
P
P
O
Power Supply Connection for PLL1 and PLL2: When power  
is removed from both the VCC1 and VCC2 pins, all latched data  
is lost.  
VP1  
2
PLL1 Charge Pump Rail Voltage: This voltage accommo-  
dates VCO circuits with tuning voltages higher than the VCC of  
PLL1.  
DOPLL1  
3
PLL1 ChargePumpOutput: The phasedetector gainis IP/2π.  
Sense polarity can bereversed by settingthe FC bit in software  
(via the Shift Register).  
FIN1  
5
6
5
6
3
4
I
I
Input to PLL1 Prescaler: Maximum frequency 2.5 GHz.  
FIN1#  
Complementary Input to PLL1 Prescaler: A bypass capaci-  
tor should be placed as close as possible to this pin and must  
be connected directly to the ground plane.  
OSC_IN  
FO/LD  
8
8
6
8
I
Oscillator Input: This input has a VCC/2 threshold and CMOS  
logic level sensitivity.  
10  
11  
O
Lock Detect Pin of PLL1 Section: This output is HIGH when  
the loop is locked. It is multiplexed to the output of the program-  
mable counters or reference dividers inthetest program mode.  
(Refer to Table 3 for configuration.)  
CLOCK  
11  
12  
9
I
Data Clock Input: One bit of data is loaded into the Shift Reg-  
ister on the rising edge of this signal.  
DATA  
LE  
12  
13  
14  
15  
10  
11  
I
I
Serial Data Input  
Load Enable: On the rising edge of this signal, the data stored  
in the Shift Register is latched into the reference counter and  
configuration controls, PLL1 or PLL2 depending on the state  
of the control bits.  
FIN2#  
15  
17  
13  
I
Complementary Input to PLL2 Prescaler: A bypass capaci-  
tor should be placed as close as possible to this pin and must  
be connected directly to the ground plane.  
FIN2  
16  
18  
18  
20  
14  
16  
I
Input to PLL2 Prescaler: Maximum frequency 600 MHz.  
DOPLL2  
O
PLL2 ChargePumpOutput: The phasedetector gainis IP/2π.  
Sense polarity can bereversed by settingthe FC bit in software  
(via the Shift Register).  
VP2  
19  
20  
22  
23  
17  
18  
P
P
PLL2 Charge Pump Rail Voltage: This voltage accommo-  
dates VCO circuits with tuning voltages higher than the VCC of  
PLL2.  
VCC  
2
Power Supply Connections for PLL1 and PLL2: When pow-  
er is removed from both the VCC1 and VCC2 pins, all latched  
data is lost.  
GND  
N/C  
4, 7, 9,  
14, 17  
4, 7,  
10,  
16, 19  
2, 5, 7,  
12, 15  
G
Analog and Digital Ground Connections: This pin must be  
grounded.  
N/A  
1, 9,  
13, 21  
N/A  
N/C  
No Connect.  
Document #: 38-07239 Rev. **  
Page 2 of 13  
PRELIMINARY  
CYW2330  
only. Operation of the device at these or any other conditions  
above those specified in the operating sections of this specifi-  
cation is not implied. Maximum conditions for extended peri-  
ods may affect reliability.  
Absolute Maximum Ratings  
Stresses greater than those listed in this table may cause per-  
manent damage to the device. These represent a stress rating  
Parameter  
VCC or VP  
VOUT  
Description  
Power Supply Voltage  
Rating  
–0.5 to +6.5  
–0.5 to VCC+0.5  
±15  
Unit  
V
Output Voltage  
V
IOUT  
Output Current  
mA  
°C  
°C  
TL  
Lead Temperature  
Storage Temperature  
+260  
TSTG  
–55 to +150  
Always turn off power before adding or removing devices from  
system.  
Handling Precautions  
Devices should be transported and stored in antistatic con-  
tainers.  
Protect leads with a conductive sheet when handling or trans-  
porting PC boards with devices.  
These devices are static sensitive. Ensure that equipment and  
personnel contacting the devices are properly grounded.  
If devices are removed from the moisture protective bags for  
more than 36 hours, they should be baked at 85°C in a mois-  
ture free environment for 24 hours prior to assembly in less  
than 24 hours.  
Cover workbenches with grounded conductive mats.  
Recommended Operating Conditions  
Parameter  
Description  
Power Supply Voltage  
Test Condition  
Rating  
Unit  
VCC1  
,
2.7 to 5.5  
V
VCC2  
VP  
TA  
Charge Pump Voltage  
Operating Temperature  
VCC to +5.5  
V
Ambient air at 0 CFM flow  
–40 to +85  
°C  
Document #: 38-07239 Rev. **  
Page 3 of 13  
PRELIMINARY  
CYW2330  
Electrical Characteristics: VCC = VP = 2.7V to 5.5V, TA = –40°C to +85°C, Unless otherwise specified  
Parame-  
ter  
Description  
Test Condition  
Pin  
Min.  
Typ.  
Max.  
Unit  
ICC  
IPD  
Power Supply Current  
PLL1 + PLL2  
VCC1 = VCC2 = 3.0V  
VCC1,  
8.5  
mA  
VCC  
VCC1,  
VCC  
2
µA  
Power-down Current  
Power-down, VCC = 3.0V  
1
25  
2
FIN1  
FIN2  
FOSC  
Fφ  
Operating Frequency  
PLL1  
PLL2  
FIN1  
100  
45  
5
2500  
600  
45  
10  
4
MHz  
MHz  
MHz  
MHz  
dBm  
dBm  
dBm  
VP–P  
µA  
FIN2  
Oscillator Input Frequency  
Phase Detector Frequency  
Input Sensitivity  
OSC_IN  
PFIN1  
VCC = 2.7V  
FIN1  
–15  
–10  
–10  
0.5  
VCC = 5.5V  
4
PFIN2  
VOSC  
IIH, IIL  
VCC = 2.7V to 5.5V  
VCC = 3.0V  
FIN2  
4
Oscillator Input Sensitivity  
OSC_IN  
High/Low Level Input  
Current  
–100  
100  
V
CC = 3.0V  
VIH  
VIL  
IIH  
High Level Input Voltage  
Low Level Input Voltage  
High Level Input Current  
Low Level Input Current  
High level Output Voltage  
Low Level Output Voltage  
DATA,  
CLOCK,  
LE  
VCC * 0.8  
V
V
VCC * 0.2  
µA  
µA  
V
–10  
–10  
0.5  
0.5  
10  
10  
IIL  
VOH  
VOL  
VCC = 3.0V, IOH = –1 mA  
VCC = 3.0V, IOL = 1 mA  
FO/LD  
VCC * 0.8  
VCC * 0.2  
V
IDOH(SO) IDO High, Source Current  
IDOL(SO) IDO Low, Source Current  
VCC = VP = 3.0V,  
DO = VP/2  
DOPLL1  
DOPLL2  
–3.8  
–1  
3.8  
1
mA  
mA  
mA  
mA  
%
IDOH(SI)  
IDOL(SI)  
∆IDO  
IDO High, Sink Current  
IDO Low, Sink Current  
IDO Charge Pump Sink and VCC = VP = 3.0V,  
3
15  
Source Mismatch  
[IIDO(SI)I – IIDO(SO)I]/  
[1/2*{IIDO(SI)]I+IIDO(SO)I}]*100%  
–40°C<T<85°C VDO = VP/2[1]  
5
%
IDO vs T Charge Pump Current  
Variation vs. Temperature  
nA  
IOFF  
Charge Pump High-Imped- VCC = VP = 3.0V,  
ance Leakage Current  
±2.5  
Note:  
1. IDOvs T; Charge pump current variation vs. temperature.  
[IIDO(SI)@TI - IIDO(SI)@25° CI]/IIDO(SI)@25°CI * 100% and  
[IIDO(SO)@TI - IIDO(SO)@25°CI]/IIDO(SO)@25°CI *100%.  
Document #: 38-07239 Rev. **  
Page 4 of 13  
PRELIMINARY  
CYW2330  
Timing Waveforms  
Key:  
FC Bit HIGH  
FC Bit LOW  
Increasing  
Voltage  
(Refer to Table 2 for meaning of FC bit.)  
Increasing Frequency  
VCO Characteristics  
Phase Comparator Sense  
Phase Detector Output Waveform  
F
F
R
P
tw  
tw  
LD  
DO Charge Pump Output Current Waveform  
F
F
R
P
tw  
tw  
D
o
ID  
O
Hi-Impedance State  
Document #: 38-07239 Rev. **  
Page 5 of 13  
PRELIMINARY  
CYW2330  
Timing Waveforms (continued)  
Serial Data Input Timing Waveform[2, 3, 4, 5]  
//  
//  
//  
//  
PD = MSB  
PRE  
B1  
A7  
CNT2  
CNT1 = LSB  
DATA  
//  
//  
CLOCK  
t5  
t4  
t3  
t2  
t1  
//  
//  
//  
//  
LE  
t6  
Serial Data Input  
Data is input serially using the DATA, CLOCK, and LE pins. Two control bits direct data as described in Table 1.  
Table 1. Control Configuration  
CNT1  
CNT2  
Function  
0
0
Program Reference 2: R = 3 to 32767, set PLL2 (low frequency) phase detector  
polarity, set current in PLL2, set PLL2 to Hi-Impedance state, set monitor selector to PLL2.  
0
1
1
1
0
1
Program Reference 1: R = 3 to 32767, set PLL1 (high frequency) phase detector  
polarity, set current in PLL1, set PLL1 to Hi-Impedance state, set monitor selector to PLL1  
Program Counter for PLL2: A = 0 to 15, B = 3 to 2047, set PLL2 prescaler ratio, set PLL2  
to power-down.  
Program Counter for PLL1: A = 0 to 63, B = 3 to 2047, set PLL1 prescaler ratio, set PLL1  
to power-down.  
Notes:  
2. t1–t6 = t > 50 ns.  
3. CLOCK may remain HIGH after latching in data.  
4. DATA is shifted in with the MSB first.  
5. For DATA definitions, refer to Table 2.  
Document #: 38-07239 Rev. **  
Page 6 of 13  
PRELIMINARY  
CYW2330  
Table 2. Shift Register Configuration[6]  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22  
Reference Counter and Configuration Bits  
CNT1 CNT2  
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 FC IDO TS LD FO  
Programmable Counter bits  
CNT1 CNT2  
A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 PRE PD  
Bit(s) Name  
CNT1, CNT2  
R1–R15  
FC  
Function  
Control Bits: Directs programming data to PLL1 (high frequency) or PLL2 (low frequency).  
Reference Counter Setting Bits: 15 bits, R = 3 to 32767.[7]  
Phase Sense of the Phase Detector: Set to match the VCO polarity, H = + (Positive VCO transfer function).  
Charge Pump Setting Bit: IDO HIGH = 3.8 mA, IDO LOW = 1 mA at VP = 3V.  
Hi-Impedance State Bit: Makes DO Hi-Impedance for PLL1 and PLL2 when HIGH.  
IDO  
TS  
LD  
Lock Detect: Directs the lock detect signal source pin 10. Pin 10 is HIGH with narrow low excursions when  
locked. When not locked, this pin is LOW.  
FO  
Frequency Out: This bit can be set to read out reference or programmable divider at the LD pin for test  
purposes.  
PRE  
PD  
Prescaler Divide Bit: For PLL1: LOW = 32/33 and HIGH = 64/65. For PLL2: LOW = 8/9 and HIGH = 16/17.  
Power-down: LOW = power-up and HIGH = power-down. FIN is at a high-impedance state, respective B  
counter is disabled, forces DO outputs to Hi-Impedance and phase comparators are disabled. The reference  
counter is disabled and the OSC input is high-impedance after both PLLs are powered down. Data can be  
input and latched in the power-down state.  
A1–A7  
Swallow Counter Divide Ratio: A = 0 to 63 for PLL1 and 0 to 15 for PLL2.  
Programmable Counter Divide Ratio: B = 3 to 2047.[7]  
B1–B11  
Table 3. FO/LD Pin Truth Table  
FO (Bit 22)  
LD (Bit 21)  
PLL1  
PLL2  
PLL1  
PLL2  
FO/LD Pin Output State  
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
0
1
0
1
1
1
0
0
1
1
X
X
X
X
0
1
1
0
1
0
1
0
0
1
1
1
0
1
Disable  
PLL2 Lock Detect  
PLL1 Lock Detect  
PLL1/PLL2 Lock Detect  
PLL2 Reference Divider Output  
PLL1 Reference Divider Output  
PLL2 Programmable Divider Output  
PLL1 Programmable Divider Output  
PLL2 Counter Reset  
PLL1 Counter Reset  
PLL1/PLL2 Counter Reset  
Notes:  
6. The MSB is loaded in first.  
7. Low count ratios may violate frequency limits of the phase detector.  
Document #: 38-07239 Rev. **  
Page 7 of 13  
PRELIMINARY  
CYW2330  
Table 4. 6-Bit Swallow Counter (A) Truth Table[8]  
Divide Ratio A  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
PLL1 (High Frequency)  
0
X
X
:::  
X
X
0
0
0
0
0
0
0
0
0
0
0
1
1
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
62  
63  
1
1
1
1
1
1
PLL2 (Low Frequency)  
0
X
X
:::  
X
X
X
X
:::  
X
X
X
X
:::  
X
X
0
0
0
0
0
0
0
1
1
:::  
14  
15  
:::  
1
:::  
1
:::  
1
:::  
0
1
1
1
1
Table 5. 11-Bit Programmable Counter (B) Truth Table[9]  
Divide Ratio B  
B11  
0
B10  
0
B9  
0
B8  
0
B7  
0
B6  
0
B5  
0
B4  
0
B3  
B2  
1
B1  
1
3
4
0
1
0
0
0
0
0
0
0
0
0
0
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
2046  
2047  
1
1
1
1
1
1
1
1
1
1
1
Table 6. 15-Bit Programmable Reference Counter (for PLL1 and PLL2) Truth Table[10]  
Divide Ratio R  
R15 R14 R13 R12 R11 R10  
R9  
0
R8  
0
R7  
0
R6  
0
R5  
R4  
0
R3  
0
R2  
1
R1  
3
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
32766  
32767  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Ordering Information[11]  
Package  
Name  
Ordering Code  
Package Type  
Tape and Reel Option  
ZI  
BCI  
LFI  
20-pin Thin Shrink Small Outline Package (0.173” wide)  
24-pin Chip Scale Package (3.5 mm X 4.5 mm)  
20-pin Micro Lead Frame (4 mm x 4 mm)  
CYW2330  
TR  
Notes:  
8. B is greater than or equal to A.  
9. Divide ratio less than 3 is prohibited. (See equation below.)  
10. Divide ratio less than 3 is prohibited. The divide ratio can be calculated using the following equation:  
fvco = {(P * B) + A} * fosc / R where (A < B)  
fvco: Output frequency of the external VCO.  
fosc: The crystal reference oscillator frequency.  
A: Preset divide ratio of the 6-bit swallow counter (0 to 63) and the 4-bit swallow counter (0 to 15).  
B: Preset ratio of the 11-bit programmable counter (3 to 2047).  
P: Preset divide ratio of the dual modulus prescaler.  
R: Preset ratio of the 15-bit programmable reference counter (3 to 32767).  
The divide ratio N = (P * B) + A.  
11. Operating temperature range: –40°C to +85°C.  
Document #: 38-07239 Rev. **  
Page 8 of 13  
PRELIMINARY  
CYW2330  
Typical Performance Characteristics  
Charge Pump Current vs Do Voltage  
Icp=Low  
Charge Pump Current vs Do Voltage  
Icp=High  
1.5  
1
6
4
Vp=5V  
Vp=3V  
Vp=5V  
Vp=3V  
0.5  
0
2
0
-0.5  
-1  
Vp=3V  
Vp = 5V  
Vp=3V  
-2  
-4  
-6  
Vp = 5V  
-1.5  
2
3
4
5
0
1
Do Voltage (V)  
3
4
5
1
2
Do Voltage (V)  
0
Figure 3.  
Do Output Current Low Mode  
Figure 1.  
Do Output Current High Mode  
ATTEN  
RL  
10dB  
-2.5dBm  
VAVG  
10dB/  
100  
MKR  
-85.50dB  
100.0kHz  
85 dBc  
1
START  
RBW  
835.8505MHz  
3.0kHz  
STOP  
836.1505MHz  
SWP 84.0ms  
2
VBW  
3.0kHz  
4
3
Figure 3. PLL Reference Spurs  
PLL Reference Spurious Level is –85.5 dBc  
Marker Reference  
Number  
Input  
Frequency  
Real Imaginary  
Marker 1  
623  
21  
-823  
-120  
-55  
100 MHz  
Marker 2  
Marker 3  
Marker 4  
1 GHz  
1.8 GHz  
2.2 GHz  
14  
13  
-39  
Figure 4.  
Input Impedance FIN1,FIN2  
VCC = 2.7 to 5.5V, FIN = 75 MHz to 2.6 GHz  
Document #: 38-07239 Rev. **  
Page 9 of 13  
PRELIMINARY  
CYW2330  
Package Diagram  
20-Pin Thin Shrink Small Outline Package (TSSOP, 0.173” wide)  
\
Document #: 38-07239 Rev. **  
Page 10 of 13  
PRELIMINARY  
CYW2330  
Package Diagram  
24-Pin Chip Scale Package (CSP 3.5 mm X 4.5 mm)  
Document #: 38-07239 Rev. **  
Page 11 of 13  
PRELIMINARY  
CYW2330  
Package Diagram  
20-Pin Micro Lead Frame Package (MLF 4 mm X 4 mm)  
Document #: 38-07239 Rev. **  
Page 12 of 13  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
PRELIMINARY  
CYW2330  
Document Title: CYW2330 Dual Serial Input PLL with 2.5 GHz and 600 MHz Prescalers  
Document Number: 38-07239  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
110504  
01/07/02  
SZV  
Change from Spec number: 38-00966 to 38-07239  
Document #: 38-07239 Rev. **  
Page 13 of 13  
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