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9VRS4338D

型号：

9VRS4338D

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

23 页

PDF大小：

332 K

下载PDF手册
DATASHEET  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
9VRS4338D  
General Description  
Features/Benefits  
The 9VRS4338D is a main clock for Intel Netbooks,  
conforming to the CK-NET specification. It is driven with a  
14.31818MHz crystal and generates a variety of clocks,  
including an LCD clock. An SMBus interface allows full  
control of the device.  
• 25M output can run in power down; Supports  
Wake_On_LAN  
• Selectable spread % on CPU, SRC, PCI; Supports  
margining  
• External 14.318MHz crystal; Supports tight ppm  
• CLKREQ# pins; Support SRC power management  
Recommended Application  
• Low power differential clock outputs; reduced power and  
CK-NET  
board space  
Output Features  
• Integrated 33 ohm series resistors on all differential  
outputs; reduced board space  
• 2 - 0.8V push-pull differential CPU pairs  
• 3 - 0.8V push-pull differential SRC pairs  
• 1 - 0.8V push-pull differential SATA/SRC pair  
• 1 - 0.8V push-pull differential DOT96/SRC pair  
• 1 - 0.8V push-pull differential LCD100 pair  
• 1 - 0.8V push-pull differential CPU_ITP/SRC pair  
• 3 - PCI (33MHz), 1 free-running  
Key Specifications  
• CPU cycle-to-cycle jitter <85ps  
• SRC/SATA cycle-to-cycle jitter <85ps  
• SRC(1:4) are PCIe Gen2 compliant  
• SRC5 is PCIe Gen1 compliant  
•
•
100ppm frequency accuracy on all clocks except 25M  
• 1 - 25MHz _PCI (33MHz)  
• 1 - USB_48MHz  
30ppm frequency accuracy on 25M  
• 1 - REF, 14.318MHz  
Pin Configuration  
48 47 46 45 44 43 42 41 40 39 38 37  
X2  
X1  
VDDREF  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1
2
3
4
5
6
SRC2_LRS  
SRC2#_LRS  
GNDSRC  
REF0_2x/FSLC  
SDATA_3.3  
SCLK_3.3  
SRC3_LRS  
SRC3#_LRS  
PCI_STOP#_3.3  
VDDSRC_LVIO  
SRC4_LRS  
SRC4#_LRS  
SATA_LRS  
SATA#_LRS  
GNDSATA  
9VRS4338D  
VDDPCI_3.3 7  
vITP_EN/PCI_F1_2x 8  
FSLB/PCI2_2x 9  
CLKREQA#/PCI3_2x 10  
GNDPCI 11  
GND25 12  
13 14 15 16 17 18 19 20 21 22 23 24  
48-pin MLF, 6x6 mm, 0.4mm pitch  
prefix indicates internal 120KOhm pull down resistor  
prefix indicates internal 120KOhm pull up resistor  
v
^
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
1
9VRS4338D  
REV A 022616  
9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Pin Descriptions  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
1
2
3
X2  
X1  
VDDREF  
OUT Crystal output, Nominally 14.318MHz  
IN Crystal input, Nominally 14.318MHz.  
PWR Ref, XTAL power supply, nominal 3.3V  
2x strength 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency  
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.  
4
REF0_2x/FSLC  
I/O  
SDATA_3.3  
SCLK_3.3  
VDDPCI_3.3  
5
6
7
I/O Data pin for SMBus circuitry, 3.3V tolerant.  
IN Clock pin of SMBus circuitry, 3.3V tolerant.  
PWR Power supply for PCI clocks, nominal 3.3V  
ITP Enable Latched Input/Free Running PCI clock output.  
ITP_Enable Selects the functionality of the CPU_ITP/SRC output as follows:  
1 = CPU_ITP output  
0 = SRC output  
8
9
vITP_EN/PCI_F1_2x  
FSLB/PCI2_2x  
I/O  
3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs,  
I/O see input electrical characteristics for Vil_FS and Vih_FS values. / 3.3V PCI  
clock output.  
Active low realtime input pin to enable SRC Outputs / PCI clock output. (pin  
I/O function is programmable through SMBus). See CLKREQ# Control Table and  
SRC Power Management Table for details.  
PWR Ground pin for the PCI outputs  
10 CLKREQA#/PCI3_2x  
11 GNDPCI  
GND25  
12  
PWR Ground pin for the 25MHz outputs  
SEL_PCI 3.3V latched input to select pin functionality for 25M_PCICLK3  
output/25M or PCI clock output. This pin has an internal 120Kohm pulldown  
13 vSEL_PCI/25M_PCI4_2x  
14 VDD25  
I/O resistor. Latch functionality is as follows:  
0 = 25MHz output  
1 = 33.3MHz PCICLK  
PWR Power pin for the 25MHz output.3.3V  
VDD48  
15  
PWR Power pin for the 48MHz output.3.3V  
3.3V 48MHz USB clock output. This pin has an internal 120Kohm pull down  
resistor.  
PWR Ground pin for the 48MHz outputs  
16 vUSB_48Mhz_2x  
17 GND48  
OUT  
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are  
controlled.  
0 = controlled outputs are enabled  
18 CLKREQB#  
IN  
1 = controlled outputs are Low/Low  
True clock of push-pull DOT96 or SRC clock with integrated series resistor. No  
19 DOT96_LRS/SRC5_LRS  
20 DOT96#_LRS/SRC5#_LRS  
OUT 50 ohm pull down needed. Default is DOT96. After powerup, this pin function  
may be changed to SRC via SMBus.  
Complementary clock of push-pull DOT96 or SRC clock with integrated series  
OUT resistor. No 50 ohm pull down needed. Default is DOT96. After powerup, this pin  
function may be changed to SRC via SMBus.  
21 VDD_CORE_1.5  
22 LCD100_LRS  
PWR Power for PLL core components requiring 1.5V  
True clock of differential push-pull LCD100 output with integrated 33ohm series  
OUT  
resistor. No 50ohm resistor to GND needed.  
Complementary clock of differential push-pull LCD100 output with integrated  
33ohm series resistor. No 50ohm resistor to GND needed.  
PWR Ground pin for LCD clock output  
23 LCD100#_LRS  
24 GNDLCD  
OUT  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
2
9VRS4338D  
REV A 022616  
9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Pin Descriptions (cont.)  
GNDSATA  
25  
PWR Ground pin for the SATA outputs  
Complementary clock of low power differential push-pull SATA clock pair with  
integrated 33ohm series resistor. No 50 ohm resistor to GND needed.  
26 SATA#_LRS  
OUT  
True clock of low power differential push-pull SATA clock pair with integrated  
33ohm series resistor. No 50 ohm resistor to GND needed.  
Complementary clock of differential 0.8V push-pull SRC output with integrated  
33ohm series resistor. No 50ohm resistor to GND needed.  
27 SATA_LRS  
28 SRC4#_LRS  
OUT  
OUT  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
29 SRC4_LRS  
OUT  
30 VDDSRC_LVIO  
PWR VDD for SRC I/O. Nominally 1.05V to 1.5V from external power supply  
Stops all stoppable PCI and SRC clocks at logic 0 level, when low. Free running  
PCI and SRC clocks are not effected by this input. This input is 3.3V tolerant.  
31 PCI_STOP#_3.3  
32 SRC3#_LRS  
IN  
Complementary clock of differential 0.8V push-pull SRC output with integrated  
33ohm series resistor. No 50ohm resistor to GND needed.  
OUT  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
PWR Ground pin for the SRC outputs  
33 SRC3_LRS  
34 GNDSRC  
OUT  
Complementary clock of differential 0.8V push-pull SRC output with integrated  
33ohm series resistor. No 50ohm resistor to GND needed.  
35 SRC2#_LRS  
OUT  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
36 SRC2_LRS  
OUT  
37 CPU_STOP#_3.3  
IN Stops stoppable CPU clocks when enabled. This is a 3.3V tolerant input.  
Complementary clock of low power differential CPU_ITP/SRC pair with  
integrated 33ohm series resistor. No 50ohm resistor to GND needed. The pin  
OUT function is determined by the latched value on ITP_EN:  
0 = SRC0#  
38 CPU_ITP#/SRC1#_LRS  
39 CPU_ITP/SRC1_LRS  
1 = CPU ITP#  
True clock of low power differential CPU_ITP/SRC pair with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed. The pin function is  
OUT determined by the latched value on ITP_EN:  
0 = SRC0  
1 = CPU_ITP  
VDD_CORE_1.5  
41 VDDCPU_LVIO  
40  
PWR Power for PLL core components requiring 1.5V  
PWR VDD for CPU I/O. Nominally 1.05V to 1.5V from external power supply.  
Complementary clock of differential pair 0.8V push-pull CPU outputs with  
integrated 33ohm series resistor. No 50 ohm resistor to GND needed.  
42 CPU1#_LRS  
OUT  
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm  
series resistor. No 50 ohm resistor to GND needed.  
PWR Ground pin for the CPU outputs  
43 CPU1_LRS  
44 GNDCPU  
OUT  
Complementary clock of differential pair 0.8V push-pull CPU outputs with  
integrated 33ohm series resistor. No 50 ohm resistor to GND needed.  
45 CPU0#_LRS  
OUT  
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm  
series resistor. No 50 ohm resistor to GND needed.  
46 CPU0_LRS  
OUT  
This 3.3V LVTTL input notifies device to sample latched inputs and start up on  
IN first high assertion, or exit Power Down Mode on subsequent assertions. Low  
enters Power Down Mode.  
47 CLKPWRGD/PD#_3.3  
GNDREF  
48  
PWR Ground pin for the REF outputs.  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
3
9VRS4338D  
REV A 022616  
9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Block Diagram  
14.318M  
LCD100  
SS PLL  
SEL_PCI  
0
1
25M_PCI4  
SATA  
NonSS  
PLL  
100M  
1
0
ITP_EN  
SRC(4:2)  
0
1
CPUIPT/SRC1  
14.318M  
XTAL  
SS PLL  
CPU(1:0)  
PCI(3:1)  
1
0
DOT96/SRC5  
USB48MHz  
DOT96  
NonSS  
PLL  
DOT96/SRC SEL  
Series Resistors for Single Ended Outputs  
Number of Loads Actually Driven.  
Number of  
Loads  
to Drive  
Match Point for N & P  
Voltage / Current (mA)  
1 Load  
Rs =  
2 Loads  
Rs=  
3 Loads  
Rs =  
D.C.Drive Strength  
Ω
Ω
Ω
1
2
0.56 / 33 (17 )  
33 [39 ]  
NA  
NA  
NA  
Ω
Ω Ω Ω Ω  
39 [43 ] 22 [27 ]  
0.92 / 66 (14 )  
Notes:  
1. Preferred drive strengths using CK505 clock sources. Transmission lines to load do not  
share series resistors.  
2. Desktop/Mobile Platforms with Zo = 50/55 ohms use the first resistor value.  
3. Systems with Zo = 60 ohms use the resistor values in brackets [ ].  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
4
9VRS4338D  
REV A 022616  
9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
5 inches  
Zo  
Rs  
CL=5pF  
Test Load  
Single-ended  
Output  
5 inches  
Zo  
Rs  
Rs  
CL=5pF  
5 inches  
Zo  
CL=5pF  
Single-ended  
``  
Output  
The singled-ended outputs of the 9VRS4338 can drive 2 loads. If the output is  
driving one load, the resistor value is adjusted according to the “Series  
Resistors for Single-Ended Outputs Table. When driving two loads, both load  
traces must be equal in length.  
9VRS4338 Differential Test Load  
5 inches  
Zo = 100ohms  
2pF  
2pF  
Low-Power  
Push-Pull Buffer  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
5
9VRS4338D  
REV A 022616  
9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Driving LVDS inputs with the 9VRS4338  
Value  
Receiver has  
termination  
10K ohm  
5.6K ohm  
0.1 uF  
Receiver does not  
Component  
R7a, R7b  
R8a, R8b  
Note  
have termination  
140 ohm  
75 ohm  
Cc  
0.1 uF  
Vcm  
1.2 volts  
1.2 volts  
3.3 Volts  
R7b  
R7a  
Cc  
L4  
L4’  
Cc  
9VRS4338  
R8a  
R8b  
LVDS CLK  
Input  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
6
9VRS4338D  
REV A 022616  
9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Table 1: CPU/SRC/PCI PLL Spread/Frequency Selection Table REV D  
CPU/SRC/PCI  
FSLC  
FSLB  
Center  
Spread  
(B1b6)  
SS1  
(B1b5)  
SS0  
(B1b4)  
CPU  
MHz  
SRC  
MHz  
PCI  
MHz  
SPREAD  
(B0b7)  
(B0b6)  
-0.50%  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
133.33  
167.67  
100.00  
200.00  
133.33  
167.67  
100.00  
200.00  
133.33  
167.67  
100.00  
200.00  
133.33  
167.67  
100.00  
200.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
-0.50%  
-0.50%  
-0.50%  
-0.40%  
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
-0.40%  
-0.40%  
-0.40%  
-0.30%  
-0.30%  
-0.30%  
-0.30%  
OFF  
OFF  
OFF  
OFF  
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
+/-0.25%  
+/-0.25%  
+/-0.25%  
+/-0.25%  
133.33  
167.67  
100.00  
200.00  
100.00  
100.00  
100.00  
100.00  
33.33  
33.33  
33.33  
33.33  
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
+/-0.20%  
+/-0.20%  
+/-0.20%  
+/-0.20%  
133.33  
167.67  
100.00  
200.00  
100.00  
100.00  
100.00  
100.00  
33.33  
33.33  
33.33  
33.33  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
+/-0.15%  
+/-0.15%  
+/-0.15%  
+/-0.15%  
OFF  
OFF  
OFF  
OFF  
133.33  
167.67  
100.00  
200.00  
133.33  
167.67  
100.00  
200.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Note: Changing default spread amounts or type will impact SRC clocks, too. The default -  
0.5% downspread is recommended for SRC.  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
7
9VRS4338D  
REV A 022616  
9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Table 2: LCD Spread Selection Table Rev B/C/D  
LCD  
FS2  
FS1  
FS0  
Center SPREAD LCD100  
(B1b3) (B1b2) (B1b1) Spread  
(B1b0)  
%
MHz  
OFF  
OFF  
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
Reserved  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
Reserved  
Reserved  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
Reserved  
-0.50%  
-1.0%  
-1.5%  
-2.0%  
-2.50%  
OFF  
OFF  
OFF  
+/-0.25%  
+/-0.5%  
+/-0.75%  
+/-1.0%  
+/-1.25%  
OFF  
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
8
9VRS4338D  
REV A 022616  
9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
CPU Power Management Table  
SMBus  
CPU (0, 1, ITP)  
CLKPWRGD/PD#_3.3  
CPU_STOP#  
Register OE  
Enable  
Enable  
X
True O/P  
Running  
High  
Comp. O/P  
Running  
Low  
1
1
0
X
1
0
X
X
Low/20K  
Low/20K  
Low  
Low  
Disable  
DOT96 and SATA Power Management Table  
SMBus  
Register OE  
Enable  
Enable  
Disable  
SATA  
DOT96  
CLKPWRGD/PD#_3.3  
True O/P  
Running  
Low/20K  
Low/20K  
Comp. O/P  
Running  
Low  
True O/P  
Running  
Low/20K  
Low/20K  
Comp. O/P  
Running  
Low  
1
0
X
Low  
Low  
SRC Power Management Table  
SRC not controlled by  
CLKREQx#  
SMBus  
CLKPWRGD/PD#_3.3  
Register OE  
SRC controlled by CLKREQx#  
CLKREQx#  
True O/P  
Running  
Low/20K  
Low/20K  
Low/20K  
Comp. O/P  
Running  
Low  
True O/P  
Running  
Running  
Low/20K  
Low/20K  
Comp. O/P  
Running  
Running  
Low  
1
1
0
X
Enable  
Enable  
Enable  
Disable  
0
1
X
X
Low  
Low  
Low  
SIngle-ended Management Table  
PCI_F1, PCI2,  
CLKREQA#/PCI3 = PCI3  
25M_PCI4 = 25MHz  
SMBus  
Register OE  
25M_PCI4 = PCI4  
CLKPWRGD/PD#_3.3  
PCI_STOP#  
REF  
USB_48  
WLAN  
WLAN  
Free-run  
Stoppable  
Free-run  
Stoppable  
Enabled Disabled  
1
1
0
X
Enable  
Enable  
Enable  
Disable  
Running  
Running  
Hi-Z  
Running  
Low  
Hi-Z  
Running  
Running  
Low  
Running  
Low  
Low  
Running  
Running  
Running  
Hi-Z  
Running  
Running  
Hi-Z  
Running  
Running  
Hi-Z  
Running  
Running  
Hi-Z  
1
0
X
X
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
CLKREQ# Control Table  
SRC  
CLKREQ#  
controlled  
A
B
SRC1, 2  
SRC3, 4  
NOTE: SMBus selects configuration  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
9
9VRS4338D  
REV A 022616  
9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
General SMBus Serial Interface Information for 9VRS4338D  
How to Write  
How to Read  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit  
Controller (host) sends the write address  
IDT clock will acknowledge  
Controller (host) sends the beginning byte location = N  
IDT clock will acknowledge  
Controller (host) sends the byte count = X  
IDT clock will acknowledge  
Controller (host) starts sending Byte N through Byte  
N+X-1  
IDT clock will acknowledge each byte one at a time  
Controller (host) sends a Stop bit  
Controller (host) will send a start bit  
Controller (host) sends the write address  
IDT clock will acknowledge  
Controller (host) sends the beginning byte location = N  
IDT clock will acknowledge  
Controller (host) will send a separate start bit  
Controller (host) sends the read address  
IDT clock will acknowledge  
IDT clock will send the data byte count = X  
IDT clock sends Byte N+X-1  
•
•
IDT clock sends Byte 0 through Byte X (if X was  
written to Byte 8)  
(H)  
•
•
•
Controller (host) will need to acknowledge each byte  
Controller (host) will send a not acknowledge bit  
Controller (host) will send a stop bit  
Index Block Write Operation  
Index Block Read Operation  
Controller (Host)  
starT bit  
Slave Address  
IDT (Slave/Receiver)  
Controller (Host)  
starT bit  
IDT (Slave/Receiver)  
T
T
Slave Address  
WR  
WRite  
WR  
WRite  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
Beginning Byte = N  
RT  
Repeat starT  
Slave Address  
ReaD  
RD  
ACK  
O
O
O
O
O
O
Data Byte Count=X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
O
O
O
P
stoP bit  
O
O
O
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
Read Address  
Write Address  
D3  
D2  
(H)  
(H)  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
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VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
SMBus Table: Frequency Select, PD Config and SATA Source Select Register  
Byte 0  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
FSLC  
FSLB  
Control Function  
Freq Select Bit 1  
Freq Select Bit 0  
Type  
R
R
0
1
Default  
Latch  
Latch  
See Table 1: CPU PLL Frequency  
Selection Table  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
1
Reserved  
SATA_SEL  
PD Config  
Selects SATA=SRC or Non-SS  
Forces "cold" start during PD  
RW  
RW  
Follows SRC  
Reset and Relatch  
SATA PLL (NonSS)  
Normal PD# mode  
SMBus Table: CPU, LCD SS and DOT96/SRC5 Control Register  
Byte 1  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
DOT96/SRC5 SEL  
CPU/SRC/PCI Center SS En  
CPU/SRC/PCI SS1  
CPU/SRC/PCI SS0  
LCD SS2  
Control Function  
Selects DOT96 or SRC5  
Enables Center Spread for  
CPU/SRC/PCI SS Mag. MSB  
CPU/SRC/PCI SS Mag. LSB  
LCD SS Magnitude MSB  
LCD SS Magnitude  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DOT96  
Down Spread  
See Table 1 for Details. Default is -0.5%  
down spread when spread is enabled  
SRC5  
Center Spread  
0
0
0
0
1
1
0
0
LCD SS1  
LCD SS0  
LCD Center SS En  
See Table 2 for Details.  
LCD SS Magnitude LSB  
Enables Center Spread for LCD RW  
Down Spread  
Center Spread  
SMBus Table: Output Enable Control Register  
Byte 2  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
REF0 OE  
USB_48MHz OE  
Control Function  
Output Enable  
Output Enable  
Type  
RW  
RW  
0
1
Default  
Disable  
Disable  
Enable  
Enable  
1
1
1
1
1
1
1
1
Reserved  
25M_PCI4 OE  
PCI3 OE  
PCI2 OE  
PCI_F1 OE  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
RW  
RW  
RW  
RW  
Disable  
Disable  
Disable  
Disable  
Enable  
Enable  
Enable  
Enable  
Reserved  
SMBus Table: Output Enable Control Register  
Byte 3  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
1
1
1
1
1
1
1
1
Reserved  
Reserved  
Reserved  
Reserved  
LCD CLK OE  
SRC4 OE  
SATA OE  
Output Enable  
Output Enable  
Output Enable  
RW  
RW  
RW  
Disable  
Disable  
Disable  
Enable  
Enable  
Enable  
SMBus Table: Output Enable and SS Enable Control Register  
Byte 4  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
SRC3 OE  
SRC2 OE  
Control Function  
0
1
Default  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Disable  
Disable  
Disable  
Disable  
Disable  
Disable  
SS OFF  
Enable  
Enable  
Enable  
Enable  
Enable  
1
1
1
1
1
1
1
CPU_ITP/SRC1 OE  
DOT96/SRC5 OE  
CPU1 OE  
CPU0 OE  
CPU/SRC PLL SS EN  
Enable  
SS ON @ -0.5%  
Reserved  
1
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
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VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
SMBus Table: CLKREQ_A# and CLKREQB# Mapping  
Byte 5  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
CLKREQ_A# EN  
CLKREQ_A# MAP  
Control Function  
Pin 10 Configuration  
MAP CLKREQ_A# to SRC  
Reserved  
MAP CLKREQ_B# to SRC  
Reserved  
0
1
Default  
RW  
RW  
Pin 10 = PCI3  
SRC1 Controlled  
Pin 10 = CLKREQ  
SRC2 Controlled  
0
0
0
0
0
0
0
0
CLKREQ_B# MAP  
RW  
SRC3 Controlled  
SRC4 Controlled  
Reserved  
Reserved  
Reserved  
SMBus Table: SRC STOP Control Register  
Byte 6  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
SRC STOP EN  
SRC stop with PCI_STOP  
Free-running  
SRC Stoppable  
SMBus Table: Revision and Vendor ID Register  
Byte 7  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
Control Function  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
0
0
1
0
0
0
0
1
Revision ID  
D rev = 0010  
VENDOR ID  
0001 = ICS/IDT  
SMBus Table: Reserved  
Byte 8  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Type  
0
1
Default  
Reserved  
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
SMBus Table: Byte Count Register  
Byte 9  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Type  
0
1
Default  
Reserved  
Reserved  
Reserved  
0
0
0
0
1
0
1
0
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
Writing to this register will configure how  
many bytes will be read back, default is 0A  
= 10 bytes.  
Byte Count Programming  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
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VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 9VRS4338D. These ratings, which are  
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any  
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute  
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over  
the recommended operating temperature range.  
PARAMETER  
Maximum Supply Voltage  
SYMBOL  
VDD  
CONDITIONS  
Supply Voltage  
MIN  
TYP  
MAX  
3.9  
UNITS Notes  
V
1,4  
Maximum Supply Voltage  
VDD_CORE_1.5  
Supply Voltage  
1.9  
V
1,4  
Maximum Supply Voltage  
Maximum Input Voltage  
Minimum Input Voltage  
VDD_LVIO  
VIH  
Supply Voltage  
3.3V Inputs, including SMBus  
Any Input  
1.9  
3.9  
V
V
V
°C  
°C  
V
1,4  
1,2,4  
1,4  
VIL  
GND - 0.5  
-65  
Storage Temperature  
Case Temperature  
Input ESD protection  
Ts  
Tcase  
ESD prot  
-
-
150  
115  
4
1
3,4  
Human Body Model  
2000  
AC Electrical Characteristics–CPU, SRC, SATA, DOT96MHz  
PARAMETER  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Slew Rate Variation  
SYMBOL  
tSLR  
CONDITIONS  
MIN  
2.5  
2.5  
TYP  
3.2  
MAX  
4
4
20  
1150  
UNITS NOTES  
Differential Measurement  
Differential Measurement  
Single-ended Measurement  
Includes overshoot  
V/ns  
V/ns  
%
1,2  
1,2  
1
tFLR  
tSLVAR  
VHIGH  
VLOW  
VSWING  
VXABS  
VXABSVAR  
DCYC  
3.1  
12.4  
869  
Maximum Output Voltage  
Minimum Output Voltage  
Differential Voltage Swing  
Crossing Point Voltage  
Crossing Point Variation  
Duty Cycle  
mV  
mV  
mV  
mV  
mV  
%
1
1
1
Includes undershoot  
-300  
300  
300  
Differential Measurement  
Single-ended Measurement  
Single-ended Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
364  
32  
550  
140  
55  
85  
85  
1,3,4  
1,3,5  
1
45  
49.8  
46.1  
45.9  
52.1  
110.7  
32  
CPU Jitter - Cycle to Cycle  
SRC Jitter - Cycle to Cycle  
SATA Jitter - Cycle to Cycle  
DOT Jitter - Cycle to Cycle  
CPU[1:0] Skew  
CPUJC2C  
SRCJC2C  
SATAJC2C  
DOTJC2C  
CPU10SKEW  
CPU20SKEW  
SRC24SKEW  
SRC15SKEW  
ps  
1
ps  
1
85  
ps  
1
250  
100  
150  
250  
500  
ps  
1
ps  
ps  
ps  
1,6  
1,6  
1
CPU[2_ITP:0] Skew  
SRC(2:4) Skew  
SRC(1:5) Skew  
53  
53  
142  
ps  
1
Notes:  
Notes: TA = 0 - 85°C; VDD = 3.3 V +/-5%; CL=2pF, Rs=0Ω (unless specified otherwise)  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz  
3 Slew rate emastured through V_swing voltage range centered about differential zero  
4 Vcross is defined at the voltage where Clock = Clock#.  
5 Only applies to the differential rising edge (Clock rising, Clock# falling.)  
6 CPU group skew is nominally 0ps.  
Electrical Characteristics - Phase Jitter  
MIN  
TYP  
29  
MAX  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS NOTES  
tjphPCIe1  
86  
PCIe Gen 1 REFCLK phase jitter  
PCIe Gen 2 REFCLK phase jitter  
Lo-band content  
PCIe Gen 2 REFCLK phase jitter  
ps  
ps  
(RMS)  
ps  
1,2,3  
tjphPCIe2Lo  
tjphPCIe2Hi  
1,2,4  
1.1  
1.9  
3
Jitter, Phase  
1,2,4  
3.1  
Hi-band content  
(RMS)  
Notes on Phase Jitter:  
1 See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production.  
2 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-1 2  
3 Applies to all SRC outputs.  
4 Applies to SRC(1:4) outputs.  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
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VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Electrical Characteristics–Input/Supply/Common Output Parameters  
PARAMETER  
Ambient Operating Temp  
SYMBOL  
Tambient  
VDD  
CONDITIONS  
MIN  
0
3.135  
TYP  
25  
3.3  
MAX  
85  
3.465  
UNITS Notes  
°C  
V
-
Supply Voltage  
Supply Voltage  
VDD_CORE_1.5  
Supply Voltage  
1.425  
1.5  
1.575  
V
V
VDD_LVIO  
VIHSE  
Supply Voltage  
0.9975  
2
1.05  
1.575  
DD + 0.3  
V
Input High Voltage  
Input Low Voltage  
Single-ended 3.3V inputs  
Single-ended 3.3V inputs  
V
V
7
7
VILSE  
VIH_LI  
VIL_LI  
VIH_FS  
VSS - 0.3  
0.8  
Latched Input High Voltage  
Latched Input Low Voltage  
Single-ended 3.3V Latched Inputs  
Single-ended 3.3V Latched Inputs  
Low threshold inputs (FS(C:B))  
2
VDD + 0.3  
0.8  
V
V
V
VSS - 0.3  
0.7  
Low Threshold Latched Input-  
High Voltage  
VDD+0.3  
Low Threshold Latched Input-  
Low Voltage  
VIL_FS  
IIN  
V
SS - 0.3  
-5  
Low threshold inputs (FS(C:B))  
VIN = VDD , VIN =GND  
0.35  
5
V
Input Leakage Current  
uA  
6
Inputs with pull up or pull down  
resistors  
IINRES  
Input Leakage Current  
-200  
2.4  
200  
uA  
VIN = VDD , VIN =GND  
Output High Voltage  
Output Low Voltage  
VOHS E  
VOLSE  
Single-ended outputs, IOH = -1mA  
Single-ended outputs, IOL = 1 mA  
Full Active, CL = Full load; IDD 3.3V  
Full Active, CL = Full load; IDD 1.5V  
V
5
5
0.4  
25  
35  
V
IDDOP3.3  
IDDOP1.5  
17.0  
29.5  
mA  
mA  
Operating Supply Current  
IDDOP1.0 5  
Full Active, CL = Full load; IDD LVIO  
31.4  
35  
mA  
IDDPD3.3  
IDDPD1.5  
IDDPDLVIO  
IDDW OL3.3  
IDDW OL1.5  
IDDWOLLVIO  
Fi  
Power down mode, 3.3V Rail  
Power down mode, 1.5V Rail  
Power down mode, 1.05V Rail  
Wake On Lan mode, 3.3V Rail  
Wake On Lan mode, 1.5V Rail  
Wake On Lan mode, LVIO Rail  
VDD = 3.3 V  
0.3  
0.4  
0.0  
4.0  
9.0  
0.0  
1
1
mA  
mA  
mA  
mA  
mA  
mA  
MHz  
nH  
9
9
Powerdown Current  
0.01  
5
9
10  
10  
10  
8
Wake-On-Lan Current  
12  
0.01  
15  
7
Input Frequency  
Pin Inductance  
Lpin  
CIN  
Logic Inputs  
Output pin capacitance  
X1 & X2 pins  
1.5  
5
pF  
COUT  
Input Capacitance  
Clk Stabilization  
6
pF  
CINX  
6
pF  
From VDD Power-Up or de-assertion  
of PD to 1st clock  
TSTAB  
1.8  
ms  
Output stop after CLKREQ#  
deasserted  
Output run after CLKREQ# asserted  
TCROFF  
TCRON  
TSTOP  
Tstop_CR_off  
Trun_CR_on  
Tstop  
2
2
2
3
3
3
Clocks  
Clocks  
Clocks  
CPU or PCI stop after  
CPU or PCI STOP# assertion  
CPU or PCI run after  
TRUN  
Trun  
2
3
Clocks  
CPU or PCI STOP# de-assertion  
TFALL  
TRISE  
Tfall_SE  
Trise_SE  
10  
10  
3.6  
0.4  
ns  
ns  
V
Fall/rise time of all 3.3V control inputs  
from 20-80%  
VDD  
SMBus Voltage  
Low-level Output Voltage  
Current sinking at  
2.7  
4
3.3  
VOLSMB  
@ IPULLUP  
V
IPULLUP  
TRI2C  
SMB Data Pin  
mA  
V
OLSMB = 0.4 V  
SCLK/SDATA  
Clock/Data Rise Time  
SCLK/SDATA  
Clock/Data Fall Time  
Maximum SMBus Operating  
Frequency  
(Max VIL - 0.15) to  
(Min VIH + 0.15)  
(Min VIH + 0.15) to  
(Max VIL - 0.15)  
1000  
300  
100  
33  
ns  
ns  
TFI2C  
FSMBUS  
fSSMOD  
kHz  
kHz  
Spread Spectrum Modulation  
Frequency  
Triangular Modulation  
30  
31.5  
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).  
1 Intentionally blank  
2 Maximum VIH is not to exceed VDD  
3 Human Body Model  
4 Operation under these conditions is neither implied, nor guaranteed.  
5Signal is required to be monotonic in this region.  
6 Input leakage current does not include inputs with pull-up or pull-down resistors  
7 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, ITP_EN, SCLK, SDATA, CLKPWRgD/PD#, SEL_PCI and CLKREQ# inputs if selected.  
8 For margining purposes only. Normal operation should have Fin = 14.318MHz +/-50ppm  
9 Standard powerdown with Wake on LAN disabled.  
10 Powerdown with Wake on LAN enabled  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
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VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Electrical Characteristics–PCICLK/PCICLK_F  
PARAMETER  
Output Impedance  
Long Accuracy  
SYMBOL  
RDSP  
CONDITIONS  
VO = VDD*(0.5)  
MIN  
12  
-100  
2.4  
TYP  
0
MAX  
55  
100  
UNITS NOTES  
Ω
ppm  
V
1
2
1
ppm  
VOH  
see Tperiod min-max values  
IOH = -1 mA  
Output High Voltage  
VOL  
IOL = 1 mA  
Output Low Voltage  
0.4  
-33  
V
mA  
mA  
mA  
mA  
V/ns  
V/ns  
%
1
1
1
1
1
1
1
1
1
1
1
V OH @MIN = 1.0 V  
-33  
30  
IOH  
Output High Current  
V
OH@MAX = 3.135 V  
VOL @ MIN = 1.95 V  
OL @ MAX = 0.4 V  
Output Low Current  
IOL  
V
38  
4
tSLR  
tFLR  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Duty Cycle  
Measured from 0.8 to 2.0 V  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
1
1
1.4  
1.5  
4
dt1  
45  
47.7  
55  
tskew  
tskew  
tjcyc-cyc  
VT = 1.5 V  
VT = 1.5 V  
VT = 1.5 V  
Pin to Pin Skew  
206  
200  
139  
250  
200  
500  
ps  
Intentional PCI to PCI delay  
Jitter, Cycle to cycle  
100  
ps  
ps  
Electrical Characteristics–USB48MHz  
PARAMETER  
Long Accuracy  
SYMBOL  
ppm  
CONDITIONS  
see Tperiod min-max values  
IOH = -1 mA  
MIN  
-100  
TYP  
0
MAX  
100  
UNITS NOTES  
ppm  
1,2  
VOH  
Output High Voltage  
Output Low Voltage  
2.4  
-29  
29  
V
1
VOL  
IOL = 1 mA  
0.4  
-23  
V
1
V OH @MIN = 1.0 V  
mA  
mA  
mA  
mA  
V/ns  
V/ns  
%
1
1
1
1
1
1
1
1
IOH  
Output High Current  
Output Low Current  
VOH@MAX = 3.135 V  
VOL @ MIN = 1.95 V  
VOL @ MAX = 0.4 V  
Measured from 0.8 to 2.0 V  
IOL  
27  
2
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Duty Cycle  
tSLR  
tFLR  
1
1
1.4  
1.4  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
2
dt1  
45  
47.3  
123  
55  
350  
tjcyc-cyc  
VT = 1.5 V  
Jitter, Cycle to cycle  
ps  
Electrical Characteristics–25MHz  
PARAMETER  
Long Accuracy  
SYMBOL  
ppm  
CONDITIONS  
see Tperiod min-max values  
IOH = -1 mA  
MIN  
-30  
TYP  
0
MAX  
30  
UNITS NOTES  
ppm  
1,2  
VOH  
Output High Voltage  
Output Low Voltage  
2.4  
-29  
29  
V
1
VOL  
IOL = 1 mA  
0.4  
-23  
V
1
V OH @MIN = 1.0 V  
mA  
mA  
mA  
mA  
V/ns  
V/ns  
%
1
1
1
1
1
1
1
1
IOH  
Output High Current  
Output Low Current  
VOH@MAX = 3.135 V  
VOL @ MIN = 1.95 V  
VOL @ MAX = 0.4 V  
Measured from 0.8 to 2.0 V  
IOL  
27  
2
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Duty Cycle  
tSLR  
tFLR  
0.5  
0.5  
45  
1.4  
1.6  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
2
dt1  
49.3  
170  
55  
200  
tjcyc-cyc  
VT = 1.5 V  
Jitter, Cycle to cycle  
ps  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
15  
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9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Electrical Characteristics–REF-14.318MHz  
PARAMETER  
Long Accuracy  
SYMBOL  
ppm  
CONDITIONS  
see Tperiod min-max values  
IOH = -1 mA  
MIN  
-100  
2.4  
TYP  
0
MAX  
100  
UNITS Notes  
ppm  
V
1,2  
1
Output High Voltage  
Output Low Voltage  
VOH  
VOL  
IOL = 1 mA  
0.4  
-23  
V
1
VOH @MIN = 1.0 V,  
VOH@MAX = 3.135 V  
VOL @MIN = 1.95 V,  
VOL @MAX = 0.4 V  
Measured from 0.8 to 2.0 V  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
Output High Current  
Output Low Current  
IOH  
IOL  
-29  
29  
mA  
mA  
1
1
27  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Duty Cycle  
tSLR  
tFLR  
dt1  
1
1
45  
1.5  
1.6  
50.1  
138  
4
4
55  
V/ns  
V/ns  
%
1
1
1
1
Jitter, Cycle to cycle  
tjcyc-cyc  
VT = 1.5 V  
1000  
ps  
Notes for PCI, USB48M, 25M and 14.318M outputs  
TA = 0 - 85°C; VDD = 3.3 V +/-5%; CL=5pF, Rs is according to Data Sheet Loading Table for 1 load (unless specified otherwise)  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz  
3 The average period over any 1us period of time  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
16  
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9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Single-ended Clock Tolerances No Spread- Spec  
REF  
PCI  
48M  
25M  
PPM tolerance  
Cycle to Cycle Jitter  
Spread  
ppm  
ps  
%
100  
1000  
0.00%  
100  
500  
0.00%  
100  
350  
0.00%  
30  
200  
0.00%  
Clock Periods - Single-ended Outputs with Spread Spectrum Disabled - Spec  
Measurement Window  
1 Clock  
1us  
0.1s  
0.1s  
0.1s  
1us  
1 Clock  
Center  
Freq.  
MHz  
-SSC  
- ppm  
+ ppm  
+SSC  
Short-Term  
Average  
Max  
SSC OFF  
-c2c jitter  
AbsPer  
Min  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term 0 ppm Period Long-Term  
Average  
Average  
Min  
Nominal  
Average  
Max  
Min  
14.318  
33.333  
48.000  
25.000  
68.83429  
29.49700  
20.48125  
39.79880  
69.83429  
29.99700  
20.83125  
39.99880  
69.84128  
30.00000  
20.83333  
40.00000  
69.84826  
30.00300  
20.83542  
40.00120  
70.84826  
30.50300  
21.18542  
40.20120  
ns  
ns  
ns  
ns  
1,2  
1,2  
1,2  
1,2  
REF  
PCI  
48M  
25M  
Single-ended Clock Tolerances with Spread Spectrum Enabled - Spec  
REF  
PCI  
48M  
25M  
PPM tolerance  
Cycle to Cycle Jitter  
Spread  
ppm  
ps  
%
100  
1000  
0.00%  
100  
500  
-0.50%  
100  
350  
0.00%  
30  
200  
0.00%  
Clock Periods - Single-ended Outputs with Spread Spectrum Enabled - Spec  
Measurement Window  
1 Clock  
1us  
0.1s  
0.1s  
0.1s  
1us  
1 Clock  
Center  
Freq.  
MHz  
SSC ON  
Units Notes  
-SSC  
- ppm  
+ ppm  
+SSC  
Short-Term  
Average  
Max  
-c2c jitter  
AbsPer  
Min  
+c2c jitter  
AbsPer  
Max  
Short-Term Long-Term 0 ppm Period Long-Term  
Average  
Min  
Average  
Min  
Nominal  
Average  
Max  
REF  
PCI  
48M  
25M  
14.318  
33.250  
48.000  
25.000  
N/A  
30.07519  
N/A  
ns  
ns  
ns  
ns  
1,2  
1,2  
1,2  
1,2  
29.49718  
29.99718  
30.07218  
30.07218  
30.14718  
30.64718  
N/A  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818MHz.  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
17  
9VRS4338D  
REV A 022616  
9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Differential Clock Tolerances  
CPU  
SRC  
DOT96  
SATA  
PPM tolerance  
Cycle to Cycle Jitter  
Spread  
ppm  
ps  
%
100  
85  
-0.50%  
100  
85  
-0.50%  
100  
250  
0.00%  
100  
85  
0.00%  
Clock Periods–Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC OFF  
Units Notes  
-c2c jitter  
AbsPer  
Min  
+c2c jitter  
AbsPer  
Max  
Short-Term Long-Term 0 ppm Period Long-Term  
Average  
Min  
Average  
Min  
Nominal  
Average  
Max  
100.00  
133.33  
166.67  
200.00  
266.67  
333.33  
400.00  
100.00  
100.00  
96.00  
9.91400  
7.41425  
5.91440  
4.91450  
3.66462  
2.91470  
2.41475  
9.91400  
9.91400  
10.16563  
9.99900  
7.49925  
5.99940  
4.99950  
3.74962  
2.99970  
2.49975  
9.99900  
9.99900  
10.41563  
10.00000  
7.50000  
6.00000  
5.00000  
3.75000  
3.00000  
2.50000  
10.00000  
10.00000  
10.41667  
10.00100  
7.50075  
6.00060  
5.00050  
3.75037  
3.00030  
2.50025  
10.00100  
10.00100  
10.41771  
10.08600  
7.58575  
6.08560  
5.08550  
3.83537  
3.08530  
2.58525  
10.08600  
10.08600  
10.66771  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
CPU  
SRC  
SATA  
DOT96  
Clock Periods–Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC ON  
Units Notes  
-c2c jitter  
AbsPer  
Min  
+c2c jitter  
AbsPer  
Max  
Short-Term Long-Term 0 ppm Period Long-Term  
Average  
Min  
Average  
Min  
Nominal  
Average  
Max  
99.75  
133.00  
166.25  
199.50  
266.00  
332.50  
399.00  
99.75  
9.91406  
7.41430  
5.91444  
4.91453  
3.66465  
2.91472  
2.41477  
9.91406  
9.99906  
7.49930  
5.99944  
4.99953  
3.74965  
2.99972  
2.49977  
9.99906  
10.02406  
7.51805  
6.01444  
5.01203  
3.75902  
3.00722  
2.50602  
10.02406  
10.02506  
7.51880  
6.01504  
5.01253  
3.75940  
3.00752  
2.50627  
10.02506  
10.02607  
7.51955  
6.01564  
5.01303  
3.75977  
3.00782  
2.50652  
10.02607  
10.05107  
7.53830  
6.03064  
5.02553  
3.76915  
3.01532  
2.51277  
10.05107  
10.13607  
7.62330  
6.11564  
5.11053  
3.85415  
3.10032  
2.59777  
10.13607  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
CPU  
SRC  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818MHz.  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
18  
9VRS4338D  
REV A 022616  
9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Power-up Sequencing Requirements  
Marking Diagram  
ICS  
VRS4338DL  
YYWW  
COO  
LOT  
Notes:  
1. Line 1: company name  
2. Line 2: truncated part number.  
3. “L” denotes RoHS compliant package.  
4. Line 3: YYWW is the last two digits of the year and week that the part was assembled.  
5. Line 4: Country of origin.  
6. Line 5: LOT is the lot number.  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
19  
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9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Package Outline and Dimensions (NDG48)  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
20  
9VRS4338D  
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9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Package Outline and Dimensions (NDG48), cont.  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
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VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Ordering Information  
Part / Order Number Shipping Packaging  
Package  
48-pin MLF  
48-pin MLF  
Temperature  
0 to +85° C  
0 to +85° C  
9VRS4338DKLF  
9VRS4338DKLFT  
Trays  
Tape and Reel  
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
“D” is the device revision designator (will not correlate with the datasheet revision).  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
Revision History  
Rev.  
A
Issue Date Intiator Description  
2/26/2016 RDW Updated POD drawings with current NDG48 spec.  
Page #  
Various  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
22  
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9VRS4338D  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
SYNTHESIZERS  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
800-345-7015  
408-284-8200  
Fax: 408-284-2775  
Tech Support  
www.idt.com/go/support  
Corporate Headquarters  
Integrated Device Technology, Inc.  
www.idt.com  
© 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated  
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or  
registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
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