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9VRS4339BKLFT

型号：

9VRS4339BKLFT

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

21 页

PDF大小：

322 K

下载PDF手册
DATASHEET  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
9VRS4339B  
General Description  
Features/Benefits  
The 9VRS4339B is a Intel CK-NET compatible main clock  
for Intel Netbooks, conforming to the CK-NET specification.  
It is driven with a 25MHz crystal and generates a variety of  
clocks, including an LCD clock. An SMBus interface allows  
full control of the device.  
• Supports Wake_On_LAN (see pin55 pin description)  
• Selectable spread % on CPU, SRC, PCI; Supports  
margining  
• Uses external 25MHz crystal, external crystal load caps  
are required for frequency tuning  
• CLKREQ# pins; Support SRC power management  
• Low power differential clock outputs driving 100 ohm  
differential traces; reduced powe  
• Integrated 33 ohm series resistors on all differential  
outputs; reduced board space  
Output Features  
• 2 – 0.8V push-pull differential CPU pairs  
• 5 – 0.8V push-pull differential SRC pairs  
• 1 – 0.8V push-pull differential SATA pair  
• 1 – 0.8V push-pull differential DOT96/SRC pair  
• 1 – 0.8V push-pull differential LCD100 pair  
• 1 – 0.8V push-pull differential CPU_ITP/SRC pair  
• 2 – PCI (33MHz)  
Key Specifications  
• CPU outputs cycle-to-cycle jitter <85ps  
• SRC cycle-to-cycle jitter <85ps  
• 1 – PCI_F, (33MHz) free-running  
• 1 – USB_48MHz  
• 1 – 48MHz  
• SRC meets PCIEX Gen2 specifications  
• SATA outputs cycle-to-cycle jitter <125ps  
• PCI outputs cycle-to-cycle jitter <500ps  
• 1 – 25MHz  
•
100ppm frequency accuracy on all clocks  
• 1 – 27MHz/PCI  
• 1 – 14.318MHz  
Pin Configuration  
56 55 54 53 52 51 50 49 48 47 46 45 44 43  
SRC2_LPRS  
SRC2#_LPRS  
GNDSRC  
1
2
3
4
5
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
X2  
X1  
VDD25_3.3  
25M  
SRC6_LPRS  
SRC6#_LPRS  
SRC3_LPRS  
SRC3#_LPRS  
PCI_STOP#_3.3  
VDDSRC_LVIO  
SRC4_LPRS  
SRC4#_LPRS  
SATA_LPRS  
SATA#_LPRS  
GNDSATA  
SDATA_3.3  
SCLK_3.3 6  
VDDPCI_3.3 7  
vITP_EN/PCI_F1_2x 8  
FSLB/PCI2_2x 9  
9VRS4339B  
10  
11  
CLKREQA#/PCI3_2x  
GNDPCI  
GND14M 12  
14M_2X/FSLC 13  
VDD14_3.3 14  
15 16 17 18 19 20 21 22 23 24 25 26 27 28  
v prefix indicates internal pull-down resistor  
^ prefix indicates internal pull-up resistor  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
1
9VRS4339B  
REV A 010312  
9VRS4339B  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Pin Descriptions  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
1
2
3
4
5
6
7
X2  
X1  
OUT Crystal output, nominally 25MHz  
IN  
Crystal input, nominally 25MHz  
VDD25_3.3  
25M  
SDATA_3.3  
SCLK_3.3  
VDDPCI_3.3  
PWR Power pin for crystal and 25MHz output, nominal 3.3V  
OUT 3.3V 25MHz clock output  
I/O  
Data pin for SMBus circuitry, 3.3V tolerant.  
OUT Clock pin of SMBus circuitry, 3.3V tolerant.  
PWR Power supply for PCI clocks, nominal 3.3V  
ITP enable latched input  
ITP_Enable Selects the functionality of the CPU_ITP/SRC output as follows:  
8
9
vITP_EN/PCI_F1_2x  
FSLB/PCI2_2x  
I/O  
1 = CPU_ITP output  
0 = SRC1 output  
/ Free-Running 3.3V PCI clock output, default to drive 2 loads.  
3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see  
input electrical characteristics for Vil_FS and Vih_FS values / 3.3V PCI clock output,  
default to drive 2 loads.  
I/O  
3.3V real-time output enable for PCI Express (SRC) outputs. SMBus selects which  
outputs are controlled. Pin function is programmable through SMBus. See  
CLKREQ# Control Table and SRC Power Management Table for details  
0 = controlled outputs are enabled  
10 CLKREQA#/PCI3_2x  
I/O  
1 = controlled outputs are Low/Low  
/ 3.3V PCI clock output, default to drive 2 loads. .  
11 GNDPCI  
12 GND14M  
PWR Ground pin for the PCI outputs  
PWR Ground pin for the 14.318MHz output  
3.3V 14.318 MHz clock output, default to drive 2 loads / 3.3V tolerant input for CPU  
13 14M_2X/FSLC  
I/O  
frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS  
values.  
14 VDD14_3.3  
15 VDD48_3.3  
PWR Power pin for 14.318MHz output, nominal 3.3V  
PWR Power pin for 48MHz outputs, nominal 3.3V  
Input latched pin to select Pin23/24 as DOT 96MHz clock or SRC clock  
1 = DOT96 output  
0 = SRC5 output  
16 ^DOT96_SEL/USB48M  
I/O  
/ 3.3V 48MHz USB clock output.  
3.3V real-time output enable for PCI Express (SRC) outputs. SMBus selects which  
outputs are controlled. Pin function is programmable through SMBus. See  
CLKREQ# Control Table and SRC Power Management Table for details  
0 = controlled outputs are enabled  
17 CLKREQC#/48M  
I/O  
1 = controlled outputs are Low/Low  
/ 3.3V 48MHz clock output  
18 GND48  
PWR Ground pin for 48MHz outputs  
3.3V real-time output enable for PCI Express (SRC) outputs. SMBus selects which  
outputs are controlled.  
0 = controlled outputs are enabled  
1 = controlled outputs are Low/Low  
19 CLKREQB#  
20 VDD27  
IN  
PWR Power pin for 27MHz output , nominal 3.3V  
3.3V input latch pin to select this pin as 27M output or PCI4 clock output. This pin has  
an internal pulldown resistor. Latch functionality is as follows:  
0 = 27MHz output  
21 vSEL_PCI/27M_PCI4_2X  
I/O  
1 = 33.33MHz PCI output  
22 GND27  
PWR Ground pin for the 27MHz output  
True clock of push-pull DOT96 or SRC clock with integrated series resistor. No 50  
ohm pull down needed. Default is pending on Pin16 DOT96_SEL.  
23 DOT96_LPRS/SRC5_LPRS  
OUT  
Complement clock of push-pull DOT96 or SRC clock with integrated series resistor.  
No 50 ohm pull down needed. Default is pending on Pin16 DOT96_SEL.  
PWR Power pin for core PLL's, nominal 1.5V.  
24 DOT96#_LPRS/SRC5#_LPRS  
25 VDD_CORE_1.5  
OUT  
True clock of differential push-pull LCD100 output with integrated 33ohm series  
resistor. No 50ohm resistor to GND needed.  
26 LCD100_LPRS  
OUT  
Complementary clock of differential push-pull LCD100 output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
PWR Ground pin for LCD clock output  
27 LCD100#_LPRS  
28 GNDLCD  
OUT  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
2
9VRS4339B  
REV A 010312  
9VRS4339B  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Pin Descriptions (cont.)  
29 GNDSATA  
PWR Ground pin for the SATA outputs  
Complementary clock of low power differential push-pull SATA clock pair with  
integrated 33ohm series resistor. No 50 ohm resistor to GND needed.  
True clock of low power differential push-pull SATA clock pair with integrated 33ohm  
series resistor. No 50 ohm resistor to GND needed.  
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
30 SATA#_LPRS  
OUT  
OUT  
OUT  
OUT  
31 SATA_LPRS  
32 SRC4#_LPRS  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series  
resistor. No 50ohm resistor to GND needed.  
33 SRC4_LPRS  
34 VDDSRC_LVIO  
35 PCI_STOP#_3.3  
PWR Power pin for SRC I/O, nominally 1.05V to 1.5V from external power supply  
Stops all stoppable PCI, SATA and SRC clocks when low. Free-Running PCI, SATA  
IN  
and SRC clocks are not effected by this input. This input is 3.3V tolerant.  
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series  
resistor. No 50ohm resistor to GND needed.  
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
36 SRC3#_LPRS  
37 SRC3_LPRS  
38 SRC6#_LPRS  
OUT  
OUT  
OUT  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series  
resistor. No 50ohm resistor to GND needed.  
PWR Ground pin for the SRC outputs  
39 SRC6_LPRS  
40 GNDSRC  
OUT  
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
41 SRC2#_LPRS  
OUT  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series  
resistor. No 50ohm resistor to GND needed.  
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
42 SRC2_LPRS  
43 SRC#7_LPRS  
OUT  
OUT  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series  
resistor. No 50ohm resistor to GND needed.  
44 SRC7_LPRS  
OUT  
45 CPU_STOP#_3.3  
IN  
Stops all stoppable CPU clocks when enabled. This is a 3.3V tolerant input.  
Complementary clock of low power differential CPU_ITP/SRC pair with integrated  
33ohm series resistor. No 50ohm resistor to GND needed. The pin function is  
46 CPU_ITP#/SRC1#_LPRS  
47 CPU_ITP/SRC1_LPRS  
OUT determined by the latched value on ITP_EN:  
0 = SRC1#  
1 = CPU_ITP#  
True clock of low power differential CPU_ITP/SRC pair with integrated 33ohm series  
resistor. No 50ohm resistor to GND needed. The pin function is determined by the  
OUT latched value on ITP_EN:  
0 = SRC1  
1 = CPU_ITP  
48 VDD_CORE_1.5  
49 VDDCPU_LVIO  
PWR Power pin for core PLL, nominal 1.5V  
PWR Power pin for CPU I/O, nominally 1.05V to 1.5V from external power supply  
Complementary clock of differential pair 0.8V push-pull CPU output with integrated  
33ohm series resistor. No 50 ohm resistor to GND needed.  
50 CPU1#_LPRS  
OUT  
True clock of differential pair 0.8V push-pull CPU output with integrated 33ohm series  
resistor. No 50 ohm resistor to GND needed.  
PWR Ground pin for the CPU outputs  
51 CPU1_LPRS  
52 GNDCPU  
OUT  
Complementary clock of differential pair 0.8V push-pull CPU output with integrated  
33ohm series resistor. No 50 ohm resistor to GND needed.  
53 CPU0#_LPRS  
OUT  
True clock of differential pair 0.8V push-pull CPU output with integrated 33ohm series  
resistor. No 50 ohm resistor to GND needed.  
54 CPU0_LPRS  
OUT  
This 3.3V LVTTL input notifies device to sample latched inputs and start up on first  
high assertion or exit Power Down Mode on subsequent assertions. When WLAN  
enable in Byte13 bit 5 =1, device will enter Wake-On-LAN mode with 25MHz being  
free-running.  
1 = Normal operation  
0 = Power Down Mode or Wake-On-LAN mode  
55 CLKPWRGD/PD#_3.3  
56 GND25  
IN  
Note: For lowest power saving during WOL mode, it is mandatory to connect 3.3V  
and 1.5V core VDD pins to standby power and suspend/remove VDDIO pins.  
PWR Ground pin for 25MHz  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
3
9VRS4339B  
REV A 010312  
9VRS4339B  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Block Diagram  
CPUCLK  
SRCCLK  
Programmable  
SS CPU/SRC  
PLL  
25MHz  
SATACLK  
FIX PLL1  
PCICLK  
DOT96  
USB48, 48M  
LCDCLK  
Programmable  
SS LCD PLL  
/2  
27FIX  
FIX PLL2  
14.318M  
25MHz  
Series Resistors for Single Ended Outputs  
Number of Loads Actually Driven.  
Number of  
Loads  
to Drive  
Match Point for N & P  
Voltage / Current (mA)  
1 Load Rs = 2 Loads Rs= 3 Loads Rs =  
D.C.Drive Strength  
1
2
0.56 / 33 (17 )  
33 [39 ]  
-
-
-
Ω
Ω
Ω
0.92 / 66 (14 )  
39 [43 ]  
22 [27 ]  
Ω Ω  
Ω
Ω
Ω
Notes:  
1. Preferred drive strengths using CK505 clock sources. Transmission lines to load do not share series  
resistors.  
2. Desktop/Mobile Platforms with Zo = 50/55 ohms use the first resistor value.  
3. Systems with Zo = 60 ohms use the resistor values in brackets [ ].  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
4
9VRS4339B  
REV A 010312  
9VRS4339B  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Table 1: CPU/SRC PLL Spread Frequency Selection  
CPU/SRC  
SS1  
SS0  
FSLC  
FSLB  
SPREAD  
%
CPU  
MHz  
SRC  
MHz  
SATA  
MHz  
PCI  
MHz  
SS Select  
(B1b6)  
(B1b5) (B1b4) (B0b7)  
(B0b6)  
-0.50%  
-0.50%  
-0.50%  
-0.50%  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
133.33  
166.67  
100.00  
200.00  
133.33  
166.67  
100.00  
200.00  
133.33  
166.67  
100.00  
200.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
-0.40%  
-0.40%  
-0.40%  
-0.40%  
-0.30%  
-0.30%  
-0.30%  
-0.30%  
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
OFF  
OFF  
OFF  
OFF  
133.33  
166.67  
100.00  
200.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
33.33  
33.33  
33.33  
33.33  
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
+/-0.25%  
+/-0.25%  
+/-0.25%  
+/-0.25%  
133.33  
166.67  
100.00  
200.00  
133.33  
166.67  
100.00  
200.00  
133.33  
166.67  
100.00  
200.00  
133.33  
166.67  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
33.33  
+/-0.20%  
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
+/-0.20%  
+/-0.20%  
+/-0.20%  
+/-0.15%  
+/-0.15%  
+/-0.15%  
+/-0.15%  
OFF  
OFF  
OFF  
OFF  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
100.00  
200.00  
100.00  
100.00  
100.00  
100.00  
33.33  
33.33  
* Bold is default  
Table 2: LCD Spread Selection Table  
FS2  
0
0
1
1
1
0
0
1
FS1  
1
1
0
0
1
1
1
0
FS0  
0
1
0
1
0
0
1
0
LCD SS SPREAD LCD100  
-0.50%  
0
0
0
0
0
1
1
1
1
1
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
100.00  
-1.0%  
-1.5%  
-2.0%  
-2.50%  
+/-0.25%  
+/-0.5%  
+/-0.75%  
+/-1.0%  
+/-1.25%  
1
1
0
1
1
0
* Bold is default  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
5
9VRS4339B  
REV A 010312  
9VRS4339B  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Power Distribution Table  
Pin Number  
3.3V VDD 1.5V VDD 1.05-1.5V VDD  
Description  
GND  
56  
11  
3
7
-
-
-
-
25MHz Crystal I/O; Internal Control Logic; 25MHz Output  
PCICLK Outputs  
14  
15  
20  
-
-
-
-
-
-
25  
-
-
-
-
-
34  
-
49  
12  
18  
22  
28, 29  
40  
14.318MHz & 27MHz outputs, 14/27MHz PLL Digital  
48MHz output  
27MHz output, 14/27MHz PLL analog  
DOT96 Fix PLL Analog & Digital, LCD100 PLL Analog & Digital  
SRC Outputs  
48  
-
52  
52  
CPU/SRC PLL Analog & Digital  
CPU Outputs  
-
CPU Power Management Table  
CLKPWRGD/P  
SMBus  
Register OE  
Enable  
CPU (0, 1, ITP)  
CPU_STOP#  
D#_3.3  
True O/P  
Running  
High  
Comp. O/P  
Running  
Low  
1
1
0
X
1
0
Enable  
X
X
X
Low/20K  
Low/20K  
Low  
Low  
Disable  
DOT96 and SATA Power Management Table  
SATA  
PEREQC# Controlled  
SATA  
CLKPWRGD/P  
D#_3.3  
SMBus  
Register OE  
DOT96  
PCI_STOP# CLKREQC#  
PEREQC# Not-Controlled  
True O/P  
Comp. O/P  
True O/P  
Comp. O/P  
True O/P  
Comp. O/P  
1
Enable  
1
0
Running  
Running  
Running  
Running  
Running  
Running  
1
0
X
Enable  
X
Disable  
1
X
X
1
X
X
Low/20K  
Low/20K  
Low/20K  
Low  
Low  
Low  
Running  
Low/20K  
Low/20K  
Running  
Low  
Low  
Running  
Low/20K  
Low/20K  
Running  
Low  
Low  
SRC Power Management Table  
SRC controlled by  
CLKREQx#  
SRC not controlled by  
CLKREQx#  
SRC controlled by  
CLKREQx#  
SRC not controlled by  
CLKREQx#  
CLKPWRGD/P  
D#_3.3  
SMBus  
Register OE  
PCI_STOP# CLKREQx#  
Free-Running  
Comp. O/P True O/P  
Running  
Stoppable  
Comp. O/P True O/P Com p. O/P  
Running  
True O/P  
Running  
C omp. O/P  
True O/P  
Running  
1
1
1
1
0
X
Enable  
Enable  
Enable  
Enable  
Enable  
Disable  
1
1
0
0
X
X
0
1
0
1
X
X
Running  
Running  
Running  
Running  
Low/20K  
Low/20K  
Running  
Running  
Running  
Running  
Low  
Running  
Running  
High  
Running  
Running  
Low  
Low/20K  
Running  
Low/20K  
Low/20K  
Low/20K  
Low  
Running  
Low  
Low  
Low  
Low/20K  
High  
Low/20K  
Low/20K  
Low/20K  
Low  
Low  
Low  
Low  
Low  
High  
Low  
Low/20K  
Low/20K  
Low  
Low  
Low  
SIngle-ended Power Management Table  
PCI_F1, PCI2, PCI4  
PCI3  
25M  
CLKPWRGD/P  
D#_3.3  
SMBus  
Register OE  
PCI_STOP#  
14.318M  
USB48  
48M  
27MHz  
WOL  
WOL  
Disabled  
Running  
Running  
Low  
Free-run  
Stoppable  
Free-run  
Stoppable  
Enabled  
Running  
Running  
Running  
Low  
1
1
0
0
1
Enable  
Enable  
Enable  
Disable  
Disable  
1
0
X
X
X
Running  
Running  
Hi-Z  
Running  
Low  
Hi-Z  
Running  
Running  
Low  
Low  
Low  
Running  
Low  
Low  
Low  
Low  
Running  
Running  
Hi-Z  
Running  
Running  
Hi-Z  
Running  
Running  
Low  
Running  
Running  
Hi-Z  
Hi-Z  
Hi-Z  
Low  
Hi-Z  
Hi-Z  
Low  
Hi-Z  
Low  
Low  
Low  
Low  
Low  
Low  
Low  
Low  
CLKREQ# Control Table  
SRC/SATA  
controlled  
CLKREQ#  
A
B
SRC1, 2, 3  
SRC4, 6  
SRC5, 7,  
SATA  
C
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
6
9VRS4339B  
REV A 010312  
9VRS4339B  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
General SMBus Serial Interface Information for 9VRS4339  
How to Write  
How to Read  
• Controller (host) sends a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) will send a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the byte count = X  
• IDT clock will acknowledge  
• Controller (host) will send a separate start bit  
• Controller (host) sends the read address  
• IDT clock will acknowledge  
• IDT clock will send the data byte count = X  
• IDT clock sends Byte N+X-1  
• Controller (host) starts sending Byte N through Byte  
N+X-1  
• IDT clock will acknowledge each byte one at a time  
• Controller (host) sends a Stop bit  
• IDT clock sends Byte 0 through Byte X (if X was  
(H)  
written to Byte 8)  
• Controller (host) will need to acknowledge each byte  
• Controller (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Write Operation  
Index Block Read Operation  
Controller (Host)  
starT bit  
Slave Address  
IDT (Slave/Receiver)  
Controller (Host)  
starT bit  
IDT (Slave/Receiver)  
T
T
Slave Address  
WR  
WRite  
WR  
WRite  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
Beginning Byte = N  
RT  
Repeat starT  
Slave Address  
ReaD  
RD  
ACK  
O
O
O
O
O
O
Data Byte Count=X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
O
O
O
P
stoP bit  
O
O
O
Read Address  
Write Address  
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
D3  
D2  
(H)  
(H)  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
7
9VRS4339B  
REV A 010312  
9VRS4339B  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
SMBus Table: Frequency Select, PD Config Source Select Register  
Byte 0  
Bit 7  
Bit 6  
Name  
FSLC  
FSLB  
Control Function  
Freq Select Bit 1  
Freq Select Bit 0  
Type  
0
1
Default  
Latch  
Latch  
RW See Table 1: CPU/SRC PLL Frequency &  
RW  
RW  
Spread Selection Table  
Enables Control of CPU1 with  
CPU_STOP  
Enables Control of CPU0 with  
CPU_STOP  
CPU1 STOP EN  
CPU0 STOP EN  
Free-Running  
Free-Running  
Stoppable  
Stoppable  
0
0
Bit 5  
Bit 4  
RW  
PCI_SSEL  
SRC_SSEL  
SATA_SSEL  
PD Config  
PCI Source Select  
RW CPU/SRC SS PLL  
RW CPU/SRC SS PLL  
RW CPU/SRC SS PLL  
FIX PLL  
FIX PLL  
FIX PLL  
0
0
0
1
Bit 3  
Bit 2  
Bit 1  
Bit 0  
SRC Source Select  
SATA Source Select  
Forces "cold" start during PD  
RW Reset and Relatch Normal PD# mode  
SMBus Table: CPU, LCD SS and DOT96/SRC5 Control Register  
Byte 1  
Bit 7  
Name  
DOT96_SEL  
Control Function  
Selects DOT96 or SRC5  
Selects Center or Down Spread  
for CPU & SRC  
Type  
R
0
1
Default  
Latch  
SRC5  
DOT96  
CPU/SRC SS Select  
RW  
Down Spread  
Center Spread  
0
Bit 6  
CPU SS1  
CPU SS0  
LCD SS2  
LCD SS1  
LCD SS0  
CPU SS Magnitude MSB  
CPU SS Magnitude LSB  
LCD SS Magnitude MSB  
LCD SS Magnitude  
RW See Table 1: CPU/SRC PLL Frequency &  
0
0
1
1
0
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
RW  
RW  
RW  
RW  
Spread Selection Table  
See Table 2: LCDCLK Spread Spectrum  
Table  
LCD SS Magnitude LSB  
Selects Center or Down Spread  
for LCDCLK  
LCD SS Select  
RW  
Down Spread  
Center Spread  
0
Bit 0  
SMBus Table: Output Enable Control Register  
Byte 2  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Name  
REF OE  
48M OE (Pin17)  
USB48M OE (Pin16)  
25M OE  
Control Function  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
Disable  
Disable  
Disable  
Disable  
Disable  
Disable  
Disable  
Enable  
Enable  
Enable  
Enable  
Enable  
Enable  
Enable  
1
1
1
1
1
1
1
PCI3 OE  
PCI2 OE  
PCI_F1 OE  
Enables Control of CPU_ITP  
with CPU_STOP  
CPU_ITP STOP EN  
RW  
Free-Running  
Stoppable  
0
Bit 0  
SMBus Table: Output Enable Control Register  
Byte 3  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
SRC7 OE  
SRC6 OE  
Control Function  
Output Enable  
Output Enable  
SRC5 is controlled  
SRC7 is controlled  
Output Enable  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
Disable  
Disable  
Not Controlled  
Not Controlled  
Disable  
Enable  
Enable  
Controlled  
Controlled  
Enable  
Enable  
Enable  
Enable  
1
1
0
0
1
1
1
1
CLKREQC# Control  
CLKREQC# Control  
PCI4/27M OE  
LCDCLK OE  
SRC4 OE  
LCDPLL & Output Enable  
Output Enable  
Disable  
Disable  
Disable  
SATA OE  
Output Enable  
SMBus Table: Output Enable and SS Enable Control Register  
Byte 4  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
SRC3 OE  
SRC2 OE  
Control Function  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
SATA is controlled  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
Disable  
Disable  
Disable  
Disable  
1
Default  
Enable  
Enable  
Enable  
Enable  
Enable  
Enable  
SS ON  
Controlled  
1
1
1
1
1
1
1
0
CPU_ITP/SRC1 OE  
DOT96/SRC5 OE  
CPU1 OE  
CPU0 OE  
CPU/SRC PLL SS EN  
CLKREQC# Control  
Disable  
Disable  
SS OFF  
Not Controlled  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
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9VRS4339B  
REV A 010312  
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VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
SMBus Table: CLKREQ Control Register  
Byte 5  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
CLKREQA# EN  
Control Function  
CLKREQA# Enable  
SRC1 is controlled  
SRC2 is controlled  
SRC3 is controlled  
CLKREQB# Enable  
SRC4 is controlled  
SRC6 is controlled  
CLKREQC# Enable  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
Disable  
Enable  
0
0
0
0
0
0
0
0
CLKREQA# Control  
CLKREQA# Control  
CLKREQA# Control  
CLKREQB# EN  
CLKREQB# Control  
CLKREQB# Control  
CLKREQC# EN  
Not Controlled  
Not Controlled  
Not Controlled  
Disable  
Not Controlled  
Not Controlled  
Disable  
Controlled  
Controlled  
Controlled  
Enable  
Controlled  
Controlled  
Enable  
Note: To enable CLKREQC function, please write "0" to Byte 9 bit 7 and "1" to Byte 5 bit 0. To select which output to  
control, please make necessay selection in Bytes 3 & 4.  
Byte 6 Reserved Register  
SMBus Table: Revision and Vendor ID Register  
Byte 7  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
Control Function  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
0
0
0
1
0
0
0
1
Revision ID  
B rev = 0001  
VENDOR ID  
0001 = ICS/IDT  
SMBus Table: Output Control Register  
Byte 8  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
00 = 1.5V/ns  
10 = 2.6V/ns  
00 = 1.5V/ns  
10 = 2.6V/ns  
-
PCI Aligned  
00 = 700mV  
10 = 900mV  
01 = 2.0V/ns  
11 = 3.3V/ns  
01 = 2.0V/ns  
11 = 3.3V/ns  
-
PCI Delayed  
01 = 800mV  
11 = 1000mV  
0
0
0
0
0
0
0
1
48M (Pin17) SR  
Slew Rate Control  
27M / PCI4 SR  
Slew Rate Control  
Reserved  
PCI_SKEW_MODE  
LCD_AMP<1>  
LCD_AMP<0>  
Reserved  
PCICLK Skew Mode Control  
LCD Amplitude Control bit1  
LCD Amplitude Control bit0  
Note: A ssystem reset maybe required when switching between PCICLK aligned and skew mode  
SMBus Table: Byte Count Register  
Byte 9  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
48M_SEL  
Reserved  
Reserved  
BC4  
Control Function  
Selects 48M or CLKREQC  
Reserved  
Type  
RW  
RW  
RW  
RW  
0
1
48M  
-
-
Default  
CLKREQC  
1
0
0
0
1
1
1
1
-
-
Reserved  
BC3  
BC2  
BC1  
BC0  
RW Writing to this register will configure how  
RW many bytes will be read back, default is  
RW  
RW  
Byte Count Programming  
0F or 1F = 15 bytes.  
Note: To enable CLKREQC function, please write "0" to Byte 9 bit 7 and "1" to Byte 5 bit 0. To select which output to  
control, please make necessay selection in Bytes 3 & 4.  
SMBus Table: Output Control Register  
Byte 10  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
00 = 1.5V/ns  
10 = 2.6V/ns  
00 = 1.5V/ns  
10 = 2.6V/ns  
00 = 1.5V/ns  
10 = 2.6V/ns  
00 = 1.5V/ns  
10 = 2.6V/ns  
01 = 2.0V/ns  
11 = 3.3V/ns  
01 = 2.0V/ns  
11 = 3.3V/ns  
01 = 2.0V/ns  
11 = 3.3V/ns  
01 = 2.0V/ns  
11 = 3.3V/ns  
0
0
0
0
0
0
0
0
USB48M (Pin16) SR  
Slew Rate Control  
REF SR  
PCI3 SR  
25M SR  
Slew Rate Control  
Slew Rate Control  
Slew Rate Control  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
9
9VRS4339B  
REV A 010312  
9VRS4339B  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
SMBus Table: Output Control Register  
Byte 11  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
CPU  
SRC  
SATA  
DOT96  
Control Function  
Differential Slew Rate  
Differential Slew Rate  
Differential Slew Rate  
Differential Slew Rate  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
0=2.5V/ns  
0=2.5V/ns  
0=2.5V/ns  
0=2.5V/ns  
00 = 1.5V/ns  
10 = 2.6V/ns  
00 = 1.5V/ns  
10 = 2.6V/ns  
1=4V/ns  
1=4V/ns  
1=4V/ns  
1=4V/ns  
01 = 2.0V/ns  
11 = 3.3V/ns  
01 = 2.0V/ns  
11 = 3.3V/ns  
1
1
1
1
0
0
0
0
PCI2  
PCI1  
Slew Rate Control  
Slew Rate Control  
SMBus Table: M/N Enable & Output Stop Control Register  
Byte 12  
Name  
Control Function  
Enables M/N programming for  
CPU/SRC PLL  
Type  
0
1
Default  
CPU/SRC PLL M/N En  
RW  
Disable  
Enable  
0
Bit 7  
Enables Control of SRC1 with  
PCI_STOP  
Enables Control of SRC2 with  
PCI_STOP  
Enables Control of SRC3 with  
PCI_STOP  
Enables Control of SRC4 with  
PCI_STOP  
Enables Control of SRC5 with  
PCI_STOP  
Enables Control of SRC6 with  
PCI_STOP  
Enables Control of SRC7 with  
PCI_STOP  
SRC1 STOP EN  
SRC2 STOP EN  
SRC3 STOP EN  
SRC4 STOP EN  
SRC5 STOP EN  
SRC6 STOP EN  
SRC7 STOP EN  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Free-Running  
Free-Running  
Free-Running  
Free-Running  
Free-Running  
Free-Running  
Free-Running  
Stoppable  
Stoppable  
Stoppable  
Stoppable  
Stoppable  
Stoppable  
Stoppable  
0
0
0
0
0
0
0
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
SMBus Table: Output Control Register  
Byte 13  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Name  
ITP_EN  
SEL_PCI  
WOL Enable  
PCI_F1  
PCI2  
Control Function  
ITP_EN readback  
Select PCI Readback  
WOL Enable for 25M  
Type  
R
R
0
1
Default  
Latch  
Latch  
SRC1  
27M  
CPU_ITP  
PCI4  
RW  
WOL Disabled  
Free-Running  
Free-Running  
Free-Running  
Free-Running  
WOL Enabled  
Stoppable  
Stoppable  
Stoppable  
Stoppable  
1
0
1
1
1
Free Running with PCI_STOP# RW  
Free Running with PCI_STOP# RW  
Free Running with PCI_STOP# RW  
Free Running with PCI_STOP# RW  
PCI3  
PCI4  
Enables Control of SATA with  
SATA STOP EN  
RW  
Free-Running  
Stoppable  
0
Bit 0  
PCI_STOP  
* For lowest power saving during WOL mode, it is mandatory to connect 3.3V and 1.5V core VDD pins to standby power  
and suspend/remove VDDIO pins.  
SMBus Table: Differential Output Amplitude Control Register  
Byte 14  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Name  
Control Function  
PCIEX Amplitude Control bit1  
PCIEX Amplitude Control bit0  
DOT96 Amplitude Control bit1 RW  
DOT96 Amplitude Control bit0 RW  
SATA Amplitude Control bit1  
SATA Amplitude Control bit0  
Type  
RW  
RW  
0
1
Default  
PCIEX_AMP<1>  
PCIEX_AMP<0>  
DOT96_AMP<1>  
DOT96_AMP<0>  
SATA_AMP<1>  
SATA_AMP<0>  
00 = 700mV  
10 = 900mV  
00 = 700mV  
10 = 900mV  
00 = 700mV  
10 = 900mV  
01 = 800mV  
11 = 1000mV  
01 = 800mV  
11 = 1000mV  
01 = 800mV  
11 = 1000mV  
0
1
0
1
0
1
RW  
RW  
CPU_AMP<1>  
CPU_AMP<0>  
CPUCLK Amplitude Control bit1 RW  
CPUCLK Amplitude Control bit0 RW  
00 = 700mV  
10 = 900mV  
01 = 800mV  
11 = 1000mV  
0
1
Bit 1  
Bit 0  
Bytes 15+ Reserved Registers  
************************************************************************************************************************************************************************  
All reserved bits and reserved bytes in this SMBus table should not be overwritten at any instance. Writing to these reserved  
bits and bytes may cause unexpected behavior. IDT does not warrant any application issue going forward if continuing to  
overwrite these reserve bits and bytes.  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
10  
9VRS4339B  
REV A 010312  
9VRS4339B  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Absolute Maximum Ratings–DC Parameters  
Stresses above the ratings listed below can cause permanent damage to the 9VRS4339B. These ratings, which are  
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any  
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute  
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over  
the recommended operating temperature range.  
PARAMETER  
SYMBOL  
VDD27, VDD_3.3  
VDD_CORE_1.5  
VDD_LVIO  
CONDITIONS  
Supply Voltage  
Supply Voltage  
Supply Voltage  
MIN  
MAX  
4.6  
1.9  
UNITS  
Notes  
1,4  
1,4  
Maximum Supply Voltage  
Maximum Supply Voltage  
Maximum Supply Voltage  
V
V
V
1.9  
1,4  
Maximum Input Voltage  
Minimum Input Voltage  
Storage Temperature  
VIH  
VIL  
Ts  
3.3V Inputs, including SMBus  
4.6  
V
1,2,4  
1,4  
4
Any Input  
-
GND - 0.5  
-65  
V
°C  
°C  
V
150  
115  
Case Temperature  
Input ESD protection  
Tcase  
ESD prot  
-
1
3,4  
Human Body Model  
2000  
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).  
1 Intentionally blank  
2 Maximum VIH is not to exceed VDD  
3 Human Body Model  
4 Operation under these conditions is neither implied, nor guaranteed.  
Electrical Characteristics–PCICLK/PCICLK_F  
PARAMETER  
Long Accuracy  
SYMBOL  
ppm  
CONDITIONS  
see Tperiod min-max values  
33.33MHz output no spread  
33.33MHz output spread  
33.33MHz output no spread  
33.33MHz output nominal/spread  
IOH = -1 mA  
MIN  
-100  
MAX  
100  
30.00300  
30.23459  
30.50300  
30.58421  
UNITS NOTES  
ppm  
ns  
ns  
ns  
ns  
V
1,2  
1,2,5  
1,2,5  
1,2  
1,2  
1
29.99700  
30.08421  
29.49700  
29.56617  
2.4  
Clock period  
Tperi od  
Tabs  
Absolute min/max period  
VOH  
VOL  
Output High Voltage  
Output Low Voltage  
IOL = 1 mA  
0.4  
V
mA  
mA  
mA  
mA  
V/ns  
V/ns  
%
1
1
V OH @MIN = 1.0 V  
VOH@MAX = 3.135 V  
-33  
30  
IOH  
Output High Current  
Output Low Current  
-33  
1
V
OL @ MIN = 1.95 V  
1
IOL  
VOL @ MAX = 0.4 V  
38  
4
1
tSLR  
tFL R  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Duty Cycle  
Measured from 0.8 to 2.0 V  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
1
1
1,3  
1,3  
1,4  
1,4,7  
4
dt1  
45  
55  
250  
Adjacent Pin to Pin Skew  
tsk ew  
VT = 1.5 V, PCI Aligned Mode (Default)  
VT = 1.5 V, PCI Delayed Mode  
VT = 1.5 V , PCI Delayed Mode  
VT = 1.5 V  
ps  
ts kew_delay  
tskew_total  
200ps typical  
800  
500  
Adjacent Pin to Pin Intentional Delay  
Total PCI Skew Window  
ps  
ps  
ps  
1,4,8  
1,4,9  
1,4  
t
Jitter, Cycle to cycle  
jcyc-cyc  
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, Rs=39ohm, CL=5pF  
1 Unless otherwise noted, guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.000000MHz  
3Edge rate in system is measured from 0.8V to 2.0V.  
4 Duty cycle, Peroid, Skew and Jitter are measured with respect to 1.5V  
5 The average period over any 1us period of time  
6 Using frequency counter with the measurment interval equal or greater that 0.15s. Target frequencies are 14.318181 MHz, 25.000000MHz, 33.333333MHz,  
27.000000MHz and 48.000000MHz  
7 Adjacent pin to pin skew is the pin to pin skew between PCI1 and PCI2, PCI2 and PCI3, or PCI3 to PCI4.  
8 Adjacent pin to pin intentional delay is the intentional delay between PCI1 and PCI2, PCI2 and PCI3, or PCI3 to PCI4.  
9 Total PCI skew winodw is absolute skew between PCI1 and PCI4.  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
11  
9VRS4339B  
REV A 010312  
9VRS4339B  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
PCICLK Relationship Timing Diagram During Delayed Mode  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
12  
9VRS4339B  
REV A 010312  
9VRS4339B  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Electrical Characteristics–Input/Supply/Common Output DC Parameters  
PARAMETER  
Ambient Operating Temp  
SYMBOL  
Tambient  
VDD27, VDD_3.3  
VDD_CORE_1.5  
VDD_LVIO  
CONDITIONS  
-
Supply Voltage  
Supply Voltage  
Supply Voltage  
MIN  
0
3.135  
1.425  
0.9975  
MAX  
70  
3.465  
1.575  
1.575  
UNITS  
°C  
V
V
V
Notes  
Supply Voltage  
Input High Voltage  
Input Low Voltage  
VIHSE  
VILSE  
VIH_LI  
VIL_LI  
Single-ended 3.3V inputs  
Single-ended 3.3V inputs  
2
VDD + 0.3  
0.8  
V
V
V
V
3
3
VSS - 0.3  
2
Latched Input High Voltage  
Latched Input Low Voltage  
Single-ended 3.3V Latched Inputs  
Single-ended 3.3V Latched Inputs  
VDD + 0.3  
0.8  
VSS - 0.3  
Low Threshold Latched Input-  
High Voltage  
Low Threshold Latched Input-  
Low Voltage  
VIH_FS  
Low threshold inputs FSL[C:B]  
Low threshold inputs FSL[C:B]  
0.7  
VDD+0.3  
V
VIL_FS  
IIN  
VSS - 0.3  
-5  
0.35  
5
V
Input Leakage Current  
VIN = VDD , VIN =GND  
uA  
uA  
2
Inputs with pull up or pull down resistors  
Input Leakage Current  
IINRES  
-200  
200  
VIN = VDD , VIN =GND  
Output High Voltage  
Output Low Voltage  
VOHSE  
VOLSE  
Single-ended outputs, IOH = -1mA  
Single-ended outputs, IOL = 1 mA  
Full Active, CL = Full load; IDD 3.3V  
Full Active, CL = Full load; IDD 1.5V  
Full Active, CL = Full load; IDD LVIO  
Power down mode, 3.3V Rail  
Power down mode, 1.5V Rail  
Power down mode, 1.05V Rail  
Wake On LAN mode, 3.3V Rail  
Wake On LAN mode, 1.5V Rail  
Wake On LAN mode, LVIO Rail  
VDD = 3.3 V  
2.4  
V
V
1
1
0.4  
38  
40  
46  
1.2  
1
IDDOP3.3  
IDDOP1.5  
IDDOP1.05  
IDDPD3.3  
IDDPD1.5  
IDDPDLVIO  
IDDWOL3.3  
IDDWOL1.5  
IDDWOLLVIO  
Fi  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
MHz  
nH  
pF  
Operating Supply Current  
Powerdown Current  
5
5
5
6
6
6
4
0
10  
1
Wake-On-Lan Current  
0
25MHz Typical  
Input Frequency  
Pin Inductance  
Lpin  
7
5
6
6
CIN  
Logic Inputs  
1.5  
Input Capacitance  
COUT  
Output pin capacitance  
pF  
CINX  
X1 & X2 pins  
From VDD Power-Up or de-assertion of PD  
to 1st clock  
pF  
Clk Stabilization  
TSTAB  
1.8  
ms  
Tstop_CR_off  
Trun_CR_on  
TCROFF  
TCRON  
TSTOP  
Output stop after CLKREQ# deasserted  
2
2
3
3
Clocks  
Clocks  
Output run after CLKREQ# asserted  
CPU or PCI stop after  
CPU or PCI STOP# assertion  
CPU or PCI run after  
Tstop  
Trun  
2
2
3
3
Clocks  
Clocks  
TRUN  
CPU or PCI STOP# de-assertion  
Tfall_SE  
Trise_SE  
TFALL  
TRISE  
VDD  
10  
10  
ns  
ns  
V
Fall/rise time of all 3.3V control inputs from 20-  
80%  
SMBus Voltage  
2.7  
4
3.3  
0.4  
Low-level Output Voltage  
Current sinking at  
VOLSMB  
@ IPULLUP  
V
IPULLUP  
SMB Data Pin  
mA  
V
OLSMB = 0.4 V  
SCLK/SDATA  
Clock/Data Rise Time  
SCLK/SDATA  
(Max VIL - 0.15) to  
(Min VIH + 0.15)  
(Min VIH + 0.15) to  
(Max VIL - 0.15)  
TRI2C  
TFI2C  
1000  
300  
ns  
ns  
Clock/Data Fall Time  
Maximum SMBus Operating Frequency  
FSMBUS  
fSSMOD  
100  
33  
kHz  
kHz  
Spread Spectrum Modulation Frequency  
Triangular Modulation  
30  
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).  
1Signal is required to be monotonic in this region.  
2 input leakage current does not include inputs with pull-up or pull-down resistors  
3 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, ITP_EN, SCLK, SDATA, CLKPWRGD/PD#, DOT96_SEL, SEL_PCI, 48M_SEL and PEREQ# inputs if  
selected.  
4 For margining purposes only. Normal operation should have Fin = 25MHz +/-50ppm  
5 Standard powerdown with Wake on LAN disabled.  
6 Powerdown with Wake on LAN enabled  
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AC Electrical Characteristics–CPU, SRC, SATA, DOT96MHz  
PARAMETER  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Slew Rate Variation  
SYMBOL  
tSLR  
CONDITIONS  
MIN  
2.5  
MAX  
4
4
20  
1150  
UNITS NOTES  
Differential Measurement  
Differential Measurement  
Single-ended Measurement  
Includes overshoot  
V/ns  
V/ns  
%
mV  
mV  
mV  
mV  
mV  
%
1,3  
1,3  
1,3  
1
1
1
1,3,4  
1,3,5  
1
tFLR  
tSLVAR  
VHIGH  
VLOW  
VSWING  
VXABS  
VXABSVAR  
DCYC  
2.5  
Maximum Output Voltage  
Minimum Output Voltage  
Differential Voltage Swing  
Crossing Point Voltage  
Crossing Point Variation  
Duty Cycle  
Includes undershoot  
-300  
300  
300  
Differential Measurement  
Single-ended Measurement  
Single-ended Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
550  
140  
55  
85  
85  
125  
250  
100  
150  
250  
500  
45  
CPU Jitter - Cycle to Cycle  
SRC Jitter - Cycle to Cycle  
SATA Jitter - Cycle to Cycle  
DOT Jitter - Cycle to Cycle  
CPU[1:0] Skew  
CPUJC2C  
SRCJC2C  
SATAJC2C  
DOTJC2C  
CPU10SKEW  
CPU20SKEW  
PCIEXSKEW  
PCIEXSKEW  
ps  
1
ps  
1
ps  
1
ps  
1
ps  
ps  
ps  
1,6  
1,6  
1
CPU[ITP:0] Skew  
PCIEX(6, 4:2) Skew  
PCIEX(7:1) Skew  
ps  
1
Notes: TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL=2pF, Rs=0Ω (unless specified otherwise)  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.000000MHz  
3 Slew rate emastured throu gh V_swing voltage range centered about differential zero  
4 Vcross is defined at the voltage where Clock = Clock#.  
5 Only applies to the differential rising edge (Clock rising, Clock# falling.)  
6 CPU group skew is nominally 0ps.  
Electrical Characteristics–USB48MHz/48MHz  
PARAMETER  
Long Accuracy  
SYMBOL  
ppm  
CONDITIONS  
MIN  
-100  
MAX  
100  
UNITS NOTES  
see Tperiod min-max values  
ppm  
ns  
ns  
V
1,2  
1,2,5  
1,2  
1
Tperiod  
Clock period  
48.00MHz output nominal  
48.00MHz output nominal  
IOH = -1 mA  
20.83125  
20.48125  
2.4  
20.83542  
21.18542  
Tabs  
VOH  
VOL  
Absolute min/max period  
Output High Voltage  
Output Low Voltage  
IOL = 1 mA  
0.4  
V
1
V
OH @MIN = 1.0 V  
-29  
29  
mA  
1
IOH  
IOL  
Output High Current  
Output Low Current  
V
OH@MAX = 3.135 V  
-23  
mA  
mA  
1
VOL @ MIN = 1.95 V  
1
V
OL @ MAX = 0.4 V  
27  
2
mA  
1
Rising Edge Slew Rate (USB48M)  
Falling Edge Slew Rate (USB48M)  
Rising Edge Slew Rate (48M)  
Falling Edge Slew Rate (48M)  
Duty Cycle  
tSLR  
tFL R  
tSLR  
tFL R  
dt1  
Measured from 0.8 to 2.0 V  
1
1
V/ns  
V/ns  
V/ns  
V/ns  
%
1,3  
1,3  
1,3  
1,3  
1,4  
1,4  
Measured from 2.0 to 0.8 V  
Measured from 0.8 to 2.0 V  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
2
1
4
1
4
45  
55  
350  
t
VT = 1.5 V  
ps  
Jitter, Cycle to cycle  
jcyc-cyc  
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, Rs=39ohm, CL=5pF  
1 Unless otherwise noted, guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.000000MHz  
3Edge rate in system is measured from 0.8V to 2.0V.  
4 Duty cycle, Peroid and Jitter are measured with respect to 1.5V  
5 The average period over any 1us period of time  
6 Using frequency counter with the measurment interval equal or greater that 0.15s. Target frequencies are 14.318181 MHz, 25.000000MHz, 33.333333MHz,  
27.000000MHz and 48.000000MHz  
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Electrical Characteristics–25MHz  
PARAMETER  
Long Accuracy  
SYMBOL  
ppm  
CONDITIONS  
see Tperiod min-max values  
MIN  
-30  
MAX  
30  
UNITS NOTES  
ppm  
1,2  
Tperiod  
Clock period  
25.00MHz output nominal  
IOH = -1 mA  
39.99880  
2.4  
40.00120  
ns  
1,2,5  
Output High Voltage  
VOH  
VOL  
V
1
1
1
1
IOL = 1 mA  
Output Low Voltage  
0.4  
V
V
OH @MIN = 1.0 V  
-29  
29  
mA  
Output High Current  
IOH  
IOL  
V
OH@MAX = 3.135 V  
-23  
mA  
VOL @ MIN = 1.95 V  
VOL @ MAX = 0.4 V  
Measured from 0.8 to 2.0 V  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
mA  
1
Output Low Current  
27  
2
mA  
1
tSLR  
tFL R  
dt1  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Duty Cycle  
0.5  
0.5  
45  
V/ns  
V/ns  
1,3  
1,3  
1,4  
1,4  
2
55  
200  
%
t
VT = 1.5 V  
ps  
Jitter, Cycle to cycle  
jcyc-cyc  
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, Rs=39ohm, CL=5pF  
1 Unless otherwise noted, guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.000000MHz  
3Edge rate in system is measured from 0.8V to 2.0V.  
4 Duty cycle, Peroid and Jitter are measured with respect to 1.5V  
5 The average period over any 1us period of time  
6 Using frequency counter with the measurment interval equal or greater that 0.15s. Target frequencies are 14.318181 MHz, 25.000000MHz, 33.333333MHz,  
27.000000MHz and 48.000000MHz  
Electrical Characteristics–REF-14.318MHz  
PARAMETER  
Long Accuracy  
SYMBOL  
ppm  
CONDITIONS  
see Tperiod min-max values  
14.318MHz output nominal  
14.318MHz output nominal  
IOH = -1 mA  
MIN  
-100  
69.82033  
69.83400  
2.4  
MAX  
100  
69.86224  
70.84800  
UNITS  
ppm  
ns  
ns  
V
Notes  
1,2  
1,2,5  
1,2  
Clock period  
Absolute min/max period  
Output High Voltage  
Tperiod  
Tabs  
VOH  
1
VOL  
Output Low Voltage  
IOL = 1 mA  
0.4  
V
mA  
mA  
mA  
mA  
V/ns  
V/ns  
%
1
1
V OH @MIN = 1.0 V  
-29  
29  
IOH  
Output High Current  
V
OH@MAX = 3.135 V  
-23  
1
V
OL @ MIN = 1.95 V  
OL @ MAX = 0.4 V  
1
IOL  
Output Low Current  
V
27  
4
1
tSLR  
tFL R  
dt1  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Duty Cycle  
Measured from 0.8 to 2.0 V  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
1
1
1,3  
1,3  
1,4  
1,4  
4
45  
55  
t
Jitter, Cycle to cycle  
VT = 1.5 V  
1000  
ps  
jcyc-cyc  
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, Rs=39ohm, CL=5pF  
1 Unless otherwise noted, guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.000000MHz  
3Edge rate in system is measured from 0.8V to 2.0V.  
4 Duty cycle, Peroid and Jitter are measured with respect to 1.5V  
5 The average period over any 1us period of time  
6 Using frequency counter with the measurment interval equal or greater that 0.15s. Target frequencies are 14.318181 MHz, 25.000000MHz, 33.333333MHz,  
27.000000MHz and 48.000000MHz  
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Electrical Characteristics–27MHz  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
-50  
-15  
MAX  
50  
15  
UNITS  
ppm  
ppm  
ns  
Notes  
1,2  
1,2,7  
1,4,5  
Long Accuracy  
ppm  
see Tperiod min-max values  
Clock period  
Tperiod  
VOH  
27.000MHz output nominal  
IOH = -1 mA  
37.0365  
37.0376  
Output High Voltage  
Output Low Voltage  
2.4  
-29  
29  
V
V
1
1
VOL  
IOL = 1 mA  
0.4  
V OH @MIN = 1.0 V  
mA  
mA  
mA  
mA  
V/ns  
V/ns  
%
1
Output High Current  
Output Low Current  
IOH  
IOL  
V
OH@MAX = 3.135 V  
-23  
1
V
OL @ MIN = 1.95 V  
1
VOL @ MAX = 0.4 V  
Measured from 0.8 to 2.0 V  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
27  
4
1
tSLR  
tFL R  
dt1  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Duty Cycle  
1
1
1,3  
1,3  
1,4  
1,4  
1,4  
4
45  
55  
400  
200  
t
Long Term (10us), , VT = 1.5 V  
Cycle to Cycle, VT = 1.5 V  
ps  
ltj  
Jitter  
t
ps  
jcyc-cyc  
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, Rs = 39ohm, CL = 5pF  
1 Unless otherwise noted, guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.000000MHz  
3Edge rate in system is measured from 0.8V to 2.0V.  
4 Duty cycle, Peroid and Jitter are measured with respect to 1.5V  
5 The average period over any 1us period of time  
6 Using frequency counter with the measurment interval equal or greater that 0.15s. Target frequencies are 14.318181 MHz, 25.000000MHz, 33.333333MHz,  
27.000000MHz and 48.000000MHz  
7 At nominal voltage and temperature.  
Clock Jitter Specifications - Low Power Differential Outputs  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
MAX  
UNITS NOTES  
ps (p-p) 1,2  
tjp ha sePLL  
PCIe Gen 1  
PCIe Gen 2  
10kHz < f < 1.5MHz  
PCIe Gen 2  
86  
tjp ha seLo  
3.0  
3.1  
ps (RMS) 1,3,4  
ps (RMS) 1,3,4  
PCIEX Phase Jitter  
t
jp ha seH igh  
1.5MHz < f < Nyquist (50MHz)  
*TA = 0 - 70°C; Supply Voltage VDD = 1.5V +/- 5%, Rs=0ohm, CL=2pF  
1 Unless otherwise noted, guaranteed by design and characterization, not 100% tested in production.  
2JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system  
3
Phase jitter requirement: The designated Gen2 outputs will meet the reference clock jitter requiremernts from the PCI Express Gen2 Base Spec. The test is performed  
4See http://www.pcisig.com for complete specs  
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Differential Clock Tolerances  
CPU  
SRC  
DOT96  
SATA  
PPM tolerance  
Cycle to Cycle Jitter  
Spread  
ppm  
ps  
%
100  
85  
-0.50%  
100  
85  
-0.50%  
100  
250  
0.00%  
100  
125  
-0.50%  
Clock Periods–Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC OFF  
Units Notes  
-c2c jitter  
AbsPer  
Min  
+c2c jitter  
AbsPer  
Max  
Short-Term Long-Term 0 ppm Period Long-Term  
Average  
Min  
Average  
Min  
Nominal  
Average  
Max  
100.00  
133.33  
166.67  
200.00  
100.00  
100.00  
96.00  
9.91400  
7.41425  
5.91440  
4.91450  
9.87400  
9.87400  
10.16563  
9.99900  
7.49925  
5.99940  
4.99950  
9.99900  
9.99900  
10.41563  
10.00000  
7.50000  
6.00000  
5.00000  
10.00000  
10.00000  
10.41667  
10.00100  
7.50075  
6.00060  
5.00050  
10.00100  
10.00100  
10.41771  
10.08600  
7.58575  
6.08560  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
CPU  
5.08550  
SRC  
SATA  
DOT96  
10.12600  
10.12600  
10.66771  
Clock Periods–Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC ON  
Units Notes  
-c2c jitter  
AbsPer  
Min  
+c2c jitter  
AbsPer  
Max  
Short-Term Long-Term 0 ppm Period Long-Term  
Average  
Min  
Average  
Min  
Nominal  
Average  
Max  
99.75  
133.00  
166.25  
199.50  
99.75  
9.91406  
7.41430  
5.91444  
4.91453  
9.87406  
9.87406  
9.99906  
7.49930  
5.99944  
4.99953  
9.99906  
9.99906  
10.02406  
7.51805  
6.01444  
5.01203  
10.02406  
10.02406  
10.02506  
7.51880  
6.01504  
5.01253  
10.02506  
10.02506  
10.02607  
7.51955  
6.01564  
5.01303  
10.02607  
10.02607  
10.05107  
7.53830  
6.03064  
5.02553  
10.05107  
10.05107  
10.13607  
7.62330  
6.11564  
5.11053  
10.17607  
10.17607  
ns  
ns  
ns  
ns  
ns  
ns  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
CPU  
SRC  
SATA  
99.75  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 25.000000MHz.  
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Power-up Sequencing Requirements  
Marking Diagram  
ICS  
9VRS4339BL  
YYWW  
ORIGIN  
######  
Notes:  
1. ###### is the lot number.  
2. YYWW is the last two digits of the year and week that the part was assembled.  
3. “L” denotes RoHS compliant package.  
4. “ORIGIN” is the country of origin.  
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Package Outline and Package Dimensions (56-pin MLF)  
Millimeters  
Symbol  
Min  
0.8  
0
Max  
1.0  
A
A1  
0.05  
A3  
b
0.2 Reference  
0.15 0.25  
e
0.40 BASIC  
7.00 x 7.00  
D x E BASIC  
D2 MIN./MAX.  
E2 MIN./MAX.  
L MIN./MAX.  
N
5.60  
5.60  
0.30  
5.80  
5.80  
0.50  
56  
14  
14  
N
N
D
E
Ordering Information  
Part / Order Number  
Marking  
see page 18  
Shipping Packaging  
Trays  
Package  
56-pin MLF  
56-pin MLF  
Temperature  
0 to +70C  
0 to +70C  
9VRS4339BKLF  
9VRS4339BKLFT  
Tape and Reel  
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
“B” is the device revision designator (will not correlate with the datasheet revision).  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
19  
9VRS4339B  
REV A 010312  
9VRS4339B  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
Revision History  
Rev.  
Initiator  
Issue Date Description  
Page #  
0.1  
DC  
4/25/2011 Initial Release  
-
1. Updated "Features/Benefits" section  
2. Updated Power Distribution table  
3. Updated Byte 13  
4. Updated pin 55 description  
1. Updated "General Description"  
2. Updated "Features/Benefits"  
3. Updated pin descriptions  
0.2  
A
DC  
DC  
10/11/2011  
1/3/2012  
Various  
Various  
4. Updated Byte13  
5. Updated "Absolute Max Ratings" and "Electrical Characteristics -  
Input/Supply/Common Output DC Parameters" tables  
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
20  
9VRS4339B  
REV A 010312  
9VRS4339B  
VERY LOW POWER CLOCK FOR 2011 NETBOOKS  
SYNTHESIZERS  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
800-345-7015  
408-284-8200  
Fax: 408-284-2775  
For Tech Support  
www.idt.com/go/support  
Corporate Headquarters  
Integrated Device Technology, Inc.  
www.idt.com  
© 2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated  
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or  
registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
厂商 型号 描述 页数 下载

IDT

 		9VRS4338D [ VERY LOW POWER CLOCK FOR 2011 NETBOOKS ] 23 页

IDT

 		9VRS4338DKLF [ VERY LOW POWER CLOCK FOR 2011 NETBOOKS ] 23 页

IDT

 		9VRS4338DKLFT [ IC CLOCK TIMING 200MHZ 48VFQFPN ] 5 页

IDT

 		9VRS4339B [ VERY LOW POWER CLOCK FOR 2011 NETBOOKS ] 21 页

IDT

 		9VRS4339BKLF [ VERY LOW POWER CLOCK FOR 2011 NETBOOKS ] 21 页

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