8T73S208B-01 Datasheet
Function Tables
variable bits which are set by the hardware pins ADR[1:0] (binary
11010, ADR1, ADR0). Bit 0 of slave address is used by the bus
controller to select either the read or write mode. The hardware pins
ADR1 and ADR0 and should be individually set by the user to avoid
address conflicts of multiple 8T73S208B-01 devices on the same
bus.
Input Frequency Divider Operation
The FSEL1 and FSEL0 control pins configure the input frequency
divider. In the default state (FSEL[1:0] are set to logic 0:0 or left open)
the output frequency is equal to the input frequency (divide-by-1).
The other FSEL[1:0] settings configure the input divider to
divide-by-2, 4 or 8, respectively.
2
Table 3D. I C Slave Address
Table 3A. FSEL[1:0] Input Selection Function Table
Input
7
1
6
1
5
0
4
1
3
0
2
1
0
ADR1 ADR0 R/W
FSEL1
FSEL0
Operation
fQ[7:0] = fREF ÷ 1
0 (default)
0 (default)
0
1
1
1
0
1
fQ[7:0] = fREF ÷ 2
fQ[7:0] = fREF ÷ 4
SCL
fQ[7:0] = fREF ÷ 8
SDA
NOTE: FSEL1, FSEL0 are asynchronous controls
Output Enable Operation
START
Valid Data
Acknowledge
STOP
The output enable/disable state of each individual differential output
Qx, nQx can be set by the content of the I2C register (see Table 3C).
A logic zero to an I2C bit in register 0 enables the corresponding
differential output, while a logic one disables the differential output
(see Table 3B). After each power cycle, the device resets all I2C bits
(Dn) to its default state (logic 1) and all Qx, nQx outputs are disabled.
After the first valid I2C write, the output enable state is controlled by
the I2C register. Setting and changing the output enable state through
the I2C interface is asynchronous to the input reference clock.
Figure 1: Standard I2C Transaction
START (S) – defined as high-to-low transition on SDA while holding
SCL HIGH.
DATA – between START and STOP cycles, SDA is synchronous with
SCL. Data may change only when SCL is LOW and must be stable
when SCL is HIGH.
ACKNOWLEDGE (A) – SDA is driven LOW before the SCL rising
edge and held LOW until the SCL falling edge.
Table 3B. Individual Output Enable Control
Bit
STOP (S) – defined as low-to-high transition on SDA while holding
SCL HIGH
Dn
Operation
Output Qx, nQx is enabled.
0
Output Qx, nQx is disabled in high-impedance
state.
S
DevAdd W A Data Byte
A P
1 (default)
Figure 2: Write Transaction
Table 3C. Individual output enable control
Bit
D7
Q7
1
D6
Q6
1
D5
Q5
1
D4
Q4
1
D3
Q3
1
D2
Q2
1
D1
Q1
1
D0
Q0
1
S
DevAdd R A
Data Byte
A P
Output
Default
Figure 3: Read Transaction
S –
Start or Repeated Start
2
I C Interface Protocol
W –
R/W is set for Write
R/W is set for Read
Ack
The 8T73S208B-01 uses an I2C slave interface for writing and
reading the device configuration to and from the on-chip
configuration registers. This device uses the standard I2C write
R –
A –
format for a write transaction, and a standard I2C read format for a
read transaction. Figure 1 defines the I2C elements of the standard
I2C transaction. These elements consist of a start bit, data bytes, an
acknowledge or Not-Acknowledge bit and the stop bit. These
elements are arranged to make up the complete I2C transactions as
shown in Figure 2 and Figure 3. Figure 2 is a write transaction while
Figure 3 is read transaction. The 7-bit I2C slave address of the
8T73S208B-01 is a combination of a 5-bit fixed addresses and two
DevAdd –
P –
7 bit Device Address
Stop
©2016 Integrated Device Technology, Inc.
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April 28, 2016
