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8T73S1802

型号：

8T73S1802

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

24 页

PDF大小：

441 K

下载PDF手册

1:2 Clock Fanout Buffer and

Frequency Divider

8T73S1802

Datasheet

Description

Features

The 8T73S1802 is a fully integrated clock fanout buffer and

frequency divider. The input signal is frequency-divided and then

fanned out to one differential LVPECL and one LVCMOS output.

Each of the outputs can select its individual divider value from the

range of ÷1, ÷2, ÷4 and ÷8. Three control inputs EN, SEL0 and

SEL1 (3-level logic) are available to select the frequency dividers

and the output enable/disable state. The single-ended LVCMOS

output is phase-delayed by 650ps to minimize coupling of

LVCMOS switching into the differential output during its signal

transition.

• High-performance fanout buffer clock and fanout buffer

• Input clock signal is distributed to one LVPECL and one

LVCMOS output

• Configurable output dividers for both LVPECL and LVCMOS

outputs

• Supports clock frequencies up to 1000MHz (LVPECL) and up to

200MHz (LVCMOS)

• Flexible differential input supports LVPECL, LVDS and CML

• V_BBgenerator output supports single-ended input signal

applications

The 8T73S1802 is optimized to deliver very low phase noise

clocks. The V_BBoutput generates a common-mode voltage

reference for the differential clock input so that connecting the V_BB

pin to an unused input (nCLK) enables to use of single-ended input

signals. The extended temperature range supports wireless

infrastructure, telecommunication and networking end equipment

requirements. The 8T73S1802 can be used with a 3.3V or a 2.5V

power supply. The device is a member of the high-performance

clock family from IDT.

• Optimized for low phase noise

• 650ps delay between LVCMOS and LVPECL minimizes coupling

between outputs

• Supply voltage: 3.3V or 2.5V

• -40°C to 85°C ambient operating temperature

• 16 VFQFPN package (3 x 3 mm)

Block Diagram

Pin Assignment

÷1

CLK

nCLK

÷2

÷4

÷8

nQA

V_{CCO_QB}

SEL0

GND

SEL1

8T73S1802

Bias Generator

V_CC-1.3V

V_BB

GND

8XXXXXX

Pullup

SEL0

SEL1

Control

16-pin, 3mm x 3mm VFQFPN Package

January 21, 2018

8T73S1802 Datasheet

Pin Description and Pin Characteristic Tables

Table 1. Pin Assignment

Pin Number

Name

Type¹

Description

V_CC

Power

Input

Power supply voltage for the device core and the inputs.

Non-inverting differential clock input. Compatible with LVPECL,

LVDS and CML signals.

CLK

nCLK

V_BB

Inverting differential clock input. Compatible with LVPECL, LVDS

and CML signals.

Input

Output

Power

Bias voltage generator output. Use to bias the nCLK input in

single-ended input applications. V_BB= V_CC- 1.3V.

Ground supply voltage (GND) and ground return path. Connect to

board GND (0V).

GND

Ground supply voltage (GND) and ground return path. Connect to

board GND (0V).

GND

Power

Output

LVCMOS clock output QB. LVCMOS/LVTTL interface levels.

If this pin is disabled by connecting its power supply pin V_{CCO_QB}to

GND, QB must be left open or connected to GND.

Positive supply voltage for the QB output. The QB output (if not

connected) can be disabled by connecting this pin to GND.

V_{CCO_QB}

Power

Positive supply voltage for the QA, nQA output. The QA, nQA output

(if not connected) can be disabled by connecting this pin to GND.

V_{CCO_QA}

Differential clock output QA. LVPECL interface levels.

Output

If this pin is disabled by connecting its power supply pins V_{CCO_QA}to

GND, QA and nQA must be left open or connected to GND.

Differential clock output QA. LVPECL interface levels.

If this pin is disabled by connecting its power supply pins V_{CCO_QA}to

GND, QA and nQA must be left open or connected to GND.

nQA

Positive supply voltage for the QA, nQA output. The QA, nQA output

(if not connected) can be disabled by connecting this pin to GND.

V_{CCO_QA}

SEL0

GND

Power

Input

Configuration pins. 3-Level interface. See Table 3 for function and

Table 4D for interface levels.

60k Pullup

Ground supply voltage (GND) and ground return path. Connect to

board GND (0V).

Power

Input

Configuration pins. 3-Level interface. See Table 3 for function and

Table 4D for interface levels.

SEL1

60k Pullup

Configuration pin. 3-Level interface. See Table 3 for function and

Table 4D for interface levels.

Input

NOTE 1. Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C_IN

Input Capacitance

Power

Dissipation Capacitance

C_PD

5.4

R_PULLUP

Input Pullup Resistor

k



V_{CCO_QB}= 2.375V

V_{CCO_QB}= 3.465V

LVCMOS 

Output Resistance

R_OUT



January 21, 2018

8T73S1802 Datasheet

Principles Of Operation

input open. For the mid state, connect an external 60k resistor

from the input to GND. See Table 4D for the 3-state input min and

max levels.

Control Pins

The control input pins SEL0, SEL1 and EN are 3-level inputs with

internal 60k resistors that pull the input to the V_CClevel when left

open. Each input has three logic states: low (0), mid (V_CC/2) and

high (1). Connect a control input to GND for achieving the low (0)

state. For the high (1) state, connect the input to V_CCor leave the

Operation Modes

The device offers a many combinations of divider values and

output enable states. See Table 3 for the supported modes.

Table 3. Operation Modes

Input^{2 3 4}

Output Divider

SEL1

SEL0

QA (LVPECL)

QB (LVCMOS)

Disabled

÷4

Disabled

÷4

MID

÷1

÷2

MID

÷8

÷1

MID

÷1

÷2

÷4

÷8

÷1

÷4

÷2

÷4

÷8

÷4

Disable

÷4

NOTE 1. In the default state (control input left open), QA is disabled and QB = ÷4.

NOTE 2. 0 = Low, MID = V_CC/2, 1 = High; X = either 0, MID or 1.

NOTE 3. 0 = Low, MID = V_CC/2, 1 = High; X = either 0, MID or 1.

NOTE 4. Unspecified EN, SEL1, SEL0 input logic states are reserved and should not be used.

January 21, 2018

8T73S1802 Datasheet

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC

Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

product reliability.

Item

Rating

Supply Voltage, V_CC

Inputs, V_I

3.6V

-0.5V to V_CC+ 0.5V

Outputs, V_O(LVCMOS)

-0.5V to V

+ 0.5V

CCO_QB

Outputs, I_O(LVPECL)

Continuous Current

Surge Current



10mA

15mA

Maximum Junction Temperature, T_{J_MAX}

Storage Temperature, T_STG

ESD - Human Body Model¹

125°C

-65°C to 150°C

2000V

ESD - Charged Device Model

1500V

NOTE 1. According to JEDEC/JESD 22-A114/22-C101.

Electrical Characteristics

Table 4A. 3.3V Power Supply Characteristics, V = V

= V

= 3.0V to 3.465V, T = -40°C to 85°C

CCO_QB A

CCO_QA

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_CC

Power Supply Voltage

3.0

3.3

3.465

V_{CCO_QA,}

V_{CCO_QB}

Output Supply Voltage

Power Supply Current¹

3.3

3.465

All outputs enabled and terminated with

50 to V_CC– 2V on LVPECL outputs and

10pF on LVCMOS output;

f = 800MHz for LVPECL outputs and

200MHz for LVCMOS, V_CC= 3.3V

120

I_CC

Outputs enabled, no load;

f = 800MHz for LVPECL outputs and

200MHz for LVCMOS, V_CC= 3.465V

104

8.2

Outputs Disabled, EN = 0,

f_IN= 0Hz, V_CC= 3.465V

I_CCZ

Power Supply Current¹

Power Supply Current

All outputs enabled and terminated with

50 to V_CC– 2V on LVPECL outputs and

10pF on LVCMOS output;

I_EE

109

f = 800MHz for LVPECL outputs and

200MHz for LVCMOS

NOTE 1. I_CCincludes output current.

January 21, 2018

8T73S1802 Datasheet

Table 4B. 2.5V Power Supply Characteristics, V = V

= V

= 2.5V ± 5%, T = -40°C to 85°C

CCO_QA

CCO_QB

Symbol

Parameter

Test Conditions

Minimum

Typical

2.5

Maximum

Units

V_CC

Power Supply Voltage

2.375

2.625

V_{CCO_QA,}

V_{CCO_QB}

Output Supply Voltage

Power Supply Current¹

2.5

2.625

All outputs enabled and terminated with

50 to V_CC– 2V on LVPECL outputs and

10pF on LVCMOS output;

f = 800MHz for LVPECL outputs and

200MHz for LVCMOS, V_CC= 2.5V

114

I_CC

Outputs enabled, no load;

f = 800MHz for LVPECL outputs and

200MHz for LVCMOS, V_CC= 2.625V

Outputs Disabled, EN = 0,

f_IN= 0Hz, V_CC= 2.625V

I_CCZ

Power Supply Current¹

Power Supply Current

1.5

All outputs enabled and terminated with

50 to V_CC– 2V on LVPECL outputs and

10pF on LVCMOS output;

I_EE

f = 800MHz for LVPECL outputs and

200MHz for LVCMOS

NOTE 1. I_CCincludes output current.

Table 4C. Differential Characteristics, V = V

= 3.0V to 3.465V or 2.5V±5%, T = -40°C to 85°C

CCO_QA

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input 

I_IH

CLK, nCLK

V_CC= V_IN= V_{CC_MAX}

µA

High Current

Input 

I_IL

V_CC= V_{CC_MAX,}V_IN= 0V

-10

µA

k

Low Current

Input 

R_IN

Impedance

Reference Voltage for Input

Bias

V_BB

I_BB= -0.2mA

V_CC– 1.4

V_CC– 1.2

V_OH

V_OL

Output High Voltage¹

Output Low Voltage¹

V_{CCO_QA}– 1.18

V_{CCO_QA}– 1.98

V_{CCO_QA}– 0.81

V_{CCO_QA}– 1.55

Output Disabled Leakage

Current²

_CC= V_{CCO_QA_MAX}

V_O= V_CC-0.8V

I_OZH

I_OZL

µA

Output Disabled Leakage

Current²

V_CC= V_{CCO_QA_MAX}

V_O= 0V

NOTE 1. QA, nQA Outputs terminated with 50 to V_CC– 2V.

NOTE 2. Maximum voltage applied to a disabled (high-impedance) output is 3.465V.

January 21, 2018

8T73S1802 Datasheet

Table 4D. Single-Ended Characteristics, V = V

= 3.0V to 3.465V or 2.5V±5%, T = -40°C to 85°C

CCO_QB

Symbol Parameter

Test Conditions

Minimum

0.9 x V_CC

0.35 x V_CC

0.4 x V_CC

-0.3

Typical

Maximum

Units

V_IH

Input High Voltage¹

V_CC= 3.0V to 3.465V

V_CC= 2.5V ±5%

0.65 x V_CC

0.6 x V_CC

0.1 x V_CC

V_IM

Input Mid Voltage¹

V_IL

I_IH

Input High Voltage¹

Input High Current¹

V_IN= V_CC

µA

V_IN= 0V, V_CC= 3.0V to 3.465V

V_IN= 0V, V_CC= 2.5V ±5%

-85

-38

I_IL

Input Low Current¹

-62

-30

V_CC= 3.0V to V_{CC_MAX, OH}

= -100µA

V_{CCO_QB}– 0.1

High-

Level Voltage

V_OH

V_CC= 3.0V, I_OH= -6mA

V_CC= 3.0V, I_OH= -12mA

2.4

V_CC= 3.0V _toV_{CC_MAX, OL}

= 100µA

0.1

0.5

0.8

Low-Level

Voltage

V_OL

V_CC= 3.0V, I_OL= 6mA

V_CC= 3.0V, I_OL= 12mA

High-Level

Current

I_OH

I_OL

I_OZ

_CC= 3.3V, V_O= 1.65V

-39

µA

Low-Level

Current

V_CC= 3.3V, V_O= 1.65V

Output Disabled

Leakage Current

V_CC= V_{CC_MAX,}V_O= V_CCor V_O= 0V

-5

NOTE 1. Single-ended input: SEL1, SEL0, EN.

January 21, 2018

8T73S1802 Datasheet

AC Electrical Characteristics

1 2

Table 5. AC Characteristics, V = V

= V

= 3.0V to 3.465V or 2.5V±5%, T = -40°C to 85°C

CCO_QB A

CCO_QA

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

1000

200

Units

MHz

f_IN

Input Frequency CLK

Output

Frequency

f_OUT

V_PP

Peak-to-Peak Input Voltage³

0.15

1.0

1.3

Common Mode 

Input Voltage^{4, 5}

V_CC–

V_PP/2

V_CMR

Single-ended

Output 

Voltage Swing,

Peak-to-Peak

V_O(pp)

0.5

1.0

Differential

Output 

Voltage Swing,

V_{DIFF_OUT}

Peak-to-Peak

CLK to QA

CLK to QB

(Any Divider)

150

900

450

700

Propagation

Delay

t_PD

1100

1500

EN to Outputs Disabled

(High-Impedance)

t_DIS

Output Disable Time

t_EN

Output Enable Time

EN to Outputs Enabled

400

650

when QA and QB have the same

Output Divider

tsk(o)

Output Skew^{6, 7}QA to QB

1000

QA⁹

Part-to-Part

Skew

tsk(pp)

tsk(p)

300

Pulse Skew

100

f_IN= 800MHz

-50

Output 

Duty Cycle

Distortion⁸

t(odc)

f_IN= 200MHz, N = 1

f_IN= 200MHz, N = 2, 4, 8

-225

-150

225

150

Output 

Rise/Fall Time,

Differential

t_R/ t_F

20% to 80%

120

350

20% to 80%, V_{CCO_QB}= 3.3V

20% to 80%, V_{CCO_QB}= 2.5V

1.4

V/ns

Output

Slew Rate

V/t

200MHz – 1GHz,

Integration Range: 12kHz - 20MHz

150

250

400

200MHz – 1GHz,

Integration Range: 50kHz - 40MHz

Additive

Phase Jitter

tjit

250MHz,

Integration Range: 12kHz - 20MHz

250MHz,

Integration Range: 50kHz - 40MHz

NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications

after thermal equilibrium has been reached under these conditions.

NOTE 2. QA is terminated 50 to V_T= V_CC- 2V, the QB load is terminated 50 to V_CC/2.

NOTE 3. For single-ended LVCMOS input applications, refer to the Applications section Wiring the Differential Input Levels to Accept Sin-

gle-ended Levels.

January 21, 2018

8T73S1802 Datasheet

NOTE 4. V_ILshould not be less than -0.3V. V_IHshould not be higher than V_CC.

NOTE 5. Common mode input voltage is defined as the crosspoint.

NOTE 6. This parameter is defined in accordance with JEDEC standard 65.

NOTE 7. Defined as skew between outputs at the same supply voltage and with equal load conditions.

NOTE 8. Input CLK driven by an ideal clock input signal.

NOTE 9. Crosspoint to crosspoint distortion.

January 21, 2018

8T73S1802 Datasheet

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise.

This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as

the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental.

This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is

specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in

the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is

mathematically possible to calculate an expected bit error rate given a phase noise plot.

Additive Phase Jitter @ 622.08MHz

12kHz to 20MHz = 57fs (typical)

Offset from Carrier Frequency (Hz)

As with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. The noise

floor of the equipment can be higher or lower than the noise floor of the device. Additive phase noise is dependent on both the noise floor of the

input source and measurement equipment.

The additive phase jitter for this device was measured using a Rhode & Schwarz SMA100 input source and an Agilent E5052 Phase noise

analyzer.

January 21, 2018

8T73S1802 Datasheet

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value

of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental.

When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the

fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over

the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.

Additive Phase Jitter @ 250MHz

12kHz to 20MHz = 79fs (typical)

Offset from Carrier Frequency (Hz)

January 21, 2018

8T73S1802 Datasheet

Parameter Measurement Information

SCOPE

CC,

CCO_QA

nQx

V_EE

-0.5V ± 0.125V

-1.0V to -1.465V

3.3 Core/3.3V LVPECL Output Load AC Test Circuit

2.5V Core/2.5V LVPECL Output Load AC Test Circuit

1.25V±5%

1.5V to 1.7325V

SCOPE

CC,

CCO_QB

V_EE

-1.25V±5%

-1.5V to -1.7325V

3.3 Core/3.3V LVCMOS Output Load AC Test Circuit

2.5V Core/2.5V LVCMOS Output Load AC Test Circuit

V_{DIFF_OUT}

V_O(pp)

nCLK

CLK

V_PP

Cross Points

V_CMR

Differential Voltage Swing = 2 x Single-ended V_O(pp)

Differential Input Level

Single-Ended & Differential Output Voltage Swing

January 21, 2018

8T73S1802 Datasheet

Parameter Measurement Information, continued

nCLK

CLK

nCLK

CLK

nQA

V_{CCO_QB}

t_PD

LVPECL Propagation Delay

LVCMOS Propagation Delay

nCLK

CLK

nQA

V_{CCO_QB}

t_PLH

t_PHL

tsk(o)

tsk(p)= |t_PHL- t_PLH

Output Skew

LVPECL Pulse Skew

nQA

Output Rise/Fall Time

January 21, 2018

8T73S1802 Datasheet

Applications Information

3.3V LVPECL Clock Input Interface

The CLK /nCLK accepts LVPECL, LVDS, CML and other differential signals. Both V_SWINGand V_OHmust meet the V_PPand V_CMRinput

requirements. Figure 1A to Figure 1E show interface examples for the CLK/nCLK input driven by the most common driver types. The input

interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult

with the vendor of the driver component to confirm the driver termination requirements.

3.3V

Zo = 50Ω

CLK

100

CLK

nCLK

Zo = 50Ω

LVPECL

Differential

Inputs

nCLK

LVPECL

Differential

Inputs

CML Built-In Pullup

CML

Figure 1A. CLK/nCLK Input Driven by a CML Driver

Figure 1D. CLK/nCLK Input Driven by a 

Built-In Pullup CML Driver

3.3V

125

3.3V

Zo = 50Ω

3.3V LVPECL

CLK

VBB

nCLK

LVPECL

Differential

Inputs

LVPECL

Differential

Inputs

LVPECL

100 - 200

Figure 1B. CLK/nCLK Input Driven by a 

Figure 1E. CLK/nCLK Input Driven by a 

3.3V LVPECL Driver with AC Couple

3.3V LVPECL Driver

3.3V

Zo = 50Ω

CLK

VBB

100

nCLK

Zo = 50Ω

LVPECL

Differential

Inputs

LVDS

0.1µF

Figure 1C. CLK/nCLK Input Driven by a 3.3V LVDS

Driver

January 21, 2018

8T73S1802 Datasheet

2.5V LVPECL Clock Input Interface

The CLK /nCLK accepts LVPECL, LVDS, CML and other differential signals. Both V_SWINGand V_OHmust meet the V_PPand V_CMRinput

requirements. Figure 2A to Figure 2E show interface examples for the CLK/nCLK input driven by the most common driver types. The input

interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult

with the vendor of the driver component to confirm the driver termination requirements.

2.5V

Zo = 50Ω

2.5V

Zo = 50Ω

CLK

100

CLK

nCLK

Zo = 50Ω

LVPECL

Differential

Inputs

nCLK

LVPECL

Differential

Inputs

CML Built-In Pullup

CML

Figure 2A. CLK/nCLK Input Driven by a CML Driver

Figure 2D. CLK/nCLK Input Driven by a 

Built-In Pullup CML Driver

2.5V

Zo = 50Ω

2.5V LVPECL

CLK

VBB

nCLK

LVPECL

Differential

Inputs

100 - 200

Figure 2B. CLK/nCLK Input Driven by a 

Figure 2E. CLK/nCLK Input Driven by a 

2.5V LVPECL Driver with AC Couple

2.5V LVPECL Driver

2.5V

Zo = 50Ω

CLK

100

VBB

nCLK

Zo = 50Ω

LVPECL

LVDS

Differential

Inputs

0.1µF

Figure 2C. CLK/nCLK Input Driven by a 2.5V LVDS

Driver

January 21, 2018

8T73S1802 Datasheet

Wiring the Differential Input to Accept Single-ended LVPECL Levels

Figure 3 shows an example of the differential input that can be wired to accept single-ended LVPECL levels. The reference voltage level

V_BBgenerated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin.

0.1uF

CLK_IN

CLK

VBB

nCLK

Figure 3. Single-Ended LVPECL Signal Driving Differential Input

Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. A 1k resistor can

be used.

Outputs:

LVPECL Outputs

The unused LVPECL output pair can be left floating. We recommend that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

LVCMOS Outputs

The unused LVCMOS output can be left floating. There should be no trace attached.

January 21, 2018

8T73S1802 Datasheet

VFQFPN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed

on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific

and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis

and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved

when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is

also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to

avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and

the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note:

These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface

Mount Assembly of Amkor’s Thermally/ Electrically Enhance Lead frame Base Package, Amkor Technology.

SOLDER

EXPOSED HEAT SLUG

PIN PAD

GROUND PLANE

LAND PATTERN

(GROUND PAD)

PIN PAD

THERMAL VIA

Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

January 21, 2018

8T73S1802 Datasheet

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended

only as guidelines.

The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors

(DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines.

Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figure 5A and Figure 5B show

two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the

board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.

3.3V

125

3.3V

Z_o= 50

Input

Z_o= 50

84

Figure 5A. 3.3V LVPECL Output Termination

Figure 5B. 3.3V LVPECL Output Termination

January 21, 2018

8T73S1802 Datasheet

Termination for 2.5V LVPECL Outputs

Figure 6A and Figure 6B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to

V_CCO– 2V. For V_CCO= 2.5V, the V_CCO– 2V is very close to ground level. The R3 in Figure 6B can be eliminated and the termination is

shown in Figure 6C.

2.5V

V_CCO= 2.5V

2.5V

V_CCO= 2.5V

50

250

–

50

–

2.5V LVPECL Driver

62.5

Figure 6A. 2.5V LVPECL Driver Termination Example

Figure 6C. 2.5V LVPECL Driver Termination Example

2.5V

_CCO= 2.5V

50

–

2.5V LVPECL Driver

Figure 6B. 2.5V LVPECL Driver Termination Example

January 21, 2018

8T73S1802 Datasheet

Power Considerations

This section provides information on power dissipation and junction temperature for the 8T73S1802. 

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 8T73S1802 is the sum of the core power plus the power dissipated due to the load. 



Output Load:

LVPECL output load is 50 to (V_{CCO_QA}– 2V)

LVCMOS output load is 10pF



Frequency:

LVPECL is 800MHz

LVCMOS is 200MHz



The following is the power dissipation for V_CC= 3.3V + 5% = 3.465V, which gives worst case results.

The maximum current at 85°C is as follows:

I_{EE_MAX}= 109mA

•

Power__MAX= V_{CCx_MAX}* I_{EE_MAX}= 3.465V * 109mA = 377.685mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device.

The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures

that the bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow

and a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.378W * 74.7°C/W = 113.2°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the

type of board (multi-layer).

Table 6. Thermal Resistance  for 16-Lead VFQFPN,

Forced Convection

_JAvs. Air Flow

Meters per Second

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

74.7°C/W

65.3°C/W

58.5°C/W

January 21, 2018

8T73S1802 Datasheet

Reliability Information

Table 7.  vs. Air Flow Table for a 16-Lead VFQFPN

_JAvs. Air Flow

Meters per Second

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

74.7°C/W

65.3°C/W

58.5°C/W

Transistor Count

The transistor count for 8T73S1802 is: 1,255

Package Outline Drawings

The package outline drawings are located at the end of this document. The package information is the most current data available and is

subject to change without notice or revision of this document.

January 21, 2018

8T73S1802 Datasheet

Order Information

Table 8. Ordering Information

Part/Order Number

Marking

Package

Shipping Packaging

Temperature

8T73S1802NLGI

1802I

RoHS 6/6 16 VFQFPN

Tube

-40°C to +85°C

RoHS 6/6 16 VFQFPN

Quadrant 1 (EIA-481-C)

8T73S1802NLGI8

8T73S1802NLGI/W

Tape & Reel, Pin 1 Orientation: EIA-481-C

Tape & Reel, Pin 1 Orientation: EIA-481-D

-40°C to +85°C

RoHS 6/6 16 VFQFPN

Quadrant 2 (EIA-481-D)

1802I

Table 9. Pin 1 Orientation in Tape and Reel Packaging

Part Number Suffix

Pin 1 Orientation

Illustration

Quadrant 1 (EIA-481-C)

Quadrant 2 (EIA-481-D)

January 21, 2018

8T73S1802 Datasheet

Revision History

Revision Date

Description of Change

January 21, 2018

▪ Updated the package outline drawings; however, no technical changes.

▪ Replaced the package term VFQFN with VFQFPN.

February 7, 2017

▪ Page 24, Table 8 Ordering Information table- corrected first row/ Shipping Packaging column from Tray

to Tube.

Corporate Headquarters

Sales

Tech Support

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

www.IDT.com/go/support

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,

without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same

way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability

of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not

convey any license under intellectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-

sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property

January 21, 2018

16-VFQFPN Package Outline Drawing

3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad

NL/NLG16P2, PSC-4169-02, Rev 05, Page 1

ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ

16-VFQFPN Package Outline Drawing

3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad

NL/NLG16P2, PSC-4169-02, Rev 05, Page 2

Package Revision History

Description

Rev 04 Remove Bookmak at Pdf Format & Update Thickness Tolerance

Change QFN to VFQFPN

Date Created Rev No.

Oct 25, 2017

Jan 18, 2018

Rev 05

ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ

厂商	型号	描述	页数
IDT	8T73S1802NLGI	[ 1:2 Clock Fanout Buffer and Frequency Divider ]	25 页
IDT	8T73S1802NLGI/W	[ 1:2 Clock Fanout Buffer and Frequency Divider ]	25 页
IDT	8T73S1802NLGI8	[ 1:2 Clock Fanout Buffer and Frequency Divider ]	25 页
IDT	8T73S1802_17	[ 1:2 Clock Fanout Buffer and Frequency Divider ]	25 页
IDT	8T73S1802_18	[ 1:2 Clock Fanout Buffer and Frequency Divider ]	24 页
IDT	8T73S208	[ 2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer ]	22 页
IDT	8T73S208A-01	[ 2.5V, 3.3V Differential LVPECL Clock Divider and Buffer ]	24 页
IDT	8T73S208A-01NLGI	[ 2.5V, 3.3V Differential LVPECL Clock Divider and Buffer ]	24 页
IDT	8T73S208A-01NLGI8	[ 2.5V, 3.3V Differential LVPECL Clock Divider and Buffer ]	24 页
IDT	8T73S208A-01_16	[ 2.5V, 3.3V Differential LVPECL Clock Divider and Buffer ]	24 页

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