CYW20719,PDF,CYW20719 PDF资料,Datasheet,下载CYW20719技术资料

PRELIMINARY

CYW20719

Enhanced Low Power, BR/EDR/BLE

Bluetooth 5.0 SOC

The CYW20719 is a BT 5.0 compliant, stand-alone baseband processor with an integrated 2.4 GHz transceiver with BLE, EDR and

BR. The device is intended for use in audio, IoT, sensors (medical, home, security, and so forth) and human interface device (HID)

applications. Manufactured using an advanced 40nm CMOS low-power fabrication process, the CYW20719 employs high level of

integration to reduce external components, thereby minimizing application footprint and costs.

This datasheet provides details of the functional, operational, and electrical characteristics of the CYW20719 device. It is intended for

hardware, design, application, and OEM engineers.

Figure 1. Functional Block Diagram

RF

MODEM

PKA

SHA

LCU

RX/TX

AES

96 MHz

ARM CM4

w/FPU

Patch RAM

64 KB

RAM

448 KB

ROM 2 MB

Flash 1 MB

Bluetooth 5.0

MAC

Security Engine

Patch Control

AHB Bus Matrix

Random

Number

Generator

PWM x6

ADC

Core Buck

HP- LPO

128 KHz

XTALOSC

32 KHz

Key Scan

Watchdog

Peripheral

UART

GPIO

x40

Digital

LDO

LP- LPO

32 KHz

XTALOSC

24 MHz

SPIFFY X2

(MIPI

DBI-C, SPI,

Quad SPI)

1x I2C M/S

1x I2C

master

HCI UART

HID OFF

Timer

RF LDO

Power Management

Unit

Clock Management

Hardware Peripheral Block

Cypress Semiconductor Corporation

Document Number: 002-14815 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised Thursday, July 12, 2018

PRELIMINARY

CYW20719

Features

Bluetooth Subsystem

Peripherals and communication

■ 6x 16-bit PWMs

■ Complies with Bluetooth Core Specification v5.0 with LE 2

Mbps

■ Programmable key-scan matrix interface, up to 8x20 key-

scanning matrix ^1,2

■ Quadrature decoder²

■ Supports Basic Rate (BR), Enhanced Data Rate (EDR) 2&3

Mbps, Bluetooth Low Energy (BLE)

■ Supports Adaptive Frequency Hopping (AFH)

■ TX power 4 dBm

■ Watchdog timer (WDT)

■ 1x peripheral UART, 1x UART for programming and HCI

■ RX sensitivity -95.5 dBm (BLE)

■ Ultra-low-power radio

■ 2x SPI (master/slave mode) Blocks (SPI, Quad SPI, and

MIPI DBI-C)

❐ RX current 5.9 mA (BLE)

❐ TX current 5.6 mA @ 0 dBm (BLE)

■ 1x I2C master/slave and 1x I2C master

■ 1x 28-channel ADC (10-ENOB for DC measurement and 12-

ENOB for Audio measurement)

■ Hardware security engine²

Coexistence Support

■ Support for Global Coexistence Interface for easy coexis-

tence implementation with select Cypress Wi-Fi devices

General Purpose Input Output (GPIO)

■ 16 GPIOs on QFN package

MCU Subsystem

■ 96-MHz Arm Cortex-M4 microcontroller unit (MCU) with float-

■ 40 GPIOs on WLCSP package

■ Support up to 3.63 V operation

ing point unit (FPU)

■ Supports serial wire debug (SWD)

■ Four GPIOs support 16 mA and 8 mA sink at 3.3 V and 1.8 V

respectively

■ Runs Bluetooth stack and application

■ Option to execute from on-chip flash or RAM

Operating voltage and low-power support

■ Wide operating voltage range: 1.90 V to 3.63 V

Memory Subsystem

■ 1 MB flash

■ 5 power modes to implement ultra-low power application –

managed by real time operating system

■ 512 KB RAM

■ 0.4 uA current in HID-OFF mode (wake from GPIO).

■ 2 MB ROM that stores Bluetooth stack and driver and off-

loads flash for user applications

Packages

■ 5 mm x 5 mm 40-pin quad flat no-lead (QFN)

Audio features and interfaces

■ 1x I²S with master and slave modes

■ 3.2 mm x 3.1 mm 134-ball Wafer Level Chip Scale Package

(WLCSP)

■ 1x PCM

■ PDM²

Software Support

■ WICED Studio

■ Analog front end for analog microphone¹

Applications

Clocks

■ Wearables and Fitness bands

■ Headsets, earbuds, and other audio solutions

■ Home automation

■ On-chip 32 kHz oscillator (LP-LPO)

■ On-chip 128 kHz oscillator (HP-LPO)

■ 32 kHz crystal oscillator (Optional if low power modes not

required)

■ Blood pressure monitors and other medical applications

■ Proximity sensors

■ 24 MHz crystal oscillator

■ 48-bit real time clock (RTC)

■ Key Fobs

■ Thermostats and thermometers

■ Toys

1. Available only in WLCSP Package

2. Subjected to driver support in WICED Studio

®

Document Number: 002-14815 Rev. *D

Page 2 of 49

PRELIMINARY

CYW20719

Contents

1. Bluetooth Baseband Core ...........................................4

1.1 BQB and Regulatory Testing Support ...................4

2. MCU ...............................................................................5

3. External Reset ...............................................................5

4. Power Management Unit (PMU) ..................................6

5. Integrated Radio Transceiver ......................................7

5.1 Transmitter Path ....................................................7

5.2 Receiver Path ........................................................7

5.3 Local Oscillator (LO) ..............................................7

6. Peripheral and Communication Interfaces ................8

6.1 I2C Compatible Master ..........................................8

6.2 HCI UART Interface ..............................................8

6.3 Peripheral UART Interface ....................................8

6.4 Crystal Oscillators .................................................9

6.5 GPIO Ports ..........................................................10

6.6 Keyboard Scanner (Available only on WLCSP

6.13 PCM Interface ...................................................14

6.14 Security Engine .................................................14

6.15 Power Modes ....................................................15

7. Firmware ......................................................................15

8. Pin Assignments and GPIOs .....................................16

8.1 40-Pin QFN and WLCSP Pin Assignments .........16

8.2 40-Pin QFN and WLCSP GPIOs .........................18

9. Pin/Ball Maps ..............................................................23

9.1 40-Pin QFN Pin Map ...........................................23

9.2 WLCSP Ball Map .................................................24

10. Specifications ...........................................................29

10.1 Electrical Characteristics ...................................29

10.2 RF Specifications ..............................................33

10.3 Timing and AC Characteristics ..........................36

11. Mechanical Information ...........................................42

11.1 40-Pin QFN Package ........................................42

11.2 WLCSP Package ...............................................43

11.3 WLCSP Package Keep-out ...............................44

11.4 Tape Reel and Packaging Specifications ..........44

12. Ordering Information ................................................45

13. Additional Information .............................................45

13.1 Acronyms and Abbreviations .............................45

Sales, Solutions, and Legal Information .....................49

Package) .............................................................11

6.7 Mouse Quadrature Signal Decoder .....................11

6.8 ADC .....................................................................11

6.9 PWM ....................................................................12

6.10 Serial Peripheral Interface block .......................13

6.11 Pulse Density Modulation (PDM) Microphone ...13

6.12 I2S Interface ......................................................13

Document Number: 002-14815 Rev. *D

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PRELIMINARY

CYW20719

1. Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all time-critical functions required for high-performance Bluetooth operation. The

BBC manages the buffering, segmentation, and routing of data for all connections. It prioritizes and schedules all RX/TX activities

including adv, paging, scanning, and servicing of connections. In addition to these functions, it independently handles the host

controller interface (HCI) including all commands, events, and data flowing over HCI. The core also handles symbol timing, forward

error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), authentication, data encryption/decryption, and

data whitening/dewhitening.

Table 1. Bluetooth Features

Bluetooth 1.0

Bluetooth 1.2

Interlaced Scans

Bluetooth 2.0

Basic Rate

SCO

EDR 2 Mbps and 3 Mbp

Adaptive Frequency Hopping

eSCO

–

Paging and Inquiry

Page and Inquiry Scan

Sniff

–

Bluetooth 2.1

Bluetooth 3.0

Bluetooth 4.0

Bluetooth Low Energy

–

Secure Simple Pairing

Enhanced Inquiry Response

Sniff Subrating

Unicast Connectionless Data

Enhanced Power Control

eSCO

–

Bluetooth 4.1

Bluetooth 4.2

Bluetooth 5.0

LE 2 Mbps

Low Duty Cycle Advertising

Dual Mode

Data Packet Length Extension

LE Secure Connection

Link Layer Privacy

Slot Availability Mask

High Duty Cycle Advertising

LE Link Layer Topology

1.1 BQB and Regulatory Testing Support

The CYW20719 fully supports Bluetooth Test mode as described in Part 1:1 of the Specification of the Bluetooth System v3.0. This

includes the transmitter tests, normal and delayed loop back tests, and reduced hopping sequence.

In addition to the standard Bluetooth Test Mode, the CYW20719 also supports enhanced testing features to simplify RF debugging

and qualification and type-approval testing. These features include:

■ Fixed frequency carrier wave (unmodulated) transmission

❐ Simplifies some type-approval measurements (Japan)

❐ Aids in transmitter performance analysis

■ Fixed frequency constant receiver mode

❐ Receiver output directed to I/O pin

❐ Allows for direct BER measurements using standard RF test equipment

❐ Facilitates spurious emissions testing for receive mode

■ Fixed frequency constant transmission

❐ 8-bit fixed pattern or PRBS-9

❐ Enables modulated signal measurements with standard RF test equipment

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PRELIMINARY

CYW20719

2. MCU

The CYW20719 includes a Cortex M4 processor with 2 MB of ROM, 448 KB of data RAM, 64 KB of patch RAM, and 1 MB of on-chip

flash. The CM4 has a maximum speed of 96 MHz. CYW20719 supports execution from on-chip flash (OCF).

The CM4 also includes a single precision IEEE 754 compliant floating point unit (FPU).

The CM4 runs all the BT layers as well as application code. The ROM includes LM, HCI, L2CAP, GATT, as well as other stack layers

freeing up the flash for application usage. A standard SWD Interface provides debugging support.

3. External Reset

An external active-low reset signal, RESET_N, can be used to put the CYW20719 in the reset state. The RESET_N should be released

only after the VDDO supply voltage level has been stabilized for at least 35 ms.

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PRELIMINARY

CYW20719

4. Power Management Unit (PMU)

Figure 2 shows the CYW20719 PMU block diagram. The CYW20719 includes an integrated buck regulator, a bypass LDO, a capless

LDO for digital circuits and a separate LDO for RF. The bypass LDO automatically takes over from the buck once V_batsupply falls

below 2.1 V.

The voltage levels shown in this figure are the default settings; the firmware may change voltage levels based on operating conditions.

Figure 2. Default Usage Mode

CYW20719 PMU

VBAT: 1.76V to 3.63V

SR_VDDBAT3V

DIGLDO_

VDDOUT

DIGLDO_VDDIN

SR_VLX

Digital LDO

VBAT

Core buck

regulator

BT Digital

SR_

PVSS

Internal LDO (capless)

CBUCK

BT Retention Memory

Maximum 50 mA

RFLDO_

VDDOUT

BYPLDO

50 mA

RF LDO

BT RF

RFLDO_VDDIN

Denotes board pin

Denotes chip pin

Denotes power switch

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PRELIMINARY

CYW20719

5. Integrated Radio Transceiver

The CYW20719 has an integrated radio transceiver that has been designed to provide low power operation in the globally available

2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and exceeds the requirements to provide

the highest communication link quality of service.

5.1 Transmitter Path

The CYW20719 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.

Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes

any frequency drift or anomalies in the modulation characteristics of the transmitted signal.

Power Amplifier

The CYW20719 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation.

5.2 Receiver Path

The receiver path uses a low IF scheme to down-convert the received signal for demodulation in the digital demodulator and bit

synchronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in

the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYW20719 to be used

in most applications without off-chip filtering.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit

synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the CYW20719 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller

to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the

transmitter should increase or decrease its output power.

5.3 Local Oscillator (LO)

LO provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels for BR/EDR functionality. The

CYW20719 uses an internal loop filter.

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PRELIMINARY

CYW20719

6. Peripheral and Communication Interfaces

2

6.1 I C Compatible Master

The CYW20719 provides a 2-pin I²C compatible Master interface to communicate with I²C compatible peripherals. The I²C compatible

master supports the following clock speeds:

■ 100 kHz

■ 400 kHz

■ 800 kHz (Not a standard I²C-compatible speed.)

■ 1 MHz (Compatibility with high-speed I²C-compatible devices is not guaranteed.)

SCL and SDA lines can be routed to any of the P0-P39 GPIOs allowing for flexible system configuration. When used as SCL/SDA

the GPIOs go into open drain mode and require an external pull-up for proper operation. I²C block does not support multi master

capability by either master/slave devices.

I²C1 is Master Only; I²C2 is Master/Slave. The Slave support is subject to driver support in WICED^Studio.

6.2 HCI UART Interface

The CYW20719 includes a UART interface for factory programming as well as when operating as a BT HCI device in a system with

an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from

115200 bps to 1.5 Mbps. Typical rates are 115200, 921600, 1500000 bps although intermediate speeds are also available. Support

for changing the baud rate during normal HCI UART operation is included through a vendor-specific command. The CYW20719 UART

operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%. The UART interface

has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth

UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.

During HCI mode the DEV_WAKE signal can be programmed to wake up the CYW20719 or allow the CYW20719 to sleep when radio

activities permit. The CYW20719 can also wake up the host as needed or allow the host to sleep via the HOST_WAKE signal. The

combined two signals allow the host and the CYW20719 to optimize system power consumption by allowing independent control of

low power modes. DEV_WAKE and HOST_WAKE signals can be enabled via a vendor specific command.

6.3 Peripheral UART Interface

The CYW20719 has a second UART that may be used to interface to peripherals. This peripheral UART is accessed through the

optional I/O ports, which can be configured individually and separately for each functional pin. The CYW20719 can map the peripheral

UART to any GPIO (P0-P39). The Peripheral UART is functionally the same as HCI UART but with a 256 byte transmit and receive

FIFO.

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PRELIMINARY

CYW20719

6.4 Crystal Oscillators

6.4.1 24-MHz Crystal Oscillator

The CYW20719 uses a 24 MHz crystal oscillator (XTAL). The XTAL must have an accuracy of ±20 ppm as defined by the Bluetooth

specification. Two external load capacitors are required to work with the crystal oscillator. The selection of the load capacitors is XTAL-

dependent (see Figure 3).

Figure 3. Recommended 24 MHz Oscillator Configuration

CL1

XIN

Crystal

XOUT

CL2

Table 2. Reference Crystal Electrical Specifications

Parameter

Nominal frequency

Conditions

Minimum

Typical

24.000

Maximum

Unit

MHz

–

Oscillation mode

Fundamental

–

Frequency Accuracy

Includes operating temperature

range and aging

–

± 20

ppm

Equivalent series resistance

Load capacitance

Drive level

–

8

–

60

–

ohm

pF

200

2

μW

pF

Shunt capacitance

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PRELIMINARY

CYW20719

6.4.2 32 kHz Crystal Oscillator

The CYW20719 includes a 32 KHz oscillator to provide accurate timing during low power operations. Figure 4 shows the 32 kHz XTAL

oscillator with external components and Table 3 lists the oscillator’s characteristics. This oscillator can be operated with 32.768 kHz

crystal oscillator or be driven with a clock input at similar frequency. The default component values are: R1 = 10 MΩ and C1 = C2 =

~6 pF. The values of C1 and C2 are used to fine-tune the oscillator.

Figure 4. Recommended 32 kHz Oscillator Electrical Specification

C2

32.768 kH z

R1

XTAL

C1

Table 3. Reference 32 kHz Oscillator Electrical Specification

Parameter

Output frequency

Symbol

F_oscout

Conditions

–

Minimum

Typical

Maximum

Unit

kHz

ppm

ms

–

32.768

–

Frequency tolerance

Start-up time

–

Crystal-dependent

–

100

500

–

T_startup

P_drv

–

XTAL drive level

For crystal selection

–

0.5

70

2.2

–

μW

XTAL series resistance

XTAL shunt capacitance

External AC Input Amplitude

R_series

C_shunt

–

kΩ

–

pF

V

_IN(AC)

C_couple= 100 pF;

R_bias= 10 Mohm

400

–

mVpp

6.5 GPIO Ports

The CYW20719 has 40 GPIOs labeled P0-P39 on WLCSP package and 16 GPIOs on QFN package. All GPIOs support the following:

■ programmable pull-up/down of approx 45K Ohms.

■ input disable, allowing pins to be left floating or analog signals connected without risk of leakage.

■ source/sink 8 mA at 3.3 V and 4 mA at 1.8 V.

■ P15 is Bonded to the same pin as XTALI_32K on the QFN package (Pin 32). If External 32.768KHz crystal is not used, then this

pin can be used as GPIO P15.

■ P26/P27/P28/P29 (some of these pins are not available on QFN package) sink/source 16 mA at 3.3 V and 8 mA at 1.8 V.

Most peripheral functions can be assigned to any GPIO. For details, refer to Table 4 and Table 5.

For more details on Supermux configuration and control, refer to "Supermux Wizard for CYW20719" user guide.

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PRELIMINARY

CYW20719

6.6 Keyboard Scanner (Available only on WLCSP Package)

The CYW20719 includes a HW keyscanner that supports a maximum matrix size of 20x8. The scanner has 8 inputs (also referred to

as rows) and 20 outputs (also referred to as columns). Keys are detected by driving the columns down sequentially and sampling the

rows. The HW scanner includes support for ghost key detection and debouncing. The scanner can also operate in sleep and PDS

mode allowing low power operation while continuing to detect/store all key strokes, up or down. In other low power modes, the scanner

can continue to monitor the matrix and initiate exit to active mode upon detecting a change of state.

Note: Subject to the driver support in WICED^Studio.

6.7 Mouse Quadrature Signal Decoder

The CYW20719 includes one double-axis and one single axis quadrature decoders. There are two input lines for each axis and a

programmable control signal that can be active high or low. The application can access the quadrature interface via the driver included

in the firmware.

Note: Subject to the driver support in WICED^Studio.

6.8 ADC

CYW20719 includes is a Σ-Δ ADC designed for audio (13 bits) and DC (10 bits) measurements. The ADC can measure the voltage

on 28 GPIO. When used for analog inputs, the GPIOs must be placed in digital input disable mode to disconnect the digital circuit

from the pin and avoid leakage. The internal band gap reference has ±5% accuracy without calibration. Calibration and digital

correction schemes can be applied to reduce ADC absolute error and improve measurement accuracy in DC mode.

■ P0, P1, P8-P18, P21-23, P28-P38 can be used as ADC inputs.

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PRELIMINARY

CYW20719

6.9 PWM

The CYW20719 has six internal PWMs, labeled PWM0-5

■ Each of the six PWM channels contains the following registers:

❐ 16-bit initial value register (read/write)

❐ 16-bit toggle register (read/write)

❐ 16-bit PWM counter value register (read)

■ PWM configuration register is shared among PWM0–5 (read/write). This 6-bit register is used:

❐ To enable/disable each PWM channel

❐ To select the clock of each PWM channel

❐ To invert the output phase of each PWM channel

The application can access the PWM module through the FW driver.

Figure 5 shows the structure of one PWM channel.

Figure 5. PWM Block Diagram

pwm_cfg_adr register

pwm#_init_val_adr register

16

pwm#_togg_val_adr register

16

pwm#_cntr_adr

16

cntr value is ARM readable

pwm_out

Example: PWM cntr w/ pwm#_init_val = 0 (dashed line)

PWM cntr w/ pwm#_init_val = x (solid line)

16'HFFFF

pwm_togg_val_adr

16'Hx

16'H000

pwm#_init

_value is x

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PRELIMINARY

CYW20719

6.10 Serial Peripheral Interface block

The CYW20719 has two independent SPI interfaces. Both interfaces support Single, Dual, and Quad mode SPI operations as well

as MIPI DBI-C Interface.Either of the interface can be a master/slave. SPI2 can support only one Slave. SPI1 has a 1024 byte transmit

and receive buffers which is shared with the host UART interface. SPI2 has a dedicated 256 byte transmit and receive buffers. To

support more flexibility for user applications, the CYW20719 has optional I/O ports that can be configured individually and separately

for each functional pin. SPI I/O voltage depends on VDDO.

6.10.1 MIPI interface

There are three options in DBI type-C corresponding to 9-bit, 16-bit, and 8-bit modes. The CYW20719 plays the role of host, and only

the 9-bit and 8-bit modes (option 1 and option 3 in DBI-C spec) are supported. In the 9-bit mode, the SCL, CS, MOSI, and MISO pins

are used. In the 8-bit mode, an additional pin DCX, indicating whether the current outgoing bit stream is a command or data byte is

required.

6.11 Pulse Density Modulation (PDM) Microphone

The CYW20719 accepts a ΣΔ-based one-bit PDM input stream and outputs filtered samples at either 8 kHz or 16 kHz sampling rates.

The PDM signal derives from an external kit that can process analog microphone signals and generate digital signals. The PDM input

shares the filter path with the aux ADC. Two types of data rates can be supported:

■ 8 kHz

■ 16 kHz

The external digital microphone takes in a 2.4 MHz clock generated by the CYW20719 and outputs a PDM signal which is registered

by the PDM interface with either the rising or falling edge of the 2.4 MHz clock selectable through a programmable control bit. The

design can accommodate two simultaneous PDM input channels, so stereo voice is possible.

Note: Subject to the driver support in WICED Studio.

2

6.12 I S Interface

The CYW20719 supports a single I²S digital audio port in both master and slave modes. The I²S signals are:

■ I²S Clock: I²S SCK

■ I²S Word Select: I²S WS

■ I²S Data Out: I²S DO

■ I²S Data In: I²S DI

I²S SCK and I²S WS become outputs in master mode and inputs in slave mode, while I²S DO always stays as an output and I²S DI

stays as input. The channel word length is fixed to 16 bits (frame length of 32 bits) and the data is justified so that the MSB of the left-

channel data is aligned with the MSB of the I²S bus, as per I²S Specifications. The MSB of each data word is transmitted one bit clock

cycle after the I²S WS transition, synchronous with the falling edge of bit clock. Left Channel data is transmitted when I²S WS is low,

and right-channel data is transmitted when I2S WS is high. Data bits sent by the CYW20719 are synchronized with the falling edge

of I²S SCK and should be sampled by the receiver on the rising edge of the I²S SCK.

The I²S port is primarily used to transfer audio samples while using the A2DP profile¹. The A2DP controller is half duplex and the

direction of the audio samples depend on the A2DP role (sink/source). The I2S clock in the master mode can either be

■ 44.1 KHz x 32 bits per frame = 1411.2 KHz

■ 48 KHz x 32 bits per frame = 1536 KHz

In the slave mode, any clock rate is supported up to a maximum of 3.072 MHz.

Note: PCM interface shares HW with the I²S interface which means that both voice and audio cannot be routed at the same time.

2

1. The I S port cannot be used at the application level for purposes other than routing A2DP audio samples.

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CYW20719

6.13 PCM Interface

The CYW20719 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode. In master mode,

the CYW20719 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another device on

the PCM interface and are inputs to the CYW20719. Some of the parameters of the PCM interface may be configured by the host.

The PCM interface is used for full-duplex bi-directional transfer of 8K or 16K voice samples from and to a SCO or eSCO connection².

By default, the PCM interface runs in an I²S compatible mode, which allows the CYW20719 to transfer voice samples to I²S devices.

Note: PCM interface shares HW with the I²S interface which means that both voice and audio cannot be routed simultaneously.

6.13.1 Slot Mapping

The CYW20719 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM Interface. These three

channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz voice sample

interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 256kHz, 512

kHz, 1024 kHz or 2048 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit

and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on

unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling

edge of the PCM clock during the last bit of the slot.

6.13.2 Frame Synchronization

The CYW20719 supports both short and long-frame synchronization in both master and slave modes and can be configured from the

host. In short frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a

single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of

the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode,

the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and

the pulse starts coincident with the first bit of the first slot.

6.13.3 Data Formatting

The CYW20719 may be configured to generate or accept several different data formats. For conventional narrow band speech mode,

the CYW20719 always uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support

various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit,

or a programmed value on the output. The default format is 13-bit 2's complement data, left justified, filled with 0's and clocked MSB

first.

6.13.4 Burst PCM Mode

In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and

save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with

an HCI command from the host.

6.14 Security Engine

The CYW20719 includes a hardware security accelerator which greatly decreases the time required to perform typical security

operations.This security engine includes:

■ Public key acceleration (PKA) cryptography

■ AES-CTR/CBC-MAC/CCM acceleration

■ SHA2 message hash and HMAC acceleration

■ RSA encryption and decryption of modulus sizes up to 2048 bits

■ Elliptic curve Diffie-Hellman in prime field GF(p)

Note: Security engine is used only by Bluetooth stack to reduce CPU overhead. It is not available for application use

6.14.1 Random Number Generator

This hardware block is used for key generation for Bluetooth.

Note: Availability for use by the application is subject to the support in WICED^Studio.

2. The PCM interface cannot be used as a generic serial interface at the application level. It can only be used for routing SCO or eSCO voice samples.

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CYW20719

6.15 Power Modes

The CYW20719 supports the following HW power modes:

■ Active mode - Normal operating mode in which all peripherals are available and the CPU is active.

■ Idle mode- In this mode, the CPU is in “Wait for Interrupt” (WFI) and the HCLK, which is the high frequency clock derived from the

main crystal oscillator is running at a lower clock speed. Other clocks are active and the state of the entire chip is retained.

■ Sleep mode - In this mode, CPU is in WFI and the HCLK is not running. The PMU determines if the other clocks can be turned off

and does accordingly. State of the entire chip is retained, the internal LDOs run at a lower voltage (voltage is managed by the PMU),

and SRAM is retained.

■ Power Down Sleep (PDS) mode -This mode is an extension of the PMU Sleep wherein most of the peripherals such as UART and

SPI are turned off. The entire memory is retained, and on wakeup the execution resumes from where it paused.

■ Shut Down Sleep (SDS) mode -Everything is turned off except I/O Power Domain, RTC, and LPO. The device can come out of

this mode either due to BT activity or by an external interrupt. Before going into this mode, the application can store some bytes of

data into “Always On RAM” (AON). When the device comes out of this mode, the data from AON is restored. After waking from

SDS, the application will start from the beginning (warmboot) and has to restore its state based on information stored in AON. In

the SDS mode, a single BT task with no data activity, such as an ACL connection, BLE connection, or BLE advertisement can be

performed.

■ HID-OFF (Timed-Wake) mode -The device can enter this mode asynchronously, that is, the application can force the device into

this mode at any time. I/O Power Domain, RTC, and LPO are the only active blocks. A timer that runs off the LPO is used to wake

the device up after a predetermined fixed time.

■ HID-OFF (External Interrupt-Waked) mode - This mode is similar to Timed-Wake, but in HID-OFF mode even the LPO and RTC

are turned off. So, the only wakeup source is an external interrupt.

Transition between power modes is handled by the on-chip firmware with host/application involvement. Please see Firmware Section

for details.

7. Firmware

The CYW20719 ROM firmware runs on a real time operating system and handles the programming and configuration of all on-chip

hardware functions as well as the BT/LE baseband, Link Manager (LM), HCI, Generic Attribute Profile (GATT), Attribute Protocol

(ATT), Logical Link Control and Adaptation Protocol (L2CAP) and Service Discovery Protocol (SDP) layers. The ROM also includes

drivers for on-chip peripherals as well as handling on-chip power management functions including transitions between different power

modes.

The CYW20719 is fully supported by the Cypress WICED^®Studio platform. WICED releases provide latest ROM patches, drivers,

and sample applications allowing customized applications using the CYW20719 to be built quickly and efficiently.

Please refer to WICED Technical Brief and CYW20719 Product Guide for details on the firmware architecture, driver documentation,

power modes and how to write applications/profiles using the CYW20719.

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8. Pin Assignments and GPIOs

This section addresses both QFN and WLCSP pin assignments and GPIOs for the CYW20719 device.

8.1 40-Pin QFN and WLCSP Pin Assignments

Table 4. 40-Pin QFN and WLCSP Pin Assignments

Pin Number

Pin Name

I/O

Power Domain

Description

QFN-40

WLCSP

Microphone

ADC_avddBAT

ADC_AVDDC

Mic_avdd

–

5

I

VDDIO

–

VDDIO

3

No Connect

19

32

4

MIC_AVDD

AVSS

Microphone supply

Micbias

Microphone Bias Supply

Microphone negative input

Microphone positive input

Analog ground

Micn

Micp

18

34

17

33

47

ADC_AVSS

ADC_AVSSC

ADC_REFGND

Mic_avss

AVSS

Analog ground

AVSS

Analog reference ground

Microphone analog ground

AVSS

Baseband Supply

BT_VDDO

25

–

1,8,9,11,14,26,29,4

2,56,66,91

I

I/O

I

VDDO

VDDC

VDDO

I/O Pad Power supply

BT_VDDC

VDDO

2,43,58,74,

99

Baseband core power supply

39

-

LHL PAD power supply. Can be tied to

BT_VDDO.

RF Power Supply

BT_PAVDD

17

21

20

19

116

106

125

110

I

PAVDD

PA supply

BT_PLLVDD1p2

BT_VCOVDD1p2

BT_IFVDD1P2

Onboard LDO's

DIGLDO_VDDIN

DIGLDO_VDDOUT

RFLDO_VDDIN

RFLDO_VDDOUT

SR_VDDBAT3V

VDDBAT3V

PLLVDD1P2 RFPLL and crystal oscillator supply

VCOVDD1P2 VCO supply

IFVDD1P2

IFPLL Power Supply

16

–

127

126

111

128

129

120

121

I

O

I

Internal Digital LDO input

Internal Digital LDO output

RF LDO Input

15

14

13

–

O

I

RF LDO Output

Core Buck Input

I

Core Buck Input

SR_VLX

12

O

Core Buck Output

Ground Pins

BT_PAVSS

BT_PLLVSS

BT_VCOVSS

BT_IFVSS

–

123

107

119

115

I

VSS

Ground

BT_VSSC

30, 57, 75, 87, 117,

118, 124, 133, 134

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Table 4. 40-Pin QFN and WLCSP Pin Assignments (Cont.)

Pin Number

WLCSP

Pin Name

I/O

Power Domain

Description

QFN-40

VSSC

–

112

I

VSS

Ground

VSSO_0

10,13, 25, 28,72,

96,101

SR_PVSS

xtal_avss

–

130

35

I

VSS

Ground

XTAL_AVSS Crystal ground

PMU_AVSS PMU ground

PMU_AVSS

UART

113

BT_UART_CTS_N

30

29

15

31

I, PU

VDDO

Clear to send (CTS) for HCI UART

interface. Leave unconnected if not

used.

BT_UART_RTS_N

O, PU

Request to send (RTS) for HCI UART

interface. Leave unconnected if not

used.

BT_UART_RXD

BT_UART_TXD

27

28

45

46

I

VDDO

UART serial input. Serial data input for

the HCI UART interface.

O, PU

UART serial output. Serial data output

for the HCI UART interface.

Crystal

BT_XTALI

22

105

I

PLLVDD1P2 Crystal oscillator input. See “The XTAL

must have an accuracy of ±20 ppm as

defined by the Bluetooth specification.

Two external load capacitors are

required to work with the crystal oscil-

lator. The selection of the load capac-

itors is XTAL-dependent (see Figure 3)”

for options.

BT_XTALO

XTALI_32K

XTALO_32K

BT_RF

23

32

31

18

–

104

6

O

I

PLLVDD1P2 Crystal oscillator output.

VDDO

–

Low-power oscillator input.

Low-power oscillator output.

RF Antenna Port

20

O

–

132

68

BT_CLK_REQ

JTAG_SEL

O

–

N/A

–

Used for shared-clock application.

11

102

Reserved ARM JTAG debug mode

control. Connect to GND for all applica-

tions.

RST_N

10

103

I

VDDO

Active-low system reset with internal

pull-up resistor.

Reserved Pins

Reserved

26

–

21, 36, 49, 61, 77,

84, 85, 108

N/A

Reserved. Leave unconnected.

Reserved, connect to GND

Reserved, Connect to

GND

16, 92

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8.2 40-Pin QFN and WLCSP GPIOs

Table 5. 40-Pin QFN and WLCSP GPIOs

Pin Number

Power

Domain

Pin Name

I/O

Description

QFN-40

WLCSP

BT_DEV_WAKE

–

86

I

VDDO

Asignal from the host to the CYW20719 indicating

that the host requires attention.

BT_HOST_WAKE

24

76

O

VDDO

A signal from the CYW20719 device to the host

indicating that the Bluetooth device requires

attention.

BT_GPIO_2

BT_GPIO_3

BT_GPIO_4

BT_GPIO_5

P0

–

3

44

59

79

78

93

I/O

VDDO

GPIO: Can also be configured as a GCI Pin

■ GPIO: P0

■ Keyboard scan input (row): KSI0

■ A/D converter input 29

■ Supermux I/O functions as defined in Table 6.

P1

4

54

I/O

VDDO

■ GPIO: P1

■ Keyboard scan input (row): KSI1

■ A/D converter input 28

■ Supermux I/O functions as defined in Table 6

P2

P3

P4

P5

P6

P7

P8

P9

34

–

60

22

23

37

50

62

69

52

I/O

VDDO

■ GPIO: P2

■ Keyboard scan input (row): KSI2

■ Supermux I/O functions as defined in Table 6

■ GPIO: P3

■ Keyboard scan input (row): KSI3

■ Supermux I/O functions as defined in Table 6

35

–

■ GPIO: P4

■ Keyboard scan input (row): KSI4

■ Supermux I/O functions as defined in Table 6

■ GPIO: P5

■ Keyboard scan input (row): KSI5

■ Supermux I/O functions as defined in Table 6

36

37

–

■ GPIO: P6

■ Keyboard scan input (row): KSI6

■ Supermux I/O functions as defined in Table 6

■ GPIO: P7

■ Keyboard scan input (row): KSI7

■ Supermux I/O functions as defined in Table 6

■ GPIO: P8

■ A/D converter input 27

■ Supermux I/O functions as defined in Table 6

–

■ GPIO: P9

■ A/D converter input 26

■ External T/R switch control: tx_pd

■ Supermux I/O functions as defined in Table 6

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Table 5. 40-Pin QFN and WLCSP GPIOs (Cont.)

Pin Number

Pin Name

Power

Domain

I/O

Description

QFN-40

WLCSP

P10

40

63

I/O

VDDO

■ GPIO: P10

■ Keyboard scan output (column): KSO2

■ A/D converter input 25

■ Supermux I/O functions as defined in Table 6

P11

P12

P13

P14

P15^c

P16

P17

P18

40

–

70

40

71

24

7

I/O

VDDO

■ GPIO: P11

■ A/D converter input 24

■ Supermux I/O functions as defined in Table 6

■ GPIO: P12

■ A/D converter input 23

■ Supermux I/O functions as defined in Table 6

1

■ GPIO: P13

■ A/D converter input 22

■ Supermux I/O functions as defined in Table 6

–

■ GPIO: P14

■ A/D converter input 21

■ Supermux I/O functions as defined in Table 6

32

33

38

–

■ GPIO: P15

■ A/D converter input 20

■ Supermux I/O functions as defined in Table 12

48

38

51

■ GPIO: P16

■ A/D converter input 19

■ Supermux I/O functions as defined in Table 6

■ GPIO: P17

■ A/D converter input 18

■ Supermux I/O functions as defined in Table 6

■ GPIO: P18

■ A/D converter input 17

■ Supermux I/O functions as defined in Table 6

P19

P20

P21

–

39

12

53

I/O

VDDO

■ Reserved for system use. Leave unconnected.

■ GPIO: P21

■ A/D converter input 14

■ Supermux I/O functions as defined in Table 6

P22

P23

–

1

27

64

I/O

VDDO

■ GPIO: P22

■ A/D converter input 13

■ Supermux I/O functions as defined in Table 6

■ GPIO: P23

■ A/D converter input 12

■ Supermux I/O functions as defined in Table 6

P24

P25

P26

–

8

7

90

97

83

I/O

VDDO

■ GPIO: P24

■ Supermux I/O functions as defined in Table 6

■ GPIO: P25

■ Supermux I/O functions as defined in Table 6

■ GPIO: P26

■ Current: 16 mA sink

■ Supermux I/O functions as defined in Table 6

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Table 5. 40-Pin QFN and WLCSP GPIOs (Cont.)

Pin Number

Pin Name

Power

Domain

I/O

Description

QFN-40

WLCSP

P27

P28

–

94

I/O

VDDO

■ GPIO: P27

■ Current: 16 mA sink

■ Supermux I/O functions as defined in Table 6

1

2

41

I/O

VDDO

■ GPIO: P28

■ A/D converter input 11

■ Current: 16 mA sink

■ Supermux I/O functions as defined in Table 6

P29

80

■ GPIO: P29

■ Optical control output: QOC3

■ A/D converter input 10

■ Current: 16 mA sink

■ Supermux I/O functions as defined in Table 6

P30

P31

P32

P33

P34

P35

P36

P37^c

P38

–

9

5

–

6

–

95

73

98

100

81

65

55

88

89

82

I/O

VDDO

■ GPIO: P30

■ A/D converter input 9

■ Supermux I/O functions as defined in Table 6

■ GPIO: P31

■ A/D converter input 8

■ Supermux I/O functions as defined in Table 6

■ GPIO: P32

■ A/D converter input 7

■ Supermux I/O functions as defined in Table 6

■ GPIO: P33

■ A/D converter input 6

■ Supermux I/O functions as defined in Table 6

■ GPIO: P34

■ A/D converter input 5

■ Supermux I/O functions as defined in Table 6

■ GPIO: P35

■ A/D converter input 4

■ Supermux I/O functions as defined in Table 6

■ GPIO: P36

■ A/D converter input 3

■ Supermux I/O functions as defined in Table 6

■ GPIO: P37

■ A/D converter input 2

■ Supermux I/O functions as defined in Table 6

■ GPIO: P38

■ A/D converter input 1

■ Supermux I/O functions as defined in Table 6

P39

■ Reserved for system use. Leave unconnected.

Strapping Pins

BT_TM1

–

67

I

–

Device test mode control. Connect to GND for all

applications.

PMU_DISABLE

109

VDDO

PMU Enable/Disable. Connected to ground.

a. All GPIOs are super mux. All GPIOs can be programmed for any alternative functions as listed in Table 6 and Table 7.

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b. During power-on reset, all inputs are disabled.

c. P15 and P37 should not be driven high externally while the part is held in reset (they can be floating or driven low). Failure to do so may cause some current to flow

through these pins until the part comes out of reset.

Table 6. GPIO Supermux Input Functions (Cont.)

Table 6. GPIO Supermux Input Functions

Input

spiffy2_int[s]

puart_rx

puart_cts_n

SCL

Description

SPIFFY 2 Interrupt (Slave)

Peripheral UART RX

Peripheral UART CTS

I2C Clock

Input

SWDCK

Description

Serial Wire Debugger Clock

Serial Wire Debugger I/O

SPIFFY 1 Clock (Slave)

SWDIO

spiffy1_clk[s]

spiffy1_cs[s]

SPIFFY 1 Chip Select (Slave)

SDA

I2C Data

spiffy1_mosi[s] SPIFFY 1 MOSI (Slave)

spiffy1_miso[m] SPIFFY 1 MISO (Master)

SCL2

I2C2 Clock

SDA2

I2C2 Data

spiffy1_io2

SPIFFY 1 I/O 2 (Quad SPI)

SPIFFY 1 I/O 3 (Quad SPI)

SPIFFY 1 Interrupt (Slave)

SPIFFY 2 Clock (Slave)

PCM_IN

PCM_CLK

PCM_SYNC

I2S_DI

PCM Input

spiffy1_io3

PCM Clock

spiffy1_int[s]

spiffy2_clk[s]

spiffy2_cs[s]

PCM Sync

I2S Data Input

I2S Word Select

I2S Clock

SPIFFY 2 Chip Select (Slave)

I2S_WS

I2S_CLK

spiffy2_mosi[s] SPIFFY 2 MOSI (Slave)

spiffy2_miso[m] SPIFFY 2 MISO (Master)

PDM_IN_Ch_1 PDM Input Channel 1

PDM_IN_Ch 2 PDM Input Channel 2

spiffy2_io2

spiffy2_io3

SPIFFY 2 I/O 2

SPIFFY 2 I/O 3

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Table 7. GPIO Supermux Output Functions (Cont.)

Output Description

Table 7. GPIO Supermux Output Functions

Output

Description

rx_pu

External PA Control Signal

do_P# (data out of GPIO. For example: 0)

SWDIO

Serial Wire Debugger Input/

Output

kso0

Key Scan output 0

kso1

Key Scan output 1

Key Scan output 2

Key Scan output 3

Key Scan output 4

Key Scan output 5

Key Scan output 6

Key Scan output 7

Key Scan output 8

Key Scan output 9

Key Scan output 10

Key Scan output 11

Key Scan output 12

Key Scan output 13

Key Scan output 14

Key Scan output 15

Key Scan output 16

Key Scan output 17

Key Scan output 18

Key Scan output 19

PWM Channel 0

SDA2

SCL2

I2C 2 Data

kso2

I2C 2 Clock

kso3

puart_tx (uart2_tx)

puart_rts_n (uart2_rts_n)

spiffy1_CLK

Peripheral UART TX

Peripheral UART RTS

SPIFFY 1 Clock

SPIFFY 1 Chip Select

SPIFFY 1 MOSI

SPIFFY 1 MISO

SPIFFY I/O 2

kso4

kso5

spiffy1_CS

kso6

spiffy1_MOSI

spiffy1_MISO

spiffy1_IO2

kso7

kso8

kso9

spiffy1_IO3

SPIFFY I/O 3

kso10

spiffy1_INT

SPIFFY Interrupt

kso11

spiffy1_DCX

MIPI-DBI Data/Command

Indicator

kso12

kso13

spiffy2_CLK

spiffy2_CS

SPIFFY 2 Clock

SPIFFY 2 Chip Select

SPIFFY 2 MOSI

SPIFFY 2 MISO

SPIFFY 2 I/O 2

kso14

kso15

spiffy2_MOSI

spiffy2_MISO

spiffy2_IO2

spiffy2_IO3

spiffy2_INT

spiffy2_DCX

kso16

kso17

kso18

SPIFFY 2 I/O 3

kso19

SPIFFY 2 Interrupt

do_P# ^ pwm0

do_P# ^ pwm1

do_P# ^ pwm2

do_P# ^ pwm3

do_P# ^ pwm4

do_P# ^ pwm5

aclk0

MIPI-DBI Data/Command

Indicator

PWM Channel 1

PWM Channel 2

pcm_in_o

pcm_out_o

pcm_bclk_o

pcm_sync_o

i2s_ssd

PCM IN

PCM Out

PWM Channel 3

PCM Bit Clock

PWM Channel 4

PCM Sync Output

I2S Slave Serial Data

I2S Slave Word Select

I2S Slave Clock

I2S Master Serial Data

I2S Master Word Select

I2S Master Clock

PWM Channel 5

Auxiliary clock Output 0

Auxiliary clock Output 1

HID-OFF Indicator

External PA ramp

External PA Control Signal

i2s_sws

aclk1

i2s_sck

HID_OFF

pa_ramp

tx_pu

i2s_msd

i2s_mws

i2s_mck

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9. Pin/Ball Maps

9.1 40-Pin QFN Pin Map

The CYW20719 40-pin QFN package is shown in Figure 6.

Figure 6. 40-Pin QFN Pin Map

40

39

38

37

36

35

P4

34

P2

33

32

31

P10

P17

xtali_32K

LHL_VDDO

P7

P6

P16

xtalo_32K

UART_

CTS_N

P28

P29

P0

1

2

30

29

28

27

26

25

24

23

22

21

UART_

RTS_N

3

UART_TXD

UART_RXD

P1

4

CYW20719 5x5 QFN-40

P34

P38

P26

5

RSVD

6

BT_VDDO

HOST_

WAKE

7

P25

8

XTALO

P33

9

XTAL1

RST_N

10

PLLVDD1p2

SR_

VDDBAT3V

RFLDO_

VDDOOUT

RFLDO_

VDDIN

DIGLDO_

VDDIN

BT_RF

18

IFVDD1p2 VCOVDD1p2

SR_VLX

12

PAVDD

17

JTAG_SEL

11

13

14

15

16

19

20

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9.2 WLCSP Ball Map

The CYW20719 WLCSP package is shown in Figure 7.

Figure 7. WLCSP Ball Map

14

28

42

55

66

73

83

91

98

103

13

27

41

54

65

72

82

90

97

102

12

26

40

53

64

71

81

89

96

101

11

25

39

52

63

70

80

88

95

100

10

24

38

51

9

8

7

6

5

4

3

2

1

23

37

50

62

69

22

36

49

61

21

35

48

60

20

34

19

33

47

18

32

46

59

17

31

45

58

16

30

44

57

68

77

86

15

29

43

56

67

76

85

74

79

78

87

75

84

92

94

93

99

105

104

107

106

109

108

113

120

129

110

114

122

131

112

128

111

127

115

116

118

117

123

119

125

121

130

124

126

132

134

133

Notes:

■ Figure 7 shows the bottom view of the WLCSP package (Bumps facing up).

■ See Table 4 and Table 9 and for additional WLCSP information.

■ Table 9 shows the package view from the bottom (bumps facing up).

■ Coordinate origin (0, 0) is at the center of the WLCSP package with the bumps facing up.

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.

Table 8. CYW20719 WLCSP Bump Coordinates

Bump#

1

NET_NAME

X-COORD (μm)

Y-COORD (μm)

BT_VDDO

BT_VDDC

1232.28

1032.28

832.28

632.28

432.28

232.29

32.29

1356.88

1156.88

956.88

2

3

Reserved - Do not connect

Micn

4

5

ADC_avddBAT

xtali_32K

P15

6

7

8

VDDO_0

VSSO_0

VDDO_0

P20

-167.7

9

-367.7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

-567.7

-767.7

-967.69

-1167.69

-1367.69

1232.28

1032.28

832.28

632.28

432.28

232.29

32.29

VSSO_0

VDDO_0

BT_UART_CTS_N

Reserved, Connect to GND

ADC_AVSSC

Micp

Mic_avdd

xtalo_32K

Reserved

P3

-167.7

P4

-367.7

P14

-567.7

VSSO_0

VDDO_0

P22

-767.7

-967.69

-1167.69

-1367.69

1232.28

1032.28

832.28

632.28

432.28

232.29

32.29

VSSO_0

BT_VDDO

BT_VSSC

BT_UART_RTS_N

Micbias

956.88

ADC_REFGND

ADC_AVSS

xtal_avss

Reserved

P5

956.88

-167.7

956.88

-367.7

956.88

P17

-567.7

956.88

P19

-767.7

956.88

P12

-967.69

-1167.69

-1367.69

956.88

P28

956.88

VDDO_0

956.88

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Page 25 of 49

PRELIMINARY

CYW20719

Table 8. CYW20719 WLCSP Bump Coordinates (Cont.)

NET_NAME

Bump#

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

X-COORD (μm)

Y-COORD (μm)

BT_VDDC

BT_GPIO_2

BT_UART_RXD

BT_UART_TXD

Mic_avss

P16

1232.28

1032.28

832.28

632.28

432.28

32.29

756.89

556.89

356.89

322.94

156.89

-43.1

Reserved

P6

-167.7

-367.7

P18

-567.7

P9

-767.7

P21

-967.69

-1167.69

-1367.69

1232.28

1032.28

832.28

632.28

32.29

P1

P36

BT_VDDO

BT_VSSC

BT_VDDC

BT_GPIO_3

P2

Reserved

P7

-167.7

-367.7

P10

-767.7

P23

-967.69

-1167.69

-1367.69

1232.28

1032.28

-367.7

P35

VDDO_0

BT_TM1

BT_CLK_REQ

P8

P11

-767.7

P13

-967.69

-1167.69

-1367.69

401.88

1432.27

1232.28

1032.28

832.28

632.28

-767.7

VSSO_0

P31

BT_VDDC

BT_VSSC

BT_HOST_WAKE

Reserved

BT_GPIO_5

BT_GPIO_4

P29

P34

-967.69

-1167.69

-1367.69

1432.27

P39

P26

Reserved

Document Number: 002-14815 Rev. *D

Page 26 of 49

PRELIMINARY

CYW20719

Table 8. CYW20719 WLCSP Bump Coordinates (Cont.)

Bump#

85

NET_NAME

X-COORD (μm)

Y-COORD (μm)

Reserved

BT_DEV_WAKE

BT_VSSC

P37

1232.28

1032.28

832.28

-767.7

-43.1

86

87

-43.1

88

-43.1

89

P38

-967.69

-1167.69

-1367.69

1432.27

-367.7

-43.1

90

P24

-43.1

91

VDDO_0

-43.1

92

Reserved, Connect to GND

P0

-243.09

-435.87

-443.09

-597.97

-797.97

-814.63

-819

93

94

P27

-567.7

95

P30

-767.7

96

VSSO_0

-967.69

-1167.69

-1367.69

56.23

97

P25

98

P32

99

BT_VDDC

P33

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

-767.7

VSSO_0

-967.69

-1167.69

-1367.69

1462.79

1262.79

1462.79

-1059.5

-1259.5

1062.79

-659.5

JTAG_SEL

RST_N

BT_XTALO

BT_XTALI

BT_PLLVDD1p2

BT_PLLVSS

Reserved

PMU_DISABLE

BT_IFVDD1p2

RFLDO_VDDIN1P5

VSSC

-819

-849.66

-1018.99

-1035.5

-1087.29

-1128.6

-1212.28

-1218.99

-1153.5

-1328.59

-1412.28

-1418.99

-859.5

PMU_AVSS

BT_IFVSS

BT_PAVDD

BT_VSSC

BT_VCOVSS

VDDBAT3V

SR_VLX

-1059.5

-1459.49

1159.51

756.99

-234

-433.99

1472.59

-1059.5

-1259.5

-1459.49

994.94

-34

Reserved

BT_PAVSS

BT_VSSC

BT_VCOVDD1p2

DIGLDO_VDDOUT

1472.59

-459.5

Document Number: 002-14815 Rev. *D

Page 27 of 49

PRELIMINARY

CYW20719

Table 8. CYW20719 WLCSP Bump Coordinates (Cont.)

Bump#

127

NET_NAME

DIGLDO_VDDIN1P5

X-COORD (μm)

Y-COORD (μm)

-659.5

-859.5

-1418.99

-1475

128

RFLDO_VDDOUT

SR_VDDBAT3V

SR_PVSS

129

-1059.5

-1259.5

-1459.49

988.31

365.99

165.99

130

131

Reserved

132

BT_RF

133

BT_VSSC

-1479.96

134

BT_VSSC

Document Number: 002-14815 Rev. *D

Page 28 of 49

PRELIMINARY

CYW20719

10. Specifications

10.1 Electrical Characteristics

Caution! The absolute maximum ratings in the following table indicate levels where permanent damage to the device can occur, even

if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at

absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.

Table 9. Absolute Maximum Ratings

Requirement Parameter

Maximum Junction Temperature

Specification

Unit

Min.

–

Nom.

Max.

125

–

°C

V

VDD IO (BT_VDDO, VDDO_0)

–0.5

3.795

1.38

VDD RF (BT_IFVDD1p2, BT_PLLVDD1p2,

BT_VCOVDD1p2, BT_PAVDD)

V

VDDBAT3V/SR_VDDBAT3V

DIGLDO_VDDIN1P5

RFLDO_VDDIN1P5

MIC_AVDD

–0.5

–

3.795

1.65

V

1.50

3.795

Table 10. ESD/Latch up

Requirement Parameter

Specification

Unit

Min.

–2000

–500

–

Nom.

–

Max.

2000

500

–

ESD Tolerance HBM

ESD Tolerance CDM

Latch up

V

–

200

mA

Table 11. Environmental Ratings

Characteristic

Operating Temperature

Value

Units

°C

–30 to +85

Storage Temperature

–40 to +150

°C

Note:

Lowest operating temperature for the 32 KHz xtal is -10°C

Table 12. Recommended Operating Conditions

Parameter

Specification

Unit

Min.

1.76

1.9

Typ.

3.0

Max.

3.63

VDDIO (BT_VDDO, VDDO_0)

VDDBAT3V^a/SR_VDDBAT3V^a

MIC_AVDD

V

3.0

1.76

3.0

a. Supply tolerance for VDDBAT3V and SR_VDDBAT3V must be 2% or less.

Document Number: 002-14815 Rev. *D

Page 29 of 49

PRELIMINARY

CYW20719

The CYW20719 uses an on board low voltage detector to shut down the part when supply voltage (VDDBAT3V) drops below operating

range.

Table 13. Shutdown Voltage

Specification

Parameter

Unit

Min.

Typ.

Max.

V_SHUT

1.625

1.7

1.76

V

10.1.1 Core Buck Regulator

Table 14. Core Buck Regulator

Parameter

Input supply voltage DC, VBAT

CBUCK output current

Conditions

Min.

1.9

–

Typ.

3.0

–

Max.

3.63

65

Unit

V

DC voltage range inclusive of disturbances

Low Power Operation Mode (LPOM) only

mA

V

Output voltage range

Programmable, 30mV/step

default = 1.2 V (bits = 0000)

1.2

1.26

1.5

Output voltage DC accuracy

Includes load and line regulation

–4

–

+4

%

LPOM efficiency (high load)

LPOM efficiency (low load)

–

85

80

–

%

–

Input supply voltage ramp-up time

0 to 3.3 V

40

μs

■ Minimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature,

and aging.

■ Maximum capacitor value refers to the total capacitance seen at a node where the capacitor is connected. This also includes any

decoupling capacitors connected at the load side, if any.

10.1.2 Recommended External Component for Core Buck Regulator

Table 15. Recommended External Component for Core Buck Regulator

Parameter

Conditions

Min.

Typ.

Max.

Unit

External output inductor L

2.2 μH ±25%, DCR=114 mΩ ±20%, ACR<1Ω

(for frequency<1 MHz)

–

2.2

–

μH

External output capacitor, Cout

External input capacitor, Cin

4.7 μF ±10%, 6.3V, 0402 inch, X5R, MLCC

capacitor +board total-ESR < 20 mΩ

–

4.7

10

–

μF

For SR_VDDBAT pin

Ceramic, X5R, 0402, ESR<30 mΩ at

4 MHz, +/-20%, 6.3V, 10 μF

10.1.3 Recommended External Components for RFLDO

Table 16. Recommended External Components for RFLDO

Parameter

Conditions

Total ESR (trace/cap): 5 m–240 mΩ

Min.

Typ.

Max.

Unit

External output capacitor, Co

0.5

2.2

4.7

μF

Document Number: 002-14815 Rev. *D

Page 30 of 49

PRELIMINARY

CYW20719

10.1.4 Digital I/O Characteristics

Table 17. Digital I/O Characteristics

Characteristics

Input low voltage (VDDO = 3 V)

Input high voltage (VDDO = 3 V)

Input low voltage (VDDO = 1.8 V)

Input high voltage (VDDO = 1.8 V)

Output low voltage

Symbol

V_IL

Minimum

Typical

Maximum

Unit

V

–

0.8

–

V_IH

V_IL

2.4

V

–

0.4

–

V

V_IH

V_OL

V_OH

I_IL

1.4

V

–

0.45

–

V

Output high voltage

VDDO – 0.45 V

V

Input low current

–

1.0

0.4

8.0

4.0

8.0

4.0

μA

pF

mA

Input high current

I_IH

Input capacitance

C_IN

I_OL

Output low current (VDDO = 3 V, V_OL= 0.5 V)

Output low current (VDDO = 1.8 V, V_OL= 0.5 V)

Output high current (VDDO = 3 V, V_OH= 2.55 V)

Output high current (VDDO = 1.8 V, V_OH= 1.35 V)

I_OL

I_OH

10.1.5 ADC Electrical Characteristics

Table 18. Electrical Characteristics

Parameter

Current consumption

Power down current

ADC Core Specification

ADC reference voltage

ADC sampling clock

Absolute error

Symbol

I_TOT

–

Conditions/Comments

Min.

Typ.

Max.

Unit

–

2

1

3

–

mA

μA

At room temperature

VREF

From BG with ±3% accuracy

–

0.85

12

–

5

V

MHz

%

–

Includes gain error, offset and

distortion. Without factory calibration.

Includes gain error, offset and

distortion. After factory calibration.

–

2

%

ENOB

–

For audio application

For static measurement

For audio application

For static measurement

For audio application

For static measurement

For audio application

For static measurement

For audio application

For static measurement

12

10

–

13

–

Bit

ADC input full scale

FS

1.6

–

1.8

8

3.6

–

Conversion rate

Signal bandwidth

–

16

–

kHz

Hz

20

–

8K

–

DC

–

Input impedance

Startup time

R_IN

–

10

500

–

KΩ

–

10

20

–

ms

μs

–

MIC PGA Specifications

MIC PGA gain range

MIC PGA gain step

–

0

–

1

–

42

–

dB

μV

–

PGA input referred noise

At 42 dB PGA gain A-weighted

4

Document Number: 002-14815 Rev. *D

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PRELIMINARY

CYW20719

Table 18. Electrical Characteristics (Cont.)

Parameter

MIC Bias Specifications

MIC bias output voltage

MIC bias loading current

MIC bias noise

Symbol

Conditions/Comments

Min.

Typ.

Max.

Unit

–

At 3 V supply, 25°C, default settings

–

2.4

–

3

V

mA

μV

Refers to PGA input 20 Hz to

8 kHz, A-weighted

–

MIC bias PSRR

ADC SNR

–

at 1 kHz

40

–

dB

A-weighted 0 dB PGA gain,

Temperature= 25°C

78

ADC THD + N

–

–3 dBFS input 0 dB PGA gain,

Temperature= 25°C

–

70

–

dB

GPIO input voltage

GPIO source impedance^a

Always lower than avddBAT

Resistance

–

3.6

1

V

–

kΩ

pF

Capacitance

10

a. Conditional requirement for the measurement time of 10 μs. Relaxed with longer measurement time for each GPIO input channel.

10.1.6 Current Consumption

In Table 19, current consumption measurements are taken at input of VBAT and VDDIO combined (LDOIN = VDDIO = 3.0V).

Table 19. Current Consumption BT/LE

Operational Mode

Conditions

Typical

1.1

Unit

mA

uA

HCI

48 MHz with Pause

48 MHz Without Pause

Continuous RX

2.2

RX

5.9

TX

Continuous TX - 0 dBm

5.6

PDS

61

HID-Off

32 KHz XTAL and 16 KB Retention RAM on

Unconnectable - 1 sec

1.6

uA

Advertising

14

uA

Connectable undirected - 1 sec

Master - 1 sec

17

uA

LE Connection - SDS

TBD

122

132

138

6.9

uA

Slave - 1 sec

uA

Page Scan - PDS

Sniff - PDS

Interlaced - R1

uA

500 ms Sniff, 1 attempt, 0 timeout - Master

500 ms Sniff, 1 attempt, 0 timeout - Slave

uA

Bi-Directional Data Exchange Continuous DM5 or DH5 packets - Master/Slave

mA

Document Number: 002-14815 Rev. *D

Page 32 of 49

PRELIMINARY

CYW20719

10.2 RF Specifications

Note: Table 20 and Table 21 apply to single-ended industrial temperatures. Unused inputs are left open.

Table 20. Receiver RF Specifications

Parameter

Frequency range

RX sensitivity (QFN)^a

Mode and Conditions

–

Min

Typ

–

Max

Unit

MHz

dBm

2402

2480

GFSK, 0.1% BER, 1 Mbps

π/4-DQPSK, 0.01% BER, 2 Mbps

8-DPSK, 0.01% BER, 3 Mbps

GFSK, 0.1% BER, 1 Mbps

π/4-DQPSK, 0.01% BER, 2 Mbps

8-DPSK, 0.01% BER, 3 Mbps

All data rates

–

–92.0^b

–94.0^b

–88.0^b

–91.5^b

–93.5^b

–87.5^b

–

RX sensitivity (WLCSP)^a

–

Maximum input

–20

GFSK Modulation

C/I cochannel

GFSK, 0.1% BER^c

GFSK, 0.1% BER^d

GFSK, 0.1% BER^c

GFSK, 0.1% BER^e

GFSK, 0.1% BER^c

–

11.0

0

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

C/I 3 MHz adjacent channel

C/I image channel

–30.0

–40.0

–9.0

–20.0

C/I 1 MHz adjacent to image channel GFSK, 0.1% BER^c

QPSK Modulation

C/I cochannel

p/4-DQPSK, 0.1% BER^c

p/4-DQPSK, 0.1% BER^d

p/4-DQPSK, 0.1% BER^c

p/4-DQPSK, 0.1% BER^e

p/4-DQPSK, 0.1% BER^c

–

13.0

0

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

C/I 3 MHz adjacent channel

C/I image channel

–30.0

–40.0

–9.0

–20.0

C/I 1 MHz adjacent to image channel p/4-DQPSK, 0.1% BER^c

8PSK Modulation

C/I cochannel

8-DPSK, 0.1% BER^c

8-DPSK, 0.1% BER^e

8-DPSK, 0.1% BER^c

–

21.0

5.0

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

C/I 3 MHz adjacent channel

C/I image channel

–25.0

–33.0

0

C/I 1 MHz adjacent to image channel 8-DPSK, 0.1% BER^c

13

Out-of-Band Blocking Performance (CW)^d

30 MHz to 2000 MHz

2000 MHz to 2399 MHz

2498 MHz to 3000 MHz

3000 MHz to 12.75 GHz

Inter-modulation Performance^f

BT, interferer signal level

Spurious Emissions

BDR GFSK 0.1% BER

–

–10.0

–27.0

–10.0

–

dBm

BDR GFSK 0.1% BER

–

–39.0

dBm

30 MHz to 1 GHz

–

–57.0

–55.0

dBm

1 GHz to 12.75 GHz

a. Dirty TX is off

b. Up to 1dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations

Document Number: 002-14815 Rev. *D

Page 33 of 49

PRELIMINARY

CYW20719

c. The receiver sensitivity is measured at BER of 0.1% on the device interface.

d. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).

e. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).

f. Desired signal is -64 dBm Bluetooth-modulated signal, interferer 1 is –39 dBm sine wave at frequency f1, interferer 2 is –39 dBm Bluetooth modulated signal at

frequency f2, f0 = 2*f1 – f2, and |f2 – f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4.

Table 21. Transmitter RF Specifications

Parameter

Min

Typ

Max

Unit

Transmitter Section

Frequency range

2402

–

4.0

0

2480

–

MHz

dBm

kHz

Class 2: GFSK TX power

Class2: EDR TX Power

20 dB bandwidth

–

930

1000

Adjacent Channel Power

|M – N| = 2

–

–20

–40

dBm

|M – N| 3

Out-of-Band Spurious Emission

30 MHz to 1 GHz

–

–36.0

–30.0

–47.0

dBm

1 GHz to 12.75 GHz

1.8 GHz to 1.9 GHz

5.15 GHz to 5.3 GHz

LO Performance

Initial carrier frequency tolerance

Frequency Drift

–75

–

+75

kHz

DH1 packet

–25

–40

–20

–

+25

+40

20

kHz

DH3 packet

DH5 packet

kHz

Drift rate

kHz/50 µs

Frequency Deviation

Average deviation in payload (sequence used is 00001111)

Maximum deviation in payload (sequence used is 10101010)

Channel spacing

140

115

–

1

175

–

kHz

MHz

–

Modulation Accuracy

p/4-DQPSK Frequency Stability

p/4-DQPSK RMS DEVM

p/4-QPSK Peak DEVM

p/4-DQPSK 99% DEVM

8-DPSK frequency stability

8-DPSK RMS DEVM

–10

–

10

20

35

30

10

13

25

20

kHz

%

–

%

–

%

–10

–

kHz

%

8-DPSK Peak DEVM

–

%

8-DPSK 99% DEVM

–

%

In-Band Spurious Emissions

1.0 MHz < |M – N| < 1.5 MHz

1.5 MHz < |M – N| < 2.5 MHz

|M – N| > 2.5 MHz

–

–26

–20

–40

dBc

dBm

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PRELIMINARY

CYW20719

Table 22. BLE RF Specifications

Parameter

Conditions

Minimum

Typical

–

–95.0^b

–94.5^b

4.0

Maximum

Unit

MHz

dBm

kHz

%

Frequency range

RX sensitivity (QFN)^a

RX sensitivity (WLCSP)^a

TX power

N/A

2402

–

2480

LE GFSK, 0.1% BER, 1 Mbps

N/A

–

Mod Char: Delta F1 average N/A

225

99.9

0.8

255

275

–

Mod Char: Delta F2 max^c

N/A

–

Mod Char: Ratio

0.95

–

%

a. Dirty Tx is Off

b. Up to 1dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations

c. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.

Table 23. BLE2M RF Specifications

Parameter

Frequency Range

RX Sensitivity^a

Condition

Min.

2402

-

Typ.

Max.

Unit

MHz

dBm

KHz

N/A

2480

255 Packets

N/A

-90.5

-

TX Power

-

4

Mod Char: Delta F1 average

Mod Char: Delta F2 max

Mod Char: Ratio

Frequency Drift

N/A

450

370

0.8

-50

-20

500

550

-

N/A

-

KHz

N/A

-

%

N/A

50

20

KHz

Drift Rate

N/A

KHz/50μs

a. Dirty TX is OFF.

Table 24. CYW20719 GPS and GLONASS Band Spurious Emission

Parameter Condition

1570-1580 MHz

1592-1610 MHz

Min.

Typ.

–160

–159

Max.

Unit

GPS

–

dBm/Hz

GLONASS

Document Number: 002-14815 Rev. *D

Page 35 of 49

PRELIMINARY

CYW20719

10.3 Timing and AC Characteristics

In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.

10.3.1 UART Timing

Table 25. UART Timing Specifications

Reference

Characteristics

Min.

Typ.

Max.

1.50

0.67

1.33

Unit

1

2

3

Delay time, UART_CTS_N low to UART_TXD valid

Setup time, UART_CTS_N high before midpoint of stop bit

Delay time, midpoint of stop bit to UART_RTS_N HIGH

–

Bit periods

Figure 8. UART Timing

UART_CTS_N

2

1

UART_TXD

M idpoint of STOP bit

UART_RXD

3

UART_RTS_N

Document Number: 002-14815 Rev. *D

Page 36 of 49

PRELIMINARY

CYW20719

10.3.2 SPI Timing

The SPI interface can be clocked up to 24 MHz.

Table 26 and Figure 9 show the timing requirements when operating in SPI Mode 0 and 2.

Table 26. SPI Mode 0 and 2

Reference

Characteristics

Time from master assert SPI_CSN to first clock edge

Hold time for MOSI data lines

Min.

45

Max.

Unit

ns

1

2

3

4

5

–

½ SCK

100

–

12

ns

Time from last sample on MOSI/MISO to slave deassert SPI_INT

Time from slave deassert SPI_INT to master deassert SPI_CSN

Idle time between subsequent SPI transactions

0

ns

0

ns

1 SCK

–

ns

Figure 9. SPI Timing, Mode 0 and 2

5

SPI_CSN

SPI_INT

(DirectWrite)

SPI_INT

(DirectRead)

1

SPI_CLK

(Mode 0)

SPI_CLK

(Mode 2)

2

First Bit

Second Bit

Last bit

SPI_MOSI

SPI_MISO

First Bit

Not Driven

Table 27 and Figure 10 show the timing requirements when operating in SPI Mode 0 and 2.

Table 27. SPI Mode 1 and 3

Reference

Characteristics

Time from master assert SPI_CSN to first clock edge

Hold time for MOSI data lines

Min.

45

Max.

Unit

ns

1

2

3

4

5

–

½ SCK

100

–

12

ns

Time from last sample on MOSI/MISO to slave deassert SPI_INT

Time from slave deassert SPI_INT to master deassert SPI_CSN

Idle time between subsequent SPI transactions

0

ns

0

ns

1 SCK

–

ns

Document Number: 002-14815 Rev. *D

Page 37 of 49

PRELIMINARY

CYW20719

Figure 10. SPI Timing, Mode 1 and 3

SPI_CSN

5

SPI_INT

(DirectWrite)

4

3

SPI_INT

(DirectRead)

SPI_CLK

(Mode 1)

1

SPI_CLK

(Mode 3)

2

Invalid bit

First bit

Last bit

SPI_MOSI

SPI_MISO

Not Driven

First bit

Document Number: 002-14815 Rev. *D

Page 38 of 49

PRELIMINARY

CYW20719

10.3.3 I²C Compatible Interface Timing

The specifications in Table 28 references Figure 11.

Table 28. I²C Compatible Interface Timing Specifications (up to 1 MHz)

Reference

Characteristics

Minimum

Maximum

Unit

1

Clock frequency

–

100

400

800

1000

–

kHz

2

3

START condition setup time

START condition hold time

Clock low time

650

280

650

280

0

ns

–

4

–

5

Clock high time

–

6

Data input hold time^a

Data input setup time

STOP condition setup time

Output valid from clock

Bus free time^b

–

7

100

280

–

8

–

9

400

–

10

650

a. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

b. Time that the CBUS must be free before a new transaction can start.

Figure 11. I²C Interface Timing Diagram

1

5

SCL

2

8

6

4

3

7

SDA

IN

10

9

SDA

OUT

Document Number: 002-14815 Rev. *D

Page 39 of 49

PRELIMINARY

CYW20719

Table 29. Timing for I²S Transmitters and Receivers

Transmitter

Lower LImit Upper Limit

Min Max Min Max

T_tr

Master Mode: Clock generated by transmitter or receiver

Receiver

Lower Limit Upper Limit

Min Max

T_r

Notes

Min

Max

a

Clock Period T

–

b

HIGH t_HC

LOWt_LC

0.35T_tr

–

0.35T_tr

–

Slave Mode: Clock accepted by transmitter or receiver

c

d

HIGH t_HC

–

0.35T_tr

–

0.35T_tr

–

LOW t_LC

Rise time t_RC

0.15T_tr

Transmitter

e

d

Delay t_dtr

–

0

–

0.8T

–

Hold time t_htr

Receiver

f

Setup time t_sr

–

0.2T_tr

–

Hold time t_hr

a. The system clock period T must be greater than T and T because both the transmitter and receiver have to be able to handle the data transfer rate.

tr

r

b. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, t and t are specified with

HC

LC

respect to T.

c. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum

periods are greater than 0.35T , any clock that meets the requirements can be used.

r

d. Because the delay (t ) and the maximum transmitter speed (defined by T ) are related, a fast transmitter driven by a slow clock edge can result in t not exceeding

dtr

tr

dtr

t

which means t becomes zero or negative. Therefore, the transmitter has to guarantee that t is greater than or equal to zero, so long as the clock rise-time

RC

h

t

r

h

t

r

is not more than t

, where t

is not less than 0.15T

RCmax

RCmax tr

e. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient

setup time.

f. The data setup and hold time must not be less than the specified receiver setup and hold time.

Document Number: 002-14815 Rev. *D

Page 40 of 49

PRELIMINARY

CYW20719

Figure 12. I²S Transmitter Timing

T

t_RC*

t_LC> 0.35T

t_HC> 0.35T

V_H= 2.0V

V_L= 0.8V

SCK

t_htr> 0

t_otr< 0.8T

SD and WS

T = Clock period

T_tr= Minimum allowed clock period for transmitter

T = T_tr

* t_RCis only relevant for transmitters in slave mode.

Figure 13. I²S Receiver Timing

T

t_LC> 0.35T

t_HC> 0.35

V_H= 2.0V

V_L= 0.8V

SCK

t_sr> 0.2T

t_hr> 0

SD and WS

T = Clock period

T_r= Minimum allowed clock period for transmitter

T > T_r

Document Number: 002-14815 Rev. *D

Page 41 of 49

PRELIMINARY

CYW20719

11. Mechanical Information

11.1 40-Pin QFN Package

Figure 14. CYW20719 5.0 mm x 5.0 mm 40-Pin QFN Package

Document Number: 002-14815 Rev. *D

Page 42 of 49

PRELIMINARY

CYW20719

11.2 WLCSP Package

Figure 15. CYW20719 WLCSP Package

NOTES:

DIMENSIONS

SYMBOL

1. ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y14.5M-1994.

NOTES: UNLESS OTHERWISE SPECIFIED

2. BUMP POSITION DESIGNATION PER JESD 95-1, SPP-010

3. REFER TO CYPRESS APPLICATION NOTE "WAFER-SCALE CHIP-SIZED

PACKAGE (WSCSP) OVERVIEW AND ASSEMBLY GUIDELINES FOR DESIGN,

IMPLEMENTATION, AND MANUFACTURING RECOMMENDATIONS AND GUIDELINES.

4. MINIMUM BUMP PITCH IS 0.200MM

MIN.

NOM.

MAX.

0.33

A

-

0.075

3.270

-

0.090

3.310

0.105

3.350

3.260

A1

D

E

3.180

3.220

2.84 BSC

2.83 BSC

134

DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER,

5

D1

E1

N

PARALLEL TO PRIMARY DATUM Z.

PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY

6

THE SPHERICAL CROWNS OF THE SOLDER BALLS.

0.100

0.115

0.130

b

Document Number: 002-14815 Rev. *D

Page 43 of 49

PRELIMINARY

CYW20719

11.3 WLCSP Package Keep-out

Figure 16. CYW20719YB1 WLCSP Keep-out Model

3310.0000

1

2

3

4

5

6

7

8

9 10 11 12 13 14

15 16 17 18 19 20 21 22 23 24 25 26 27 28

29 30 31 32 33 34 35 36 37 38 39 40 41 42

43 44 45 46 47

56 57 58 59

48 49 50 51 52 53 54 55

60 61 62

69

63 64 65 66

70 71 72 73

80 81 82 83

88 89 90 91

67 68

75 76 77 78 79

84 85 86 87

92

74

3220.0000

93 94 95 96 97 98

100101102103

99

104105

106

107

108109

110

115

Bump Origin

111112113

114

120121122

126127128129130131

116

117118

123

119

125

124

132

133134

Routing Keep-Out

Note: Figure 16 shows the top view of the WLCSP package (Bumps facing down).

11.4 Tape Reel and Packaging Specifications

Table 30. CYW20719 Tape Reel Specifications

Parameter

Quantity per reel

Reel diameter

Value

5000

13 inches

4 inches

12 mm

8 mm

Hub diameter

Tape width

Tape pitch

The top-left corner of the CYW20719 package is situated near the sprocket holes, as shown in Figure 17.

Figure 17. Pin 1 Orientation

Pin 1: Top left corner of package toward sprocket holes

Document Number: 002-14815 Rev. *D

Page 44 of 49

PRELIMINARY

CYW20719

12. Ordering Information

Table 31. Ordering Information

Part Number

CYW20719B1KWB9G

CYW20719B1KUMLG

Package

Ambient Operating Temperature

3.2 x 3.1 134-Ball WLCSP

5x5 40-pin QFN

-30°C to 85°C

13. Additional Information

13.1 Acronyms and Abbreviations

The following list of acronyms and abbreviations may appear in this document.

Term

Description

Term

Description

adaptive frequency hopping

Attribute Protocol

PBF

PDM

PDS

PLL

packet boundary flag

AFH

ATT

BBC

BDR

BLE

BR

pulse density modulation

Power down sleep

Bluetooth Baseband Core

basic data rate

phase locked loop

PMU

POR

power management unit

power-on reset

Bluetooth low energy

basic data rate

PRBS

PWM

Pseudo Random Binary Sequence

pulse width modulation

quad flat no-lead

BQS

CRC

ED

Bluetooth Qualification Body

cyclic redundancy check

erroneous data

QFN

QoS

quality of service

EIR

extended inquiry response

encryption pause resume

forward error correction

floating point unit

RAM

random access memory

EPR

FEC

FPU

RC oscillator

A resistor-capacitor oscillator is a circuit

composed of an amplifier, which provides

the output signal, and a resistor-capacitor

network, which controls the frequency of

the signal.

GATT

GAP

GFSK

GPIO

HCI

Generic Attribute Profile

generic access profile

Gaussian Frequency Shift Keying

general-purpose I/O

RF

radio frequency

ROM

RX/TX

SCO

SDP

SDS

SPI

read-only memory

receive/transmit

host control interface

intermediate frequency

Joint Test Action Group

synchronous connection-oriented

Service Discovery Protocol

Shut Down Sleep

IF

JTAG

L2CAP

Logical Link Control and Adaptation

Protocol

serial peripheral interface

serial peripheral interface fully functional

secure simple pairing

sniff subrating

SPIFFY

SSP

LCU

LDO

LE

link control unit

low drop-out

SSR

SWD

TSSI

UART

low energy

serial wire debug

LM

Link Manager

transmit signal strength indicator

LO

local oscillator

universal asynchronous receiver/trans-

mitter

LPO

LSTO

PA

low power oscillator

link supervision time out

power amplifier

WLCSP

wafer level chip scale package

Document Number: 002-14815 Rev. *D

Page 45 of 49

PRELIMINARY

CYW20719

Document History Page

Document Title: CYW20719 Enhanced Low Power, BR/EDR/BLE Bluetooth 5.0 SOC

Document Number: 002-14815

Orig. of Submission

Revision

ECN

Description of Change

Change

Date

**

–

UTSV

05/03/2016

20719-DS100-R

Initial release

*A

*B

5441953

5889849

UTSV

MILI

10/05/2016

09/28/2017

Updated to Cypress template

Added Cypress part numbering scheme

Added 134-Ball WLCSP in “Features” on page 2.

Added VBAT* in the Figure 2 on page 7.

Added “The Bypass LDO is activated when the VBAT input voltage falls below

2.1V” in the Section “Power Management Unit” on page 8.

Removed Figure 3. Power Management Unit.

Updated the title and Figure 4 from Usage Mode 1: RF Powered from LDO

(Default) to “Default usage Mode” on page 8.

Removed ZA_STRAP, and ZINC_air_strap from Figure 2 on page 8.

Removed 1.4.2. Usage Mode 2 and 1.4.3. Usage Mode 3.

Changed the title “1.6.1 Cypress Serial Communication Interface” to “I2C

Compatible Master” on page 10.

Replaced BSC to I²C in the datasheet.

Removed second para from the section “UART Interface” on page 10 and

added “The Firmware's UART driver allows applications to select different

baud rates”.

Removed “Table: Common Baud Rate Examples” and the corresponding

sentences from the section “UART Interface” on page 10.

Updated Figure 2: Replaced 22pF with CL1 and 20pF with CL2.

Updated Table 3 on page 11.

Removed 1.9.2 HID Peripheral Block

Added “Those pins include PWM functionality which can be used for LED

dimming” in the section GPIO Ports on page 12 and also the “Note: On the

double and triple bonded pins, only one of the GPIO can be used at a given

time. When a certain GPIO is selected, the other GPIOs bonded to the same

pin must be configured to input and output disable”.

Replaced “PAVDD2P5” to “PAVDD” throughout the document.

Added “The 20719 includes one double-axis and one single axis quadrature

decoders. There are two input lines for each axis and a programmable control

signal that can be active high or low.

The application can access the quadrature interface via the driver included in

the firmware.” in the Mouse Quadrature Signal Decoder on page 13.

Removed 1.17 Infrared Modulator and 1.18 Infrared Learning.

Added Table 7 on page 25 and Table 8 on page 28.

Updated the title to “Enhanced Low Power Bluetooth 5.0/BLE/2 Mbps

LE/EDR/Integrated SOC”.

Updated Table 12 on page 33 and Table 13 on page 34.

Removed Table: Cypress Part Numbering Scheme from Page 1.

Document Number: 002-14815 Rev.*D

Page 46 of 49

PRELIMINARY

CYW20719

Document History Page

Document Title: CYW20719 Enhanced Low Power, BR/EDR/BLE Bluetooth 5.0 SOC

Document Number: 002-14815

Orig. of Submission

Revision

ECN

Description of Change

Updated Figure 1 and Figure 2.

Change

Date

*C

6075109

SGUP

03/09/2018

Added Features and Applications section.

Created a table for Bluetooth Features.

Updated with “The CYW20719 includes a Cortex M4 processor with 2 Mbyte

of program ROM, 448 KB of data RAM, 64 KB of patch RAM, and 1 Mbyte of

on-chip flash. The M4 has a maximum speed of 96 MHz. The 1 Mbyte of flash

is supported by an 8KB cache allowing direct code execution from flash at

near maximum speed and low power consumption. The CM4 also includes a

single precision IEEE 754 compliant floating point unit (FPU).The CM4 runs

all the BT layers as well as application code. The ROM includes LM, HCI,

L2CAP, GATT, as well as other stack layers freeing up the flash for

application usage. A standard serial wire debug (SWD) interface provides

debugging support.” in MCU.

Changed the title I2C to I2C Compatible Master and UART Interface to HCI

UART Interface.

Updated Table 2, Table 4, Table 9, Table 12, Table 14, Table 17, Table 16,

Table 17, Table 20, Table 21 and Table 22.

Updated GPIO Ports, ADC, PWM, Serial Peripheral Interface block.

Created Table 6 and Table 7.

Added the terms BQS, PRBS and SPIFFY to Acronyms and Abbreviations

table.

Removed all references of “LHL”.

Added Table 18 in the ADC Electrical Characteristics section.

Replaced “CSC” as “I2C” throughout the document.

Table 20 and Table 22: Updated footnote “Up to 1dB of variation is expected

from typical sensitivity specs due to the chip and board variation”.

Added ADC Electrical Characteristics.

Added Random Number Generator section.

Updated Power Modes section.

Table 5: Removed the description “Quadrature, Peripheral UART, SPI_1,

I2C, Keyboard Scan output and External T/R switch control”.

Removed Figure: Reset Timing.

Added “I2C1 is Master Only; I2C2 is Master/Slave. The Slave support is

subject to driver support in WICED Studio” to I2C Compatible Master section.

Added “P15 is Bonded to the same pin as XTALI_32K on the QFN package

(Pin 32). If External 32.768KHz crystal is not used, then this pin can be used

as GPIO P15” to GPIO Ports section.

Table 3: Added “External AC Input Amplitude” Parameter.

Removed tables: Digital LDO and RF LDO.

Table 17: Added UART_TXD VOL and UART_TXD VOH characteristics.

Table 18: Removed “Analog supply Voltage”, “Analog core supply” and

“Audio supply” Parameters.

Document Number: 002-14815 Rev.*D

Page 47 of 49

PRELIMINARY

CYW20719

Document History Page

Document Title: CYW20719 Enhanced Low Power, BR/EDR/BLE Bluetooth 5.0 SOC

Document Number: 002-14815

Orig. of Submission

Revision

ECN

Description of Change

Change

Date

*D

6222848

MILI

07/12/2018

Table 4: Updated QFN-40 value as 26 for the Reserved Pin and removed the

QFN value for BT_VDDO and added a row for “Reserved, Connect to GND”.

Table 8: Updated “VSSO_0” to “Reserved, Connect to GND” and added a row

for “ BT_VSSC”.

Figure 6: Changed BT_VDDC to RSVD.

Updated Table 7, Table 14 and Table 18.

Added a Table 23.BLE2M RF Specifications on page 35.

Figure 1: Removed “Programmable wait states”.

Table 11: Added note “Lowest operating temperature for the 32 KHz xtal is

-10°C.

Updated I2S Interface and PCM Interface sections.

Updated Acronyms and Abbreviations section.

Document Number: 002-14815 Rev.*D

Page 48 of 49

PRELIMINARY

CYW20719

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

Arm^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Technical Support

Internet of Things

Memory

cypress.com/support

cypress.com/memory

cypress.com/mcu

Microcontrollers

PSoC

cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/wireless

49

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

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modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

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such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product

to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any

liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming

code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this

information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons

systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances

management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device

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shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from

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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number 002-14815 Rev. *D

Revised July 12, 2018

Page 49 of 49

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