8T73S208 Datasheet
Function Tables
acknowledge or Not-Acknowledge bit and the stop bit. These
Input Frequency Divider Operation
elements are arranged to make up the complete I2C transactions as
shown in Figure 2 and Figure 3. Figure 2 is a write transaction while
Figure 3 is read transaction. The 7-bit I2C slave address of the
8T73S208 is a combination of a 4-bit fixed addresses and two
variable bits which are set by the hardware pins ADR[1:0] (binary
11010, ADR1, ADR0). Bit 0 of slave address is used by the bus
controller to select either the read or write mode. The hardware pins
ADR1 and ADR0 and should be individually set by the user to avoid
address conflicts of multiple 8T73S208 devices on the same bus.
The FSEL1 and FSEL0 control pins configure the input frequency
divider. In the default state (FSEL[1:0] are set to logic 0:0 or left open)
the output frequency is equal to the input frequency (divide-by-1).
The other FSEL[1:0] settings configure the input divider to
divide-by-2, 4 or 8, respectively.
Table 3A. FSEL[1:0] Input Selection Function Table
Input
FSEL1
FSEL0
Operation
fQ[7:0] = fREF ÷ 1
fQ[7:0] = fREF ÷ 2
Q[7:0] = fREF ÷ 4
fQ[7:0] = fREF ÷ 8
Table 3D. I2C Slave Address
0 (default)
0 (default)
7
1
6
1
5
0
4
1
3
0
2
1
0
0
1
1
1
0
1
ADR1 ADR0 R/W
f
SCL
NOTE: FSEL1, FSEL0 are asynchronous controls
Output Enable Operation
The output enable/disable state of each individual differential output
Qx, nQx can be set by the content of the I2C register (see Table 3C).
A logic zero to an I2C bit in register 0 enables the corresponding
differential output, while a logic one disables the differential output
(see Table 3B). After each power cycle, the device resets all I2C bits
(Dn) to its default state (logic 0) and all Qx, nQx outputs are enabled.
After the first valid I2C write, the output enable state is controlled by
the I2C register. Setting and changing the output enable state through
the I2C interface is asynchronous to the input reference clock.
SDA
START
Valid Data
Acknowledge
STOP
Figure 1: Standard I2C Transaction
START (S) – defined as high-to-low transition on SDA while holding
SCL HIGH.
DATA – between START and STOP cycles, SDA is synchronous with
SCL. Data may change only when SCL is LOW and must be stable
when SCL is HIGH.
The device supports the enable/disable of individual outputs.
During an active operation of the device, enabling individual
previously disabled outputs may degrade signal integrity of already
enabled active outputs during the enabling transition. Disabling
multiple outputs is supported without signal integrity constraints.
ACKNOWLEDGE (A) – SDA is driven LOW before the SCL rising
edge and held LOW until the SCL falling edge.
Table 3B. Individual Output Enable Control
STOP (S) – defined as low-to-high transition on SDA while holding
SCL HIGH
Bit
Dn
Operation
Output Qx, nQx is enabled.
0 (default)
S
DevAdd W A Data Byte
A P
Output Qx, nQx is disabled in high-impedance
state.
Figure 2: Write Transaction
1
Table 3C. Individual output enable control
S
DevAdd R A
Data Byte
A P
Bit
D7
Q7
0
D6
Q6
0
D5
Q5
0
D4
Q4
0
D3
Q3
0
D2
Q2
0
D1
Q1
0
D0
Q0
0
Figure 3: Read Transaction
Output
Default
S –
Start or Repeated Start
W –
R/~W is set for Write
R/~W is set for Read
Ack
I2C Interface Protocol
R –
The IDT8T73S208I uses an I2C slave interface for writing and
reading the device configuration to and from the on-chip
configuration registers. This device uses the standard I2C write
A –
DevAdd –
P –
7 bit Device Address
Stop
format for a write transaction, and a standard I2C read format for a
read transaction. Figure 1 defines the I2C elements of the standard
I2C transaction. These elements consist of a start bit, data bytes, an
©2016 Integrated Device Technology, Inc.
3
Revision D, June 15, 2016
