CYW20730,PDF,CYW20730 PDF资料,Datasheet,下载CYW20730技术资料



CYW20730

Single-Chip Bluetooth Transceiver for

Wireless Input Devices

The Cypress CYW20730 is a Bluetooth 3.0-compliant, stand-alone baseband processor with an integrated 2.4 GHz transceiver. It is

ideal for wireless input device applications including game controllers, keyboards, 3D glasses, remote controls, gestural input devices,

and sensor devices. Built-in firmware adheres to the Bluetooth Human Interface Device (HID) profile and Bluetooth Device ID profile

specifications.

The CYW20730 radio has been designed to provide low power, low cost, and robust communications for applications operating in the

globally available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0.

The single-chip Bluetooth transceiver is a monolithic component implemented in a standard digital CMOS process and requires

minimal external components to make a fully compliant Bluetooth device. The CYW20730 is available in three package options: a 32-

pin, 5 mm × 5 mm QFN, a 40-pin, 6 mm × 6 mm QFN, and a 64-pin, 7 mm × 7 mm BGA.

Cypress Part Numbering Scheme

Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,

there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides

Cypress ordering part number that matches an existing IoT part number.

Table 1. Mapping Table for Part Number between Broadcom and Cypress

Broadcom Part Number

Cypress Part Number

BCM20730

CYW20730

BCM20730A2KML2GT

BCM20730A1KML2G

BCM20730A1KMLG

BCM20730A1KFBGT

BCM20730A2KFBG

BCM20730A1KFBG

BCM20730A1KML2GT

BCM20730A2KML2G

BCM20730A1KMLGT

BCM20730A2KFBGT

CYW20730A2KML2GT

CYW20730A1KML2G

CYW20730A1KMLG

CYW20730A1KFBGT

CYW20730A2KFBG

CYW20730A1KFBG

CYW20730A1KML2GT

CYW20730A2KML2G

CYW20730A1KMLGT

CYW20730A2KFBGT

Acronyms and Abbreviations

In most cases, acronyms and abbreviations are defined on first use.

For a comprehensive list of acronyms and other terms used in Cypress documents, go to http://www.cypress.com/glossary.

Applications

■ Wireless pointing devices: mice, trackballs, gestural controls

■ Point-of-sale (POS) input devices

■ Remote sensors

■ Wireless keyboards

■ 3D glasses

■ Home automation

■ Remote controls

■ Game controllers

■ Personal health and fitness monitoring

Cypress Semiconductor Corporation

Document Number: 002-14824 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 25, 2017

CYW20730

Features

■ On-chip support for common keyboard and mouse interfaces

■ 10-bit auxiliary ADC with 28 analog channels

eliminates external processor

■ On-chip support for serial peripheral interface (master and

■ Programmable keyscan matrix interface, up to 8 × 20 key-

slave modes)

scanning matrix

■ BroadcomSerialCommunications(BSC)interface(compatible

■ 3-axis quadrature signal decoder

■ Shutter control for 3D glasses

■ Infrared modulator

with Philips® (now NXP) I²C slaves)

■ Programmable output power control meets Class 2 or Class 3

requirements

■ Class 1 operation supported with external PA and T/R switch

■ Integrated ARM Cortex™-M3 based microprocessor core

■ On-chip power-on reset (POR)

■ IR learning

■ Triac control

■ Triggered Broadcom Fast Connect

■ Supports Adaptive Frequency Hopping

■ Excellent receiver sensitivity

■ Support for EEPROM and serial flash interfaces

■ Integrated low-dropout regulator (LDO)

■ On-chip software controlled power management unit

■ Bluetooth specification 3.0 compatible, including enhanced

power control (Unicast Connectionless Data)

■ Three package types are available:

❐ 32-pin QFN package (5 mm × 5 mm)

❐ 40-pin QFN package (6 mm × 6 mm)

❐ 64-pin BGA package (7 mm × 7 mm)

■ Bluetooth HID profile version 1.0 compliant

■ Bluetooth Device ID profile version 1.3 compliant

■ Bluetooth AVRCP-CT profile version 1.3 compliant

■ RoHS compliant

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CYW20730

Figure 1. Functional Block Diagram

Muxed on GPIO

Tx RTS_N

1.2V

UART_TXD

UART_RXD

SDA/

SCL/

Rx

CTS_N

VDD_CORE

1.2V

SCK

MOSI

MISO

1.2V VDD_CORE

Domain

WDT

28 ADC

Inputs

VSS,

VDDO,

VDDC

BSC/SPI

Master

Interface

(BSC is I²C -

compaƟble)

1.2V

POR

Test

UART

Periph 320K

UART ROM

Processing

Unit

(ARM -CM3)

60K

RAM

CT ɇ ѐ

ADC

1.2V

LDO

1.425V to 3.6V

1.62V to 3.6V

MIA

POR

System Bus

32 kHz

LPCLK

Peripheral

Interface

Block

I/O Ring

Control

Registers

Volt. Trans

hclk

VDD_IO

Domain

(24 MHz to 1 MHz)

RF Control

and Data

I/O Ring Bus

Bluetooth

2.4 GHz

Radio

Baseband

Core

3-D Glasses

and Triac

GPIO

Control/

Status

Keyboard

Matrix

3 -Axis

Mouse

IR

Mod.

and

SPI

PMU

Scanner

w/FIFO

Signal

24

M/S

Learning

Registers

MHz

Controller

Power

RF I/O

T/R

Switch

Frequency

Synthesizer

32 kHz

LPCLK

WAKE

128 kHz

LPO

6 Quadrature

Inputs (3 pair) +

High Current

IR

I/O

8 x 20

Scan

Matrix

40 GPIO

AutoCal

128 kHz

LPCLK

Driver Controls

1.2V VDD_RF

Domain

28 ADC

Inputs

÷ 4

PWM

40 GPIO on the 64-pin BGA

(22 GPIO on the 40-pin QFN)

(14 GPIO on the 32-pin QFN)

24 MHz

Ref Xtal

32 kHzꢀyƚĂůꢀ;ŽƉƟŽŶĂůͿꢀ

1.62V to 3.6V

VDD_IO

IoT Resources

Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your

design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of

information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software

updates. Customers can acquire technical documentation and software from the Cypress Support Community website 

(http://community.cypress.com/).

Document Number: 002-14824 Rev. *J

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CYW20730

Contents

1. Functional Description .................................................5

1.1 Keyboard Scanner .................................................5

1.2 Mouse Quadrature Signal Decoder .......................6

1.3 Shutter Control for 3D Glasses .............................6

1.4 Infrared Modulator .................................................7

1.5 Infrared Learning ...................................................7

1.6 Triac Control ..........................................................8

1.7 Broadcom Proprietary Control Signaling and

1.16 PWM ..................................................................18

1.17 Power Management Unit ...................................19

2. Pin Assignments ........................................................20

2.1 Pin Descriptions ..................................................20

2.2 Ball Maps .............................................................28

3. Specifications .............................................................31

3.1 Electrical Characteristics .....................................31

3.2 RF Specifications ................................................34

3.3 Timing and AC Characteristics ............................36

4. Mechanical Information .............................................41

4.1 Tape Reel and Packaging Specifications ............44

5. Ordering Information ..................................................45

A. Appendix: Acronyms and Abbreviations ................46

A.1 References ..........................................................47

Document History ..........................................................48

Sales, Solutions, and Legal Information ......................50

Triggered Broadcom Fast Connect ......................8

1.8 Bluetooth Baseband Core .....................................8

1.9 ADC Port ...............................................................9

1.10 Serial Peripheral Interface .................................10

1.11 Microprocessor Unit ..........................................12

1.12 Integrated Radio Transceiver ............................14

1.13 Peripheral Transport Unit ..................................15

1.14 Clock Frequencies .............................................15

1.15 GPIO Port ..........................................................17

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CYW20730

1. Functional Description

1.1 Keyboard Scanner

The keyboard scanner is designed to autonomously sample keys and store them into buffer registers without the need for the host

microcontroller to intervene. The scanner has the following features:

■ Ability to turn off its clock if no keys pressed.

■ Sequential scanning of up to 160 keys in an 8 x 20 matrix.

■ Programmable number of columns from 1 to 20.

■ Programmable number of rows from 1 to 8.

■ 16-byte key-code buffer (can be augmented by firmware).

■ 128 kHz clock – allows scanning of full 160-key matrix in about 1.2 ms.

■ N-key rollover with selective 2-key lockout if ghost is detected.

■ Keys are buffered until host microcontroller has a chance to read it, or until overflow occurs.

■ Hardware debouncing and noise/glitch filtering.

■ Low-power consumption. Single-digit µA-level sleep current.

1.1.1 Theory of Operation

The key scan block is controlled by a state machine with the following states:

Idle

The state machine begins in the idle state. In this state, all column outputs are driven high. If any key is pressed, a transition occurs

on one of the row inputs. This transition causes the 128 kHz clock to be enabled (if it is not already enabled by another peripheral)

and the state machine to enter the scan state. Also in this state, an 8-bit row-hit register and an 8-bit key-index counter is reset to 0.

Scan

In the scan state, a row counter counts from 0 up to a programmable number of rows minus 1. Once the last row is reached, the row

counter is reset and the column counter is incremented. This cycle repeats until the row and column counters are both at their

respective terminal count values. At that point, the state machine moves into the Scan-End state.

As the keys are being scanned, the key-index counter is incremented. This counter is the value compared to the modifier key codes

stored, or in the key-code buffer if the key is not a modifier key. It can be used by the microprocessor as an index into a lookup table

of usage codes.

Also, as the n-th row is scanned, the row-hit register is ORed with the current 8-bit row input values if the current column contains two

or more row hits. During the scan of any column, if a key is detected at the current row, and the row-hit register indicates that a hit

was detected in that same row on a previous column, then a ghost condition may have occurred, and a bit in the status register is set

to indicate this.

Scan End

This state determines whether any keys were detected while in the scan state. If yes, the state machine returns to the scan state. If

no, the state machine returns to the idle state, and the 128 kHz clock request signal is made inactive.

The microcontroller can poll the key status register.

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CYW20730

1.2 Mouse Quadrature Signal Decoder

The mouse signal decoder is designed to autonomously sample two quadrature signals commonly generated by optomechanical

mouse apparatus. The decoder has the following features:

■ Three pairs of inputs for X, Y, and Z (typical scroll wheel) axis signals. Each axis has two options:

❐ For the X axis, choose P2 or P32 as X0 and P3 or P33 as X1.

❐ For the Y axis, choose P4 or P34 as Y0 and P5 or P35 as Y1.

❐ For the Z axis, choose P6 or P36 as Z0 and P7 or P37 as Z1.

■ Control of up to four external high current GPIOs to power external optoelectronics:

❐ Turn-on and turn-off time can be staggered for each HC-GPIO to avoid simultaneous switching of high currents and having multiple

high-current devices on at the same time.

❐ Sample time can be staggered for each axis.

❐ Sense of the control signal can be active high or active low.

❐ Control signal can be tristated for off condition or driven high or low, as appropriate.

1.2.1 Theory of Operation

The mouse decoder block has four 16-bit PWMs for controlling external quadrature devices and sampling the quadrature inputs at its

core.

The GPIO signals may be used to control such items as LEDs, external ICs that may emulate quadrature signals, photodiodes, and

photodetectors.

1.3 Shutter Control for 3D Glasses

The CYW20730, combined with the CYW20702, provides full system support for 3D glasses on televisions. The CYW20702 gets

frame synchronization signals from the TV, converts them into proprietary timing control messages, then passes these messages to

the CYW20730. The CYW20730 uses these messages to synchronize the shutter control for the 3D glasses with the television frames.

The CYW20730 can provide up to four synchronized control signals for left and right eye shutter control. These four lines can output

pulses with microsecond resolution for on and off timing. The total cycle time can be set for any period up to 65535 msec. The pulses

are synchronized to each other for left and right eye shutters.

The CYW20730 seamlessly adjusts the timing of the control signals based on control messages from the CYW20702, ensuring that

the 3D glasses remain synchronized to the TV display frame.

3D hardware control on the CYW20730 works independently of the rest of the system. The CYW20730 negotiates sniff with the

CYW20702 and, except for sniff resynchronization periods, most of the CYW20730 circuitry remains in a low power state while the

3D glasses subsystem continues to provide shutter timing and control pulses. This significantly reduces total system power

consumption.

The CYW20730A2 has the new BT SIG 3DG profile, as well as legacy mode 3DG, included in ROM. This allows it to support a smaller

and lower cost external memory of 4 KB.

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CYW20730

1.4 Infrared Modulator

The CYW20730 includes hardware support for infrared TX. The hardware can transmit both modulated and unmodulated waveforms.

For modulated waveforms, hardware inserts the desired carrier frequency into all IR transmissions. IR TX can be sourced from

firmware-supplied descriptors, a programmable bit, or the peripheral UART transmitter.

If descriptors are used, they include IR on/off state and the duration between 1–32767 µsec. The CYW20730 IR TX firmware driver

inserts this information in a hardware FIFO and makes sure that all descriptors are played out without a glitch due to underrun. See

Figure 2.

Figure 2. Infrared TX

1.5 Infrared Learning

The CYW20730 includes hardware support for infrared learning. The hardware can detect both modulated and unmodulated signals.

For modulated signals, the CYW20730 can detect carrier frequencies between 10 kHz and 500 kHz and the duration that the signal

is present or absent. The CYW20730 firmware driver supports further analysis and compression of learned signal. The learned signal

can then be played back through the CYW20730 IR TX subsystem. See Figure 3.

Figure 3. Infrared RX

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CYW20730

1.6 Triac Control

The CYW20730 includes hardware support for zero-crossing detection and trigger control for up to four triacs. The CYW20730 detects

zero-crossing on the AC zero detection line and uses that to provide a pulse that is offset from the zero-crossing. This allows the

CYW20730 to be used in dimmer applications, as well as any other applications that require a control signal that is offset from an

input event.

1.7 Broadcom Proprietary Control Signaling and Triggered Broadcom Fast Connect

Broadcom Proprietary Control Signaling (BPCS) and Triggered Broadcom Fast Connect (TBFC) are Broadcom-proprietary baseband

(ACL) suspension and low latency reconnection mechanisms that reestablish the baseband connection with the peer controller that

also supports BPCS/TBFC.

The CYW20730 uses BPCS primitives to allow a Human Interface Device (HID) to suspend all RF traffic after a configurable idle

period with no reportable activity. To conserve power, it can then enter one of its low power states while still logically remaining

connected at the L2CAP and HID layers with the peer device. When an event requires the HID to deliver a report to the peer device,

the CYW20730 uses the TBFC and BPCS mechanisms to reestablish the baseband connection and can immediately resume L2CAP

traffic, greatly reducing latency between the event and delivery of the report to the peer device.

Certain applications may make use of the CYW20730 Baseband Fast Connect (BFC) mechanism for power savings and lower

latencies not achievable by using even long sniff intervals by completely eliminating the need to maintain an RF link, while still being

able to establish ACL and L2CAP connections much faster than regular methods.

1.8 Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high performance Bluetooth operation.

The BBC manages the buffering, segmentation, and data routing for all connections. It also buffers data that passes through it, handles

data flow control, schedules ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into

baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it

independently handles HCI event types and HCI command types.

The following transmit and receive functions are also implemented in the BBC hardware to increase TX/RX data reliability and security

before sending over the air:

■ Receive Functions: symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic

redundancy check (CRC), data decryption, and data dewhitening.

■ Transmit Functions: data framing, FEC generation, HEC generation, CRC generation, link key generation, data encryption, and

data whitening.

1.8.1 Frequency Hopping Generator

The frequency hopping sequence generator selects the correct hopping channel number depending on the link controller state,

Bluetooth clock, and device address.

1.8.2 E0 Encryption

The encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide

minimal processor intervention.

1.8.3 Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the Link Control Unit

(LCU). This layer consists of the Command Controller, which takes software commands, and other controllers that are activated or

configured by the Command Controller to perform the link control tasks. Each task performs a different Bluetooth link controller state.

STANDBY and CONNECTION are the two major states. In addition, there are five substates: page, page scan, inquiry, inquiry scan,

and sniff.

1.8.4 Adaptive Frequency Hopping

The CYW20730 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment and channel map

selection. The link quality is determined by using both RF and baseband signal processing to provide a more accurate frequency hop

map.

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CYW20730

1.8.5 Bluetooth Version 3.0 Features

The CYW20730 supports Bluetooth 3.0, including the following options:

■ Enhanced Power Control

■ Unicast Connectionless Data

■ HCI Read Encryption Key Size command

The CYW20730 also supports the following Bluetooth version 2.1 features:

■ Extended Inquiry Response

■ Sniff Subrating

■ Encryption Pause and Resume

■ Secure Simple Pairing

■ Link Supervision Timeout Changed Event

■ Erroneous Data Reporting

■ Non-Automatically-Flushable Packet Boundary Flag

■ Security Mode 4

1.8.6 Test Mode Support

The CYW20730 fully supports Bluetooth Test mode, as described in Part 1 of the Bluetooth 3.0 specification. This includes the

transmitter tests, normal and delayed loopback tests, and the reduced hopping sequence.

In addition to the standard Bluetooth Test mode, the device supports enhanced testing features to simplify RF debugging and quali-

fication as well as type-approval testing.

1.9 ADC Port

The CYW20730 contains a 16-bit ADC (effective number of bits is 10).

Additionally:

■ There are 28 analog input channels in the 64-pin package, 12 analog input channels in the 40-pin package, and 9 analog input

channels in the 32-pin package. All channels are multiplexed on various GPIOs.

■ The conversion time is 10 s.

■ There is a built-in reference with supply- or band-gap based reference modes.

■ The maximum conversion rate is 187 kHz.

■ There is a rail-to-rail input swing.

The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes

the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input

multiplexers that select the ADC input signal V_inpand the ADC reference signals V_ref

.

Table 2. ADC Modes

Mode

ENOB (Typical)

Maximum Sampling Rate (kHz)

Latency^a(s)

0

1

2

3

4

13

12.6

12

5.859

11.7

171

85

21

11

5

46.875

93.75

187

11.5

10

a. Settling time after switching channels.

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CYW20730

1.10 Serial Peripheral Interface

The CYW20730 has two independent SPI interfaces. One is a master-only interface and the other can be either a master or a slave.

Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more flexibility for user applications, the

CYW20730 has optional I/O ports that can be configured individually and separately for each functional pin, as shown in Table 3. The

CYW20730 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves, as shown in Table 3. The CYW20730 can also act

as an SPI slave device that supports a 1.8V or 3.3V SPI master, as shown in Table 3.

Table 3. CYW20730 First SPI Set (Master Mode)

Pin Name

Configuration set 1

Configuration set 2

SPI_CLK

SCL

SPI_MOSI

SDA

SPI_MISO

P24

SPI_CS^a

–

SCL

SDA

P26

Configuration set 3

(Default for serial flash)

SCL

SDA

P32

P39

P33

–

Configuration set 4

a. Any GPIO can be used as SPI_CS when SPI is in master mode.

Table 4. CYW20730 Second SPI Set (Master Mode)

Pin Name

SPI_CLK

P3

SPI_MOSI

P0

SPI_MISO

P1

SPI_CS^a

Configuration set 1

Configuration set 2

Configuration set 3

Configuration set 4

Configuration set 5

Configuration set 6

Configuration set 7

Configuration set 8

Configuration set 9

Configuration set 10

Configuration set 11

Configuration set 12

Configuration set 13

Configuration set 14

Configuration set 15

Configuration set 16

Configuration set 17

Configuration set 18

Configuration set 19

Configuration set 20

Configuration set 21

Configuration set 22

Configuration set 23

Configuration set 24

–

P3

P0

P5

P3

P2

P1

P3

P2

P5

P3

P4

P1

P3

P4

P5

P3

P27

P38

P0

P1

P3

P5

P3

P1

P3

P5

P7

P1

P7

P0

P5

P7

P2

P1

P7

P2

P5

P7

P4

P1

P7

P4

P5

P7

P27

P38

P0

P1

P7

P5

P7

P1

P7

P5

P24

P25

P2

P4

P27

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CYW20730

Table 4. CYW20730 Second SPI Set (Master Mode) (Cont.)

Pin Name

SPI_CLK

P24

SPI_MOSI

P38

SPI_MISO

P25

SPI_CS^a

Configuration set 25

Configuration set 26

Configuration set 27

Configuration set 28

Configuration set 29

Configuration set 30

–

P36

P0

P25

P36

P2

P25

P36

P4

P25

P36

P27

P25

P36

P38

P25

a. Any GPIO can be used as SPI_CS when SPI is in master mode.

Table 5. CYW20730 Second SPI Set (Slave Mode)^a

Pin Name

SPI_CLK

P3

SPI_MOSI

P0

SPI_MISO

P1

SPI_CS

P2

Configuration set 1

Configuration set 2

Configuration set 3

Configuration set 4

Configuration set 5

Configuration set 6

Configuration set 7

Configuration set 8

Configuration set 9

Configuration set 10

Configuration set 11

Configuration set 12

Configuration set 13

Configuration set 14

Configuration set 15

Configuration set 16

Configuration set 17

Configuration set 18

Configuration set 19

Configuration set 20

Configuration set 21

Configuration set 22

Configuration set 23

Configuration set 24

Configuration set 25

Configuration set 26

Configuration set 27

Configuration set 28

P3

P0

P5

P2

P3

P4

P1

P2

P3

P4

P5

P2

P7

P0

P1

P2

P7

P0

P5

P2

P7

P4

P1

P2

P7

P4

P5

P2

P3

P0

P1

P6

P3

P0

P5

P6

P3

P4

P1

P6

P3

P4

P5

P6

P7

P0

P1

P6

P7

P0

P5

P6

P7

P4

P1

P6

P7

P4

P5

P6

P24

P36

P24

P36

P27

P33

P38

P27

P33

P38

P27

P33

P38

P27

P33

P38

P25

P26

P32

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CYW20730

Table 5. CYW20730 Second SPI Set (Slave Mode)^a

Pin Name

SPI_CLK

P24

SPI_MOSI

P27

SPI_MISO

P25

SPI_CS

P39

Configuration set 29

Configuration set 30

Configuration set 31

Configuration set 32

Configuration set 33

Configuration set 34

P24

P33

P25

P39

P24

P38

P25

P39

P36

P27

P25

P39

P36

P33

P25

P39

P36

P38

P25

P39

a. Additional configuration sets are available upon request.

1.11 Microprocessor Unit

The CYW20730 microprocessor unit (µPU) executes software from the link control (LC) layer up to the application layer components

that ensure adherence to the Bluetooth Human Interface Device (HID) profile and Audio/Video Remote Control Profile (AVRCP). The

microprocessor is based on an ARM Cortex™-M3, 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units.

The µPU has 320 KB of ROM for program storage and boot-up, 60 KB of RAM for scratch-pad data, and patch RAM code.

The internal boot ROM provides power-on reset flexibility, which enables the same device to be used in different HID applications with

an external serial EEPROM or with an external serial flash memory. At power-up, the lowest layer of the protocol stack is executed

from the internal ROM memory.

External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can

also support the integration of user applications.

1.11.1 EEPROM Interface

The CYW20730 provides a Broadcom Serial Control (BSC) master interface. The BSC is programmed by the CPU to generate four

types of BSC bus transfers: read-only, write-only, combined read/write, and combined write/read. BSC supports both low-speed and

fast mode devices. The BSC is compatible with a Philips® (now NXP) I²C slave device, except that master arbitration (multiple I²C

masters contending for the bus) is not supported.

The EEPROM can contain customer application configuration information including: application code, configuration data, patches,

pairing information, BD_ADDR, baud rate, SDP service record, and file system information used for code.

Native support for the Microchip® 24LC128, Microchip 24AA128, and ST Micro® M24128-BR is included.

1.11.2 Serial Flash Interface

The CYW20730 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB

slave interface, transmit and receive FIFOs, and the SPI core PHY logic.

Devices natively supported include the following:

■ Atmel® AT25BCM512B

■ MXIC® MX25V512ZUI-20G

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CYW20730

1.11.3 Internal Reset

Figure 4. Internal Reset Timing

VDDO POR delay

~ 2 ms

VDDO

VDDO POR threshold

VDDC POR threshold

VDDO POR

VDDC

VDDC POR delay

~ 2 ms

VDDC POR

Crystal

warm‐up

delay:

~ 5 ms

Baseband Reset

Start reading EEPROM and

firmware boot

Crystal Enable

1.11.4 External Reset

The CYW20730 has an integrated power-on reset circuit that completely resets all circuits to a known power-on state. An external

active low reset signal, RESET_N, can be used to put the CYW20730 in the reset state. The RESET_N pin has an internal pull-up

resistor and, in most applications, it does not require that anything be connected to it. RESET_N should only be released after the

VDDO supply voltage level has been stabilized.

Figure 5. External Reset Timing

Pulse width

>50 µs

RESET_N

Crystal

warm‐up

delay:

~ 5 ms

Baseband Reset

Start reading EEPROM and

firmware boot

Crystal Enable

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Page 13 of 50

CYW20730

1.12 Integrated Radio Transceiver

The CYW20730 has an integrated radio transceiver that is optimized for 2.4 GHz Bluetooth® wireless systems. It has been designed

to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed

ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 and meets or exceeds the requirements to provide the highest

communication link quality of service.

1.12.1 Transmitter Path

The CYW20730 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.

Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes

any frequency drift or anomalies in the modulation characteristics of the transmitted signal.

Power Amplifier

The CYW20730 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation.

1.12.2 Receiver Path

The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit

synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order, on-chip channel

filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation,

enables the CYW20730 to be used in most applications without off-chip filtering.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit

synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the CYW20730 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller

to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the

transmitter should increase or decrease its output power.

1.12.3 Local Oscillator

The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The

CYW20730 uses an internal loop filter.

1.12.4 Calibration

The CYW20730 radio transceiver features a self-contained automated calibration scheme. No user interaction is required during

normal operation or during manufacturing to provide optimal performance. Calibration compensates for filter, matching network, and

amplifier gain and phase characteristics to yield radio performance within 2% of what is optimal. Calibration takes process and

temperature variations into account, and it takes place transparently during normal operation and hop setting times.

1.12.5 Internal LDO Regulator

The CYW20730 has an integrated 1.2V LDO regulator that provides power to the digital and RF circuits. The 1.2V LDO regulator

operates from a 1.425V to 3.63V input supply with a 30 mA maximum load current.

Note: Always place the decoupling capacitors near the pins as closely together as possible.

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CYW20730

1.13 Peripheral Transport Unit

1.13.1 Broadcom Serial Communications Interface

The CYW20730 provides a 2-pin master BSC interface, which can be used to retrieve configuration information from an external

EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse

devices. The BSC interface is compatible with I²C slave devices. The BSC does not support multimaster capability or flexible wait-

state insertion by either master or slave devices.

The following transfer clock rates are supported by the BSC:

■ 100 kHz

■ 400 kHz

■ 800 kHz (Not a standard I²C-compatible speed.)

■ 1 MHz (Compatibility with high-speed I²C-compatible devices is not guaranteed.)

The following transfer types are supported by the BSC:

■ Read (Up to 16 bytes can be read.)

■ Write (Up to 16 bytes can be written.)

■ Read-then-Write (Up to 16 bytes can be read and up to 16 bytes can be written.)

■ Write-then-Read (Up to 16 bytes can be written and up to 16 bytes can be read.)

Hardware controls the transfers, requiring minimal firmware setup and supervision.

The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the CYW20730 are required on

both the SCL and SDA pins for proper operation.

1.13.2 UART Interface

The UART is a standard 2-wire interface (RX and TX) and has adjustable baud rates from 9600 bps to 1.5 Mbps. The baud rate can

be selected via a vendor-specific UART HCI command. The interface supports the Bluetooth 3.0 UART HCI (H5) specification. The

default baud rate for H5 is 115.2 kbaud.

Both high and low baud rates can be supported by running the UART clock at 24 MHz.

The CYW20730 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%.

1.14 Clock Frequencies

The CYW20730 is set with crystal frequency of 24 MHz.

1.14.1 Crystal Oscillator

The crystal oscillator requires a crystal with an accuracy of ±20 ppm as defined by the Bluetooth specification. Two external load

capacitors in the range of 5 pF to 30 pF are required to work with the crystal oscillator. The selection of the load capacitors is crystal

dependent. Table 6 on page 16 shows the recommended crystal specification.

Figure 6. Recommended Oscillator Configuration—12 pF Load Crystal

22 pF

XIN

Crystal

XOUT

20 pF

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CYW20730

Table 6. Reference Crystal Electrical Specifications

Parameter

Nominal frequency

Conditions

Minimum

Typical

Maximum

Unit

MHz

–

24.000

–

Oscillation mode

–

Fundamental

Frequency tolerance

Tolerance stability over temp

Equivalent series resistance

Load capacitance

@25°C

–

±10

–

ppm

W

@0°C to +70°C

–

50

–

12

–

pF

Operating temperature range

Storage temperature range

Drive level

0

+70

+125

200

±10

2

°C

–40

–

°C

–

W

Aging

–

ppm/year

pF

Shunt capacitance

–

HID Peripheral Block

The peripheral blocks of the CYW20730 all run from a single 128 kHz low-power RC oscillator. The oscillator can be turned on at the

request of any of the peripherals. If the peripheral is not enabled, it shall not assert its clock request line.

The keyboard scanner is a special case in that it may drop its clock request line even when enabled and then reassert the clock

request line if a keypress is detected.

32 kHz Crystal Oscillator

Figure 7 shows the 32 kHz crystal (XTAL) oscillator with external components and Table 7 on page 17 lists the oscillator’s character-

istics. It is a standard Pierce oscillator using a comparator with hysteresis on the output to create a single-ended digital output. The

hysteresis was added to eliminate any chatter when the input is around the threshold of the comparator and is ~100 mV. This circuit

can be operated with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at similar frequency. The default

component values are: R1 = 10 M, C1 = C2 = ~10 pF. The values of C1 and C2 are used to fine-tune the oscillator.

Figure 7. 32 kHz Oscillator Block Diagram

C2

32.768 kHz

R1

XTAL

C1

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CYW20730

Table 7. XTAL Oscillator Characteristics

Parameter

Symbol

Conditions

Minimum

Typical

Maximum

Unit

Output frequency

F_oscout

–

32.768

–

kHz

Frequency

tolerance

–

Crystal dependent

–

100

–

ppm

Start-up time

T_startup

P_drv

–

500

–

ms

XTAL drive level

For crystal selection

0.5

W

XTAL series

resistance

R_series

C_shunt

For crystal selection

–

70

k

XTAL shunt

capacitance

1.3

pF

1.15 GPIO Port

The CYW20730 has 14 general-purpose I/Os (GPIOs) in the 32-pin package, 22 GPIOs in the 40-pin package, and 40 GPIOs in the

64-pin package. All GPIOs support programmable pull-up and pull-down resistors, and all support a 2 mA drive strength except P26,

P27, P28, and P29, which provide a 16 mA drive strength at 3.3V supply.

1.15.1 Port 0–Port 1, Port 8–Port 23, and Port 28–Port 38

All of these pins can be programmed as ADC inputs.

1.15.2 Port 26–Port 29

P[26:29] consists of four pins. All pins are capable of sinking up to 16 mA for LED. These pins also have the PWM function, which

can be used for LED dimming.

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CYW20730

1.16 PWM

The CYW20730 has four internal PWM channels. The PWM module consists of the following:

■ PWM1–4

■ Each of the four PWM channels, PWM1–4, contains the following registers:

❐ 10-bit initial value register (read/write)

❐ 10-bit toggle register (read/write)

❐ 10-bit PWM counter value register (read)

■ The PWM configuration register is shared among PWM1–4 (read/write). This 12-bit register is used:

❐ To configure each PWM channel.

❐ To select the clock of each PWM channel

❐ To change the phase of each PWM channel

Figure 8 shows the structure of one PWM channel.

Figure 8. PWM Channel Block Diagram

pwm_cfg_adr register

pwm#_init_val_adr register

10

pwm#_togg_val_adr register

10

pwm#_cntr_adr

10

cntr value is CM3 readable

pwm_out

Example: PWM cntr w/ pwm#_init_val = 0 (dashed line)

PWM cntr w/ pwm#_init_val = x (solid line)

10'H3FF

pwm_togg_val_adr

10'Hx

10'H000

pwm_out

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CYW20730

1.17 Power Management Unit

The Power Management Unit (PMU) provides power management features that can be invoked by software through power

management registers or packet-handling in the baseband core.

1.17.1 RF Power Management

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans-

ceiver, which then processes the power-down functions accordingly.

1.17.2 Host Controller Power Management

Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the

disabling of the on-chip regulator when in deep Sleep mode.

1.17.3 BBC Power Management

There are several low-power operations for the BBC:

■ Physical layer packet handling turns RF on and off dynamically within packet TX and RX.

■ Bluetooth-specified low-power connection sniff mode. While in these low-power connection modes, the CYW20730 runs on the

Low Power Oscillator and wakes up after a predefined time period.

The CYW20730 automatically adjusts its power dissipation based on user activity. The following power modes are supported:

■ Active mode

■ Idle mode

■ Sleep mode

■ HIDOFF mode

The CYW20730 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately entered

when user activity resumes.

In HIDOFF mode, the CYW20730 baseband and core are powered off by disabling power to LDOOUT. The VDDO domain remains

powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power consumption and

is intended for long periods of inactivity.

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CYW20730

2. Pin Assignments

2.1 Pin Descriptions

Table 8. Pin Descriptions

Pin Number

Pin Name

I/O

Power Domain

Description

32-Pin QFN 40-pin QFN 64-pin BGA

Radio I/O

6

8

F1

RF

I/O

VDD_RF

RF antenna port

RF Power Supplies

4

5

7

8

6

7

D1

E1

H1

H2

VDDIF

I

VDD_RF

IFPLL power supply

RF front-end supply

VCO, LOGEN supply

VDDFE

VDDVCO

VDDPLL

I

9

I

10

I

RFPLL and crystal oscillator supply

Power Supplies

11

–

13

–

H6

VDDC

VSS

I

N/A

Baseband core supply

Ground

D4, E2, E5,

F2, G1, G2

I

28

14

34

16

A6, D7

–

VDDO

VDDM

I

VDDO

VDDM

I/O pad and core supply

I/O pad supply

Clock Generator and Crystal Interface

Crystal oscillator input. See “Crystal

Oscillator” on page 15 for options.

9

11

12

H3

G3

XTALI

I

VDD_RF

10

XTALO

O

Crystal oscillator output.

Low-power oscillator (LPO) input is

used.

Alternative Function:

1

40

39

A3

B3

XTALI32K

I

VDDO

■ P11 and P27 in 32-QFN only

■ P11 in 40-QFN only

■ P39 in 64-BGA only

Low-power oscillator (LPO) output.

Alternative Function:

■ P12 and P26 in 32-QFN only

■ P12 in 40-QFN only

32

XTALO32K

O

■ P38 in 64-BGA only

Core

Active-low system reset with open-drain

output & internal pull-up resistor

18

17

20

19

G8

G7

RESET_N

TMC

I/O PU

VDDO

Test mode control

High: test mode

I

Connect to GND if not used.

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CYW20730

Table 8. Pin Descriptions (Cont.)

Pin Number

Pin Name

UART_RXD

UART_TXD

I/O

Power Domain

Description

32-Pin QFN 40-pin QFN 64-pin BGA

UART

UART serial input – Serial data input for

the HCI UART interface. Leave uncon-

nected if not used.

12

13

14

15

H5

G5

I

VDDM^a

Alternative function:

■ GPIO3

UART serial output – Serial data output

for the HCI UART interface. Leave

unconnected if not used.

O, PU

VDDM^a

Alternative Function:

■ GPIO2

BSC

Data signal for an external I²C device.

Alternative function:

VDDM^a

■ SPI_1: MOSI (master only)

15

16

17

18

F7

E8

SDA

SCL

I/O, PU

■ GPIO0

■ CTS

Clock signal for an external I²C device.

Alternative function:

■ SPI_1: SPI_CLK (master only)

■ GPIO1

■ RTS

LDO Regulator Power Supplies

2

3

4

5

B1

C1

LDOIN

I

LDO

Battery input supply for the LDO

LDO output

LDOOUT

O

a. VDDO for 64-pin package.

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CYW20730

Table 9. GPIO Pin Descriptions^a

Pin Number

Default Di-

rection

Power

Domain

Pin Name

After POR

Alternate Function Description

■ GPIO: P0

32-Pin

QFN

40-pin

QFN

64-pin

BGA

■ Keyboard scan input (row): KSI0

■ A/D converter input

■ Peripheral UART: puart_tx

■ SPI_2: MOSI (master and slave)

■ IR_RX

19

21

F6

P0

Input

Floating

VDDO

■ 60 Hz_main

■ Not available during TMC=1

■ GPIO: P1

■ Keyboard scan input (row): KSI1

■ A/D converter input

20

22

G6

P1

Input

Floating

VDDO

■ Peripheral UART: puart_rts

■ SPI_2: MISO (master and slave)

■ IR_TX

■ GPIO: P2

■ Keyboard scan input (row): KSI2

■ Quadrature: QDX0

22

24

H8

P2

Input

Floating

VDDO

■ Peripheral UART: puart_rx

■ Triac control 2

■ SPI_2: SPI_CS (slave only)

■ SPI_2: SPI_MOSI (master only)

■ GPIO: P3

■ Keyboard scan input (row): KSI3

■ Quadrature: QDX1

21

23

25

F8

P3

P4

Input

Floating

VDDO

■ Peripheral UART: puart_cts

■ SPI_2: SPI_CLK (master and slave)

■ GPIO: P4

■ Keyboard scan input (row): KSI4

■ Quadrature: QDY0

H7

■ Peripheral UART: puart_rx

■ SPI_2: MOSI (master and slave)

■ IR_TX

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CYW20730

Table 9. GPIO Pin Descriptions^a(Cont.)

Pin Number

Default Di-

rection

Power

Domain

Pin Name

After POR

Alternate Function Description

■ GPIO: P5

32-Pin

QFN

40-pin

QFN

64-pin

BGA

■ Keyboard scan input (row): KSI5

■ Quadrature: QDY1

–

26

E6

P5

Input

Floating

VDDO

■ Peripheral UART: puart_tx

■ SPI_2: MISO (master and slave)

■ GPIO: P6

■ Keyboard scan input (row): KSI6

■ Quadrature: QDZ0

P6

PWM2

–

27

F5

Input

Floating

VDDO

■ Peripheral UART: puart_rts

■ SPI_2: SPI_CS (slave only)

■ 60Hz_main

■ Triac control 1

■ GPIO: P7

■ Keyboard scan input (row): KSI7

■ Quadrature: QDZ1

–

28

29

C5

F4

P7

Input

Floating

VDDO

■ Peripheral UART: puart_cts

■ SPI_2: SPI_CLK (master and slave)

■ GPIO: P8

■ Keyboard scan output (column): KSO0

■ A/D converter input

24

P8

P9

■ External T/R switch control: ~tx_pd

Alternative Function:

■ P33 in 32-QFN only

■ GPIO: P9

■ Keyboard scan output (column): KSO1

■ A/D converter input

–

3

2

A1

D2

Input

Floating

VDDO

■ External T/R switch control: tx_pd

■ GPIO: P10

P10

PWM3

■ Keyboard scan output (column): KSO2

■ A/D converter input

■ GPIO: P11

■ Keyboard scan output (column): KSO3

■ A/D converter input

1

40

C2

P11

Input

Floating

VDDO

■ XTALI32K (32-QFN and 40-QFN only)

Alternative Function:

■ P27 in 32-QFN only

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CYW20730

Table 9. GPIO Pin Descriptions^a(Cont.)

Pin Number

Default Di-

rection

Power

Domain

Pin Name

After POR

Alternate Function Description

■ GPIO: P12

32-Pin

QFN

40-pin

QFN

64-pin

BGA

■ Keyboard scan output (column): KSO4

■ A/D converter input

32

29

39

35

B2

P12

Input

Floating

VDDO

■ XTALO32K (32-QFN and 40-QFN only)

Alternative Function:

■ P26 in 32-QFN only

■ GPIO: P13

■ Keyboard scan output (column): KSO5

■ A/D converter input

P13

PWM3

F3

Floating

■ Triac control 3

Alternative Function:

■ P28 in 32-QFN only

■ GPIO: P14

■ Keyboard scan output (column): KSO6

■ A/D converter input

P14

PWM2

30

31

36

37

D3

A2

Input

Floating

VDDO

■ Triac control 4

Alternative Function:

■ P38 in 32-QFN only

■ GPIO: P15

■ Keyboard scan output (column): KSO7

■ A/D converter input

■ IR_RX

P15

■ 60Hz_main

■ GPIO: P16

–

C8

H4

P16

P17

Input

Floating

VDDO

■ Keyboard scan output (column): KSO8

■ GPIO: P17

■ Keyboard scan output (column): KSO9

■ A/D converter input

■ GPIO: P18

–

C7

B8

A8

P18

P19

P20

Input

Floating

VDDO

■ Keyboard scan output (column): KSO10

■ A/D converter input

■ GPIO: P19

■ Keyboard scan output (column): KSO11

■ A/D converter input

■ GPIO: P20

■ Keyboard scan output (column): KSO12

■ A/D converter input

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CYW20730

Table 9. GPIO Pin Descriptions^a(Cont.)

Pin Number

Default Di-

rection

Power

Domain

Pin Name

After POR

Alternate Function Description

■ GPIO: P21

32-Pin

QFN

40-pin

QFN

64-pin

BGA

■ Keyboard scan output (column): KSO13

■ A/D converter input

–

C6

P21

Input

Floating

VDDO

■ Triac control 3

■ GPIO: P22

■ Keyboard scan output (column): KSO14

■ A/D converter input

–

G4

E3

P22

P23

Input

Floating

VDDO

■ Triac control 4

■ GPIO: P23

■ Keyboard scan output (column): KSO15

■ A/D converter input

■ GPIO: P24

■ Keyboard scan output (column): KSO16

■ SPI_2: SPI_CLK (master and slave)

■ SPI_1: MISO (master only)

■ Peripheral UART: puart_tx

■ GPIO: P25

27

26

33

32

A7

B7

P24

P25

Input

Floating

VDDO

■ Keyboard scan output (column): KSO17

■ SPI_2: MISO (master and slave)

■ Peripheral UART: puart_rx

■ GPIO: P26

■ Keyboard scan output (column): KSO18

■ SPI_2: SPI_CS (slave only)

■ SPI_1: MISO (master only)

■ Optical control output: QOC0

P26

PWM0

32

38

A4

Input

Floating

VDDO

■ Triac control 1

Alternative Function:

■ P12 in 32-QFN only

Current: 16 mA

■ GPIO: P27

■ Keyboard scan output (column): KSO19

■ SPI_2: MOSI (master and slave)

■ Optical control output: QOC1

P27

PWM1

1

B4

Input

Floating

VDDO

■ Triac control 2

Alternative Function:

■ P11 in 32-QFN only

Current: 16 mA

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CYW20730

Table 9. GPIO Pin Descriptions^a(Cont.)

Pin Number

Default Di-

rection

Power

Domain

Pin Name

After POR

Alternate Function Description

■ GPIO: P28

32-Pin

QFN

40-pin

QFN

64-pin

BGA

■ Optical control output: QOC2

■ A/D converter input

■ LED1

P28

PWM2

29

–

B5

Input

Floating

VDDO

■ IR_TX

Alternative Function:

■ P13 in 32-QFN only

Current: 16 mA

■ GPIO: P29

■ Optical control output: QOC3

■ A/D converter input

■ LED2

P29

PWM3

–

A5

Input

Floating

VDDO

■ IR_RX

Current: 16 mA

■ GPIO: P30

■ A/D converter input

–

E4

E7

P30

P31

Input

Floating

VDDO

■ Pairing button pin in default FW

■ Peripheral UART: puart_rts

■ GPIO: P31

■ A/D converter input

■ EEPROM WP pin in default FW

■ Peripheral UART: puart_tx

■ GPIO: P32

■ A/D converter input

■ Quadrature: QDX0

25

31

D6

P32

Input

Floating

VDDO

■ SPI_2: SPI_CS (slave only)

■ SPI_1: MISO (master only)

■ Auxiliary clock output: ACLK0

■ Peripheral UART: puart_tx

■ GPIO: P33

■ A/D converter input

■ Quadrature: QDX1

■ SPI_2: MOSI (slave only)

■ Auxiliary clock output: ACLK1

24

30

D8

P33

Input

Floating

VDDO

■ Peripheral UART: puart_rx

Alternative Function:

■ P8 in 32-QFN only

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CYW20730

Table 9. GPIO Pin Descriptions^a(Cont.)

Pin Number

Default Di-

rection

Power

Domain

Pin Name

After POR

Alternate Function Description

■ GPIO: P34

32-Pin

QFN

40-pin

QFN

64-pin

BGA

■ A/D converter input

–

B6

D5

P34

Input

Floating

VDDO

■ Quadrature: QDY0

■ Peripheral UART: puart_rx

■ External T/R switch control: tx_pd

■ GPIO: P35

■ A/D converter input

P35

P36

Floating

■ Quadrature: QDY1

■ Peripheral UART: puart_cts

■ GPIO: P36

■ A/D converter input

■ Quadrature: QDZ0

–

C4

Input

VDDO

■ SPI_2: SPI_CLK (master and slave)

■ Auxiliary Clock Output: ACLK0

■ Battery detect pin in default FW

■ External T/R switch control: ~tx_pd

■ GPIO: P37

■ A/D converter input

–

C3

P37

Input

Floating

VDDO

■ Quadrature: QDZ1

■ SPI_2: MISO (slave only)

■ Auxiliary clock output: ACLK1

■ GPIO: P38

■ A/D converter input

■ SPI_2: MOSI (master and slave)

■ IR_TX

30

–

B3

P38

Input

Floating

VDDO

■ XTALO32K (64-BGA only)

Alternative Function:

■ P14 in 32-QFN only

■ GPIO: P39

■ SPI_2: SPI_CS (slave only)

■ SPI_1: MISO (master only)

■ Infrared control: IR_RX

■ External PA ramp control: PA_Ramp

■ XTALI32K (64-BGA only)

■ 60Hz_main

–

A3

P39

Input

Floating

VDDO

a. During Power-On Reset, all inputs are disabled.

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CYW20730

2.2 Ball Maps

Figure 9. 32-Pin QFN Ball Map

32 31 30 29 28 27 26 25

P11/P27/XTALI32K

P8/P33

P4

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

LDO_IN

LDO_OUT

VDDIF

P2

P3

VDDFE

RF

P1

P0

VDDVCO

VDDPLL

RST_N

TMC

9 10 11 12 13 14 15 16

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CYW20730

Figure 10. 40-pin QFN Ball Map

40 39 38 37 36 35 34 33 32 31

P27/PWM1

P10

1

2

30

29

28

27

26

25

24

23

22

21

P33

P8

P7

P6

P5

P4

P2

P3

P1

P0

P9

3

LDOIN

LDOOUT

VDDIF

VDDFE

RF

4

5

6

7

8

VDDVCO

VDDPLL

9

10

11 12 13 14 15 16 17 18 19 20

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CYW20730

Figure 11. 64-pin BGA Ball Map

1

2

3

4

5

6

7

8

P26/

PWM0

P29/

PWM3

P39/

XTALI32K

P9

P15

VDDO

P24

P20

P19

P16

P33

SCL

P3

A

B

C

D

E

A

B

C

D

E

P27/

PWM1

P28/

PWM2

P38/

XTALO32K

LDOIN

LDOOUT

VDDIF

VDDFE

RF

P12

P11

P10

VSS

P34

P21

P32

P5

P25

P18

P37

P14

P36

VSS

P30

P8

P7

P35

VSS

P6

VDDO

P31

P23

P13

P0

SDA

F

UART_

TXD

RESET

_N

VSS

XTALO

P22

P1

TMC

G

H

G

H

UART_

RXD

VDDVCO

VDDPLL

XTALI

P17

VDDC

P4

P2

1

2

3

4

5

6

7

8

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CYW20730

3. Specifications

3.1 Electrical Characteristics

Table 10 shows the maximum electrical rating for voltages referenced to VDD pin.

Table 10. Maximum Electrical Rating

Rating

Symbol

Value

Unit

V

DC supply voltage for RF domain

DC supply voltage for core domain

DC supply voltage for VDDM domain (UART/I²C)

DC supply voltage for VDDO domain

DC supply voltage for VR3V

–

1.4

V

–

3.8

V

–

3.8

V

–

V

DC supply voltage for VDDFE

–

1.4

V

Voltage on input or output pin

–

VSS – 0.3 to VDD + 0.3

0 to +70

V

Operating ambient temperature range

Storage temperature range

Topr

Tstg

°C

–40 to +125

Table 11 shows the power supply characteristics for the range T_J= 0 to 125°C.

Table 11. Power Supply

Parameter

DC supply voltage for RF

Minimum^a

1.14

1.62

1.425

1.14

–

Typical

Maximum^a

1.26

Unit

V

1.2

–

DC supply voltage for Core

DC supply voltage for VDDM (UART/I²C)

1.26

V

3.63

V

DC supply voltage for VDDO

–

3.63

V

DC supply voltage for LDOIN

–

1.2^b

3.63

V

DC supply voltage for VDDFE

1.26

V

Supply noise for VDDO (peak-to-peak)

Supply noise for LDOIN (peak-to-peak)

–

100

mV

–

100

a. Overall performance degrades beyond minimum and maximum supply voltages.

b. 1.2V for Class 2 output with internal VREG.

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CYW20730

Table 13 shows the digital level characteristics for (VSS = 0V).

Table 12. LDO Regulator Electrical Specifications

Parameter

Input voltage range

Default output voltage

Conditions

Min

1.425

–

Typ

Max

3.63

–

Unit

V

–

1.2

V

Range

0.8

–

1.4

–

V

Output voltage

Step size

40 or 80

mV

%

Accuracy at any step

–5

–

+5

30

Load current

–

mA

%V_O/V

Line regulation

Vin from 1.425 to 3.63V, I_load= 30 mA

–0.2

0.2

I_loadfrom 1 µAto 30 mA, Vin = 3.3V, Bonding

R = 0.3

Load regulation

–

0.1

0.2

%V_O/mA

No load @Vin = 3.3V

*Current limit enabled

Quiescent current

–

6

5

–

µA

nA

Power-down current

Vin = 3.3V, worst@70°C

200

Table 13. ADC Specifications

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

ADC Characteristics

Number of Input

channels

–

28

–

Channel switching rate

Input signal range

Reference settling time

Input resistance

f_ch

V_inp

–

0

–

133.33

kch/s

V

–

3.63

Changing refsel

7.5

–

s

R_inp

C_inp

f_C

Effective, single-ended

500

–

k

pF

Input capacitance

Conversion rate

–

5

5.859

5.35

–

187

170.7

–

kHz

s

Conversion time

Resolution

T_C

R

–

16

bits

See Table 2

on page 9

Effective number of bits

–

Absolute voltage

measurement error

Using on-chip ADC firmware driver

±2

%

Current

I

P

I_avdd1p2+ I_avdd3p3

–

1.5

–

1

–

mA

mW

nA

Power

–

Leakage current

Power-up time

Integral nonlinearity³

Differential nonlinearity^a

I_leakage

T_powerup

INL

T = 25°C

–

100

200

1

–

s

LSB^a

–1

–

DNL

–

1

a. LSBs are expressed at the 10-bit level.

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CYW20730

Table 14. Digital Level^a

Characteristics

Symbol

VIL

Min

Typ

–

Max

0.4

–

Unit

V

Input low voltage

–

Input high voltage

VIH

0.75 × VDDO

–

V

Input low voltage (VDDO = 1.62V)

Input high voltage (VDDO = 1.62V)

Output low voltage^b

VIL

–

0.4

–

V

VIH

1.2

–

V

VOL

VOH

CIN

–

0.4

–

V

Output high voltage^b

VDDO – 0.4

–

V

Input capacitance (VDDMEM domain)

0.12

–

pF

a. This table is also applicable to VDDMEM domain.

b. At the specified drive current for the pad.

Table 15. Current Consumption ^a

Operational Mode

Conditions

Typ

Max

26.6

Unit

Receive

Receiver and baseband are both operating, 100% ON.

–

mA

24 at 2 dBm, 19 at

0 dBm

Transmit

Transmitter and baseband are both operating, 100% ON.

–

mA

Average current when the device is in the transmit state,

100% utilization of available slots.

DM1

DH1

15.2

16.67

–

Average current when the device is in the receive state,

100% utilization of available slots.

Sleep

Internal LPO is in use.

28.4

1.5

–

A

mA

A

HIDOFF

–

Sniff mode, 11.25 ms

Sniff mode, 22.5 ms

Sniff mode, 60 ms

Sniff mode, 100 ms

Sniff mode, 495 ms

Slave

2.8

1.27

750

500

125

a. Current consumption measurements are taken at VBAT with the assumption that VBAT is connected to VDDIO and LDOIN.

Caution: This device is susceptible to permanent damage from electrostatic discharge (ESD). Proper precautions are required during

handling and mounting to avoid excessive ESD.

Table 16. ESD Tolerance

Model

Tolerance

± 2000V

± 400V

Human Body Model (HBM)

Charged Device Model (CDM)

Machine Model (MM)

± 150V

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CYW20730

3.2 RF Specifications

Table 17. Receiver RF Specifications

Parameter

Mode and Conditions

Min

Typ

Max

Unit

Receiver Section

Frequency range

RX sensitivity (standard)

RX sensitivity (low current)

Input IP3

–

2402

–

–88.0

–84.0

–

2480

MHz

dBm

–84.0

GFSK, 0.1%BER, 1 Mbps

–

–16

–10

Maximum input

–

Interference Performance

C/I cochannel

GFSK, 0.1%BER^a

–

11.0

0.0

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

C/I 3 MHz adjacent channel

C/I image channel

GFSK, 0.1%BER^a

GFSK, 0.1%BER^b

GFSK, 0.1%BER^a

–30.0

–40.0

–9.0

C/I 1 MHz adjacent to image channel GFSK, 0.1%BER^a

–20.0

Out-of-Band Blocking Performance (CW)^b

30 MHz to 2000 MHz

2000 MHz to 2399 MHz

2498 MHz to 3000 MHz

3000 MHz to 12.75 GHz

0.1%BER

–

–10.0

–27

–

dBm

0.1%BER

–27

–10.0

Spurious Emissions

30 MHz to 1 GHz

–

–57.0

–55.0

dBm

1 GHz to 12.75 GHz

a. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).

b. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).

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Table 18. Transmitter RF Specifications

Parameter

Min

Typ

Max

Unit

Transmitter Section

Frequency range

2402

–6.0

–

2480

4.0

–

MHz

dBm

dB

Output power adjustment range

Default output power

Output power variation

20 dB bandwidth

4.0

2.0

900

–

1000

kHz

Adjacent Channel Power

|M – N| = 2

–

–20

–40

dBm

|M – N| 3

Out-of-Band Spurious Emission

30 MHz to 1 GHz

–

–36.0

–30.0

–47.0

dBm

1 GHz to 12.75 GHz

1.8 GHz to 1.9 GHz

5.15 GHz to 5.3 GHz

–

LO Performance

Frequency Drift

Initial carrier frequency tolerance

–

±75

kHz

DH1 packet

DH3 packet

DH5 packet

Drift rate

–

±25

±40

20

kHz

kHz/50 µs

Frequency Deviation

Average deviation in payload

(sequence used is 00001111)

140

–

175

kHz

Maximum deviation in payload

(sequence used is 10101010)

115

–

1

–

kHz

Channel spacing

MHz

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3.3 Timing and AC Characteristics

In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.

3.3.1 UART Timing

Table 19. UART Timing Specifications

Reference

Characteristics

Min

–

Max

24

10

2

Unit

Baud out

cycles

1

2

3

Delay time, UART_CTS_N low to UART_TXD valid

Setup time, UART_CTS_N high before midpoint of stop bit

Delay time, midpoint of stop bit to UART_RTS_N high

–

ns

Baud out

cycles

–

Figure 12. UART Timing

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3.3.2 SPI Timing

The SPI interface supports clock speeds up to 12 MHz with VDDIO ≥ 2.2V. The supported clock speed is 6 MHz when 2.2V ≥ VDDIO

≥ 1.62V.

Figure 13 shows the timing diagram. SPI timing values for different values of SCLK and VDDM are shown in Table 20, Table 21 on

page 38, Table 22 on page 38, Table 23 on page 39.

Figure 13. SPI Timing Diagram

5

6

CS

SCLK

Mode 1

SCLK

Mode 3

2

4

1

MSB

LSB

MOSI

MISO

3

Invalid bit

Table 20. SPI1 Timing Values—SCLK = 12 MHz and VDDM = 3.2V^a

Reference

Characteristics

Symbol

Min

Typical^b

Max

Unit

Output setup time, from MOSI 

data valid to sample edge of SCLK

1

Tds_mo

–

20

–

ns

Output hold time, from sample

2

3

Tdh_mo

Tds_mi

Tdh_mi

–

63

–

ns

edge of SCLK to MOSI data update

Input setup time, from MISO data valid

to sample edge of SCLK

TBD

Input hold time, from sample 

edge of SCLK to MISO data update

4

–

TBD

–

ns

5^c

6^c

Time from CS assert to first SCLK edge Tsu_cs

½ SCLK period – 1

½ SCLK period

–

Time from first SCLK edge to CS

deassert

Thd_cs

a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The speed can be adjusted to as low as 400 Hz by

configuring the firmware.

b. Typical timing based on 20 pF/1 MΩ load and SCLK = 12 MHz.

c. CS timing is firmware controlled.

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Table 21. SPI1 Timing Values—SCLK = 6 MHz and VDDM = 1.62V^a

Reference

Characteristics

Symbol

Min

Typical^b

Max

Unit

Output setup time, from MOSI data valid

to sample edge of SCLK

1

Tds_mo

–

41

–

ns

Output hold time, from sample 

2

3

Tdh_mo

Tds_mi

–

120

–

ns

edge of SCLK to MOSI data update

Input setup time, from MISO 

data valid to sample edge of SCLK

TBD

Input hold time, from sample 

4

Tdh_mi

Tsu_cs

Thd_cs

–

TBD

–

ns

edge of SCLK to MISO data update

5^c

6^c

Time from CS assert to first SCLK edge

½ SCLK period – 1

½ SCLK period

–

Time from first SCLK edge to CS

deassert

a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The speed can be adjusted to as low as 400 Hz by

configuring the firmware.

b. Typical timing based on 20 pF/1 MΩ load and SCLK = 6 MHz.

c. CS timing is firmware controlled.

Table 22. SPI2 Timing Values—SCLK = 12 MHz and VDDM = 3.2V^a

Reference

Characteristics

Symbol

Min

Typical^b

Max

Unit

Output setup time, from MOSI 

data valid to sample edge of SCLK

1

Tds_mo

–

26

–

ns

Output hold time, from sample 

2

3

Tdh_mo

Tds_mi

–

56

–

ns

edge of SCLK to MOSI data update

Input setup time, from MISO 

data valid to sample edge of SCLK

TBD

Input hold time, from sample 

4

Tdh_mi

Tsu_cs

Thd_cs

–

TBD

–

ns

edge of SCLK to MISO data update

5^c

6^c

Time from CS assert to first SCLK edge

½ SCLK period – 1

½ SCLK period

–

Time from first SCLK edge to CS

deassert

a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The speed can be adjusted to as low as 400 Hz by

configuring the firmware.

b. Typical timing based on 20 pF//1 MΩ load and SCLK = 12 MHz.

c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.

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CYW20730

Table 23. SPI2 Timing Values—SCLK = 6 MHz and VDDM = 1.62V^a

Reference

Characteristics

Symbol

Min

Typical^b

Max

Unit

Output setup time, from MOSI 

1

Tds_mo

–

50

–

ns

data valid to sample edge of SCLK

Output hold time, from sample 

edge of SCLK to MOSI data update

2

3

Tdh_mo

Tds_mi

–

120

ns

Input setup time, from MISO 

data valid to sample edge of SCLK

TBD

Input hold time, from sample 

4

Tdh_mi

Tsu_cs

Thd_cs

–

TBD

–

ns

edge of SCLK to MISO data update

5^c

6^c

Time from CS assert to first SCLK edge

½ SCLK period – 1

½ SCLK period

–

Time from first SCLK edge to CS

deassert

a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The speed can be adjusted to as low as 400 Hz by

configuring the firmware.

b. Typical timing based on 20 pF//1 MΩ load and SCLK = 6 MHz.

c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.

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CYW20730

3.3.3 BSC Interface Timing

Table 24. BSC Interface Timing Specifications

Reference

Characteristics

Min

Max

Unit

100

400

800

1000

–

1

Clock frequency

–

kHz

2

3

START condition setup time

START condition hold time

Clock low time

650

280

650

280

0

ns

–

4

–

5

Clock high time

–

6

Data input hold time^a

Data input setup time

STOP condition setup time

Output valid from clock

Bus free time^b

–

7

100

280

–

8

–

9

400

–

10

650

a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

b. Time that the cbus must be free before a new transaction can start.

Figure 14. BSC Interface Timing Diagram

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CYW20730

4. Mechanical Information

Figure 15. 32-Pin QFN Package

Document Number: 002-14824 Rev. *J

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CYW20730

Figure 16. 40-pin QFN Package

Document Number: 002-14824 Rev. *J

Page 42 of 50

CYW20730

Figure 17. 64-pin FBGA Package

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CYW20730

4.1 Tape Reel and Packaging Specifications

Table 25. CYW20730 5 × 5 × 1 mm QFN, 32-Pin Tape Reel Specifications

Parameter

Quantity per reel

Reel diameter

Value

2500 pieces

13 inches

7 inches

12 mm

Hub diameter

Tape width

Tape pitch

8 mm

Table 26. CYW20730 6 × 6 × 1 mm QFN, 40-Pin Tape Reel Specifications

Parameter

Quantity per reel

Reel diameter

Value

4000 pieces

13 inches

4 inches

16 mm

Hub diameter

Tape width

Tape pitch

12 mm

Table 27. CYW20730 7 × 7 × 0.8 mm WFBGA, 64-Pin Tape Reel Specifications

Parameter

Quantity per reel

Reel diameter

Value

2500 pieces

13 inches

4 inches

16 mm

Hub diameter

Tape width

Tape pitch

12 mm

The top left corner of the CYW20730 package is situated near the sprocket holes, as shown in Figure 18.

Figure 18. Pin 1 Orientation

Pin 1: Top left corner of package toward sprocket holes

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CYW20730

5. Ordering Information

Table 28. Ordering Information

Part Number

CYW20730A2KML2G

CYW20730A2KMLG

CYW20730A2KFBG

CYW20730A1KML2G

CYW20730A1KMLG

CYW20730A1KFBG

Package

Ambient Operating Temperature

32-pin QFN

40-pin QFN

64-pin BGA

32-pin QFN

40-pin QFN

64-pin BGA

0°C to 70°C

Document Number: 002-14824 Rev. *J

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CYW20730

A. Appendix: Acronyms and Abbreviations

The following list of acronyms and abbreviations may appear in this document.

Term

Description

ADC

AFH

AHB

APB

APU

analog-to-digital converter

adaptive frequency hopping

advanced high-performance bus

advanced peripheral bus

audio processing unit

Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable

Broadcom Serial Control

Bluetooth controller

ARM7TDMI-S™

BSC

BTC

COEX

DFU

DMA

EBI

coexistence

device firmware update

direct memory access

external bus interface

Host Control Interface

high voltage

HCI

HV

IDC

initial digital calibration

intermediate frequency

interrupt request

IF

IRQ

JTAG

LCU

LDO

LHL

Joint Test Action Group

link control unit

low drop-out

lean high land

LPO

LV

low power oscillator

LogicVision™

MIA

multiple interface agent

pulse code modulation

phase locked loop

PCM

PLL

PMU

POR

PWM

QD

power management unit

power-on reset

pulse width modulation

quadrature decoder

RAM

RF

random access memory

radio frequency

ROM

RX/TX

SPI

read-only memory

receive, transmit

serial peripheral interface

software

SW

UART

UPI

universal asynchronous receiver/transmitter

µ-processor interface

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CYW20730

Term

Description

WD

watchdog

A.1 References

The references in this section may be used in conjunction with this document.

Note: Cypress provides customer access to technical documentation and software through its Customer Support Portal (CSP) and

Downloads & Support site (see IoT Resources on page 3).

For documents, replace the “x” in the document number with the largest number available in the repository to ensure that you have

the most current version of the document.

Document Name

Broadcom Number

Cypress Number

Items

[1] Single-Chip Bluetooth® Transceiver and Baseband Processor

20702-DS10x-R

002-14772

Document Number: 002-14824 Rev. *J

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CYW20730

Document History

Document Title: CYW20730 Single-Chip Bluetooth Transceiver for Wireless Input Devices

Document Number: 002-14824

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

20730-DS100-RI:

Initial release

**

–

04/27/2010

20730-DS101-R:

Added:

•

“Shutter Control for 3D Glasses” on page 10.

“Infrared Modulator” on page 10.

“Infrared Learning” on page 11.

“Triac Control” on page 12.

“Broadcom Proprietary Control Signalling and Triggered Baseband Fast Connect” on

page 12.

•

Figure 5: “Internal Reset Timing,” on page 17.

Figure 6: “External Reset Timing,” on page 17.

Figure 10: “40-pin QFN Ball Map,” on page 33.

Figure 11: “64-pin BGA Ball Map,” on page 34.

“SPI Timing” on page 41.

Figure 16: “40-pin QFN,” on page 44.

Figure 17: “64-pin FBGA,” on page 45.

Revised:

*A

–

06/25/2010

“Microprocessor Unit” on page 16.

Table 6: “Pin Descriptions,” on page 25.

Table 11: “ADC Specifications,” on page 36.

Table 14: “Receiver RF Specifications,” on page 38.

Table 15: “Transmitter RF Specifications,” on page 39.

Table 21: “Ordering Information,” on page 50.

20730-DS102-R:

Added:

•

Table 1: “ADC Modes,” on page 18

Revised:

•

Figure 1: “Functional Block Diagram,” on page 2

“ADC Port” on page 17

“Internal LDO Regulator” on page 22

“UART Interface” on page 23

Table 6: “XTAL Oscillator Characteristics,” on page 25

Table 8: “GPIO Pin Descriptions,” on page 30

Table 10: “Power Supply,” on page 39

Table 11: “LDO Regulator Electrical Specifications,” on page 40

Table 12: “ADC Specifications,” on page 41

Table 14: “Current Consumption,” on page 42

Table 15: “Receiver RF Specifications,” on page 43

Table 16: “Transmitter RF Specifications,” on page 44

Table 18: “SPI Interface Timing Specifications,” on page 46

Table 21: “BCM20730 6 × 6 × 1 mm QFN, 40-Pin Tape Reel Specifications,” on

page 52

*B

–

03/23/2011

•

Table 22: “BCM20730 7 × 7 × .8 mm WFBGA, 64-Pin Tape Reel Specifications,” on

page 52

Deleted:

•

Placeholder for Figure 4: Triac Control

Placeholder for Figure 18: BCM20730, 6 x 6 QFN Package Tray

Placeholder for Figure 19: BCM20730, 7 x 7 FBGA Package Tray

20730-DS103-R:

Revised:

*C

*D

–

04/06/2011

05/09/2011

•

Table 14: “Current Consumption,” on page 42

Table 23: “Ordering Information,” on page 54

20730-DS104-R:

Revised:

•

Figure 1: “Functional Block Diagram,” on page 2

“ADC Port” on page 17

Table 10: “Power Supply,” on page 39

Document Number: 002-14824 Rev. *J

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CYW20730

Document Title: CYW20730 Single-Chip Bluetooth Transceiver for Wireless Input Devices

Document Number: 002-14824

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

20730-DS105-R:

Added:

•

Figure 9: “32-Pin QFN Ball Map,” on page 39

Figure 16: “32-Pin QFN Package,” on page 52

Table 20: “BCM20730 5 × 5 × 1 mm QFN, 32-Pin Tape Reel Specifications,” on

page 55

Revised:

•

General Description and Features on Cover

Figure 1: “Functional Block Diagram,” on page 2

“ADC Port” on page 17

Table 2: “BCM20730 First SPI Set (Master Mode),” on page 18

Figure 5: “External Reset Timing,” on page 22

“GPIO Port” on page 27

“BBC Power Management” on page 29

Table 7: “Pin Descriptions,” on page 30

Table 8: “GPIO Pin Descriptions,” on page 32

Table 12: “ADC Specifications,” on page 44

*E

–

06/29/2011

20730-DS106-R:

Changed from a Preliminary Data Sheet to a Data Sheet.

*F

–

09/20/2011

10/10/2012

20730-DS107-R:

Revised:

*G

•

“SPI Timing” on page 49

20730-DS108-R:

Revised:

•

<Cross-Ref>Section 1.3: “Shutter Control for 3D Glasses,” on page 6

Table 28, “Ordering Information,” on page 45

*H

–

09/09/2013

Added:

•

Table 16, “ESD Tolerance,” on page 33

*I

5522944

5700376

UTSV

11/16/2016 Updated to Cypress template

*J

AESATMP7

04/25/2017 Updated Cypress Logo and Copyright.

Document Number: 002-14824 Rev. *J

Page 49 of 50

CYW20730

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP| PSoC 6

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Lighting & Power Control

Memory

Technical Support

cypress.com/powerpsoc

cypress.com/memory

cypress.com/psoc

cypress.com/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/touch

cypress.com/usb

cypress.com/wireless

50

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-14824 Rev. *J

Revised April 25, 2017

Page 50 of 50

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