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IZ74LV164

型号：

IZ74LV164

描述：

8位串行输入/并行输出移位寄存器[ 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER ]

品牌：

INTEGRAL[ INTEGRAL CORP. ]

页数：

6 页

PDF大小：

49 K

下载PDF手册
TECHNICAL DATA  
IN74LV164  
8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER  
The IN74LV164 is a low-voltage Si-gate CMOS device and is pin  
and function compatible with the IN74HC/HCT164.  
N SUFFIX  
PLASTIC DIP  
The IN74LV164 is an 8-bit edge-triggered shift register with serial  
data entry and an output from each of the eight stages. Data is entered  
serially through one of two inputs (DSA or DSB); either input can be  
used as an active HIGH enable for data entry through the other input.  
Both inputs must be connected together or an unused input must be tied  
HIGH.  
Data shifts one place to the right on each LOW-to-HIGH transition  
of the clock (CP) input and enters into Q0, which is the logical AND of  
the two data inputs (DSA, DSB ) that existed one set-up time prior to the  
rising clock edge.  
14  
1
D SUFFIX  
SO  
14  
1
ORDERING INFORMATION  
IN74LV164N  
IN74LV164D  
IZ74LV164  
Plastic DIP  
SOIC  
chip  
A LOW on the master reset (MR) input overrides all other inputs  
and clears the register asynchronously, forcing all outputs LOW.  
TA = -40° to 125° C for all packages  
·
·
·
·
·
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 1.2 to 5.5 V  
Low Input Current: 1.0 mA, 0.1 mÀ at Ò = 25 °Ñ  
Output Current: 6 mA at VCC = 3.0 V; 12 mA at VCC = 4.5 V  
High Noise Immunity Characteristic of CMOS Devices  
PIN ASSIGNMENT  
DSA  
DSB  
Q0  
1
2
3
4
5
6
7
14 VCC  
13 Q7  
12 Q6  
LOGIC DIAGRAM  
Q1  
11  
Q5  
Q2  
10 Q4  
1
SERIAL  
DATA  
INPUTS DSB  
2
4
5
DSA  
Q0  
Q3  
9
8
MR  
CP  
DATA  
2
Q1  
Q2  
GND  
6
PARALLEL  
DATA  
OUTPUTS  
Q3  
Q4  
10  
11  
12  
13  
Q5  
Q6  
Q7  
8
FUNCTION TABLE  
CP  
Inputs  
Outputs  
MR  
L
CP  
DSA DSB Q0 Q1 ... Q7  
9
MR  
X
X
L
X
L
L
L
L
L
H
L … L  
Q0 ... Q6  
Q0 ... Q6  
Q0 ... Q6  
Q0 ... Q6  
H
PIN 14=VCC  
PIN 7 = GND  
H
L
H
L
H
H
H
H
H
H = high voltage level  
L = low voltage level  
X = don’t care  
INTEGRAL  
1
IN74LV164  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
-0.5 to + 7.0  
±20  
Unit  
V
VCC  
DC supply voltage  
1
IIK  
*
DC Input diode current  
DC Output diode current  
mA  
mA  
mA  
mA  
mA  
mW  
2
IOK  
*
±50  
IO *3  
DC Output source or sink current  
VCC current  
±25  
ICC  
±50  
IGND  
PD  
GND current  
±50  
Power dissipation per package: *4  
Plastic DIP  
SO  
750  
500  
Tstg  
TL  
Storage Temperature  
-65 to +150  
260  
°C  
°C  
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO  
Package) from Case for 4 Seconds  
*Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
*1 V < -0.5 V or V > VCC + 0.5 V.  
I
I
*2 VO < -0.5 V or VO > VCC + 0.5 V.  
*3 -0.5 V < VO < VCC + 0.5 V.  
*4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C  
SO Package: : - 8 mW/°C from 70° to 125°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Min  
1.2  
0
Max  
5.5  
Unit  
V
VCC  
DC Supply Voltage  
Input Voltage  
V
I
VCC  
V
VO  
TA  
Output Voltage  
0
VCC  
V
Operating Temperature, All Package Types  
Input Rise and Fall Time (Figure 1)  
-40  
+125  
°C  
ns  
tr, tf  
1.0 V £ VCC < 2.0 V  
2.0 V £ VCC < 2.7 V  
2.7 V £ VCC < 3.6 V  
3.6 V £ VCC £ 5.5 V  
0
0
0
0
500  
200  
100  
50  
This device contains protection circuitry to guard against damage due to high static voltages or electric  
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages  
to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range GND£(V or  
IN  
IN  
VOUT)£VCC.  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused  
outputs must be left open.  
INTEGRAL  
2
IN74LV164  
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)  
Test  
VCC  
V
Guaranteed Limit  
Symbol  
Parameter  
conditions  
25°C to -40°C  
85°C  
125°C  
Unit  
min  
max min max  
min  
max  
V
IH  
HIGH level input  
voltage  
1.2  
2.0  
2.7  
3.0  
3.6  
4.5  
5.5  
0.9  
1.4  
2.0  
2.0  
2.0  
-
-
-
-
-
-
-
0.9  
1.4  
2.0  
2.0  
2.0  
-
-
-
-
-
-
-
0.9  
1.4  
2.0  
2.0  
2.0  
-
-
-
-
-
-
-
V
3.15  
3.85  
3.15  
3.85  
3.15  
3.85  
V
LOW level input  
voltage  
1.2  
2.0  
2.7  
3.0  
3.6  
4.5  
5.5  
-
-
-
-
-
-
-
0.3  
0.6  
0.8  
0.8  
0.8  
-
-
-
-
-
-
-
0.3  
0.6  
0.8  
0.8  
0.8  
-
-
-
-
-
-
-
0.3  
0.6  
0.8  
0.8  
0.8  
V
V
IL  
1.35  
1.65  
1.35  
1.65  
1.35  
1.65  
VOH  
HIGH level output V = V or V  
IL  
voltage  
1.2  
2.0  
2.7  
3.0  
3.6  
4.5  
5.5  
1.05  
1.85  
2.55  
2.85  
3.45  
4.35  
5.35  
-
-
-
-
-
-
-
1.0  
1.8  
2.5  
2.8  
3.4  
4.3  
5.3  
-
-
-
-
-
-
-
1.0  
1.8  
2.5  
2.8  
3.4  
4.3  
5.3  
-
-
-
-
-
-
-
I
IH  
IO = -100 mÀ  
V = V or V  
IL  
3.0  
2.48  
-
2.40  
-
2.20  
-
V
V
V
I
IH  
IO = -6.0 mÀ  
V = V or V  
IL  
4.5  
3.70  
-
3.60  
-
3.50  
-
I
IH  
IO = -12.0 mÀ  
LOW level output V = V or V  
IL  
VOL  
1.2  
2.0  
2.7  
3.0  
3.6  
4.5  
5.5  
-
-
-
-
-
-
-
0.15  
0.15  
0.15  
0.15  
0.15  
0.15  
0.15  
-
-
-
-
-
-
-
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
-
-
-
-
-
-
-
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
I
IH  
voltage  
IO = 100 mÀ  
V = V or V  
IL  
3.0  
-
0.33  
-
0.4  
-
0.5  
V
V
I
IH  
IO = 6.0 mÀ  
V = V or V  
IL  
4.5  
-
0.40  
-
0.55  
-
0.65  
I
IH  
IO = 12.0 mÀ  
II  
Input current  
V = VCC or 0 V  
5.5  
5.5  
-
-
±0.1  
-
-
±1.0  
-
-
±1.0  
mÀ  
mÀ  
I
ICC  
Supply current  
V =VCC or 0 V  
I
8.0  
80  
160  
IO = 0 mÀ  
ICC1  
Supply current  
V =VCC – 0.6 V  
I
2.7  
3.6  
-
0.2  
-
0.5  
-
0.85  
mÀ  
INTEGRAL  
3
IN74LV164  
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf= 2.5 ns, RL = 1 kW)  
Test  
VCC  
V
Guaranteed Limit  
25°C to -40°C 85°C  
max min max min  
Symbol  
Parameter  
conditions  
125°C  
Unit  
min  
max  
tPHL, tPLH Propagation delay , CP to V = 0 V or V  
1.2  
2.0  
2.7  
3.0  
4.5  
-
-
-
-
-
150  
30  
23  
18  
15  
-
-
-
-
-
180  
39  
29  
23  
19  
-
-
-
-
-
210  
49  
36  
29  
24  
ns  
I
1
Qn  
Figure 1 and 4  
tPHL  
Propagation delay , MR to V = 0 V or V  
1.2  
2.0  
2.7  
3.0  
4.5  
-
-
-
-
-
150  
30  
23  
18  
15  
-
-
-
-
-
180  
39  
29  
23  
19  
-
-
-
-
-
210  
49  
36  
29  
24  
ns  
ns  
I
1
Qn  
Figure 1 and 4  
tw  
Pulse Width, CP or MR  
V = 0 V or V  
1.2  
2.0  
2.7  
3.0  
4.5  
100  
28  
21  
17  
14  
-
-
-
-
-
130  
34  
25  
20  
17  
-
-
-
-
-
160  
41  
30  
24  
20  
-
-
-
-
-
I
1
Figure 1  
tsu  
Setup Time, DSA or DSB V = 0 V or V  
1.2  
2.0  
2.7  
3.0  
4.5  
60  
19  
13  
11  
9
-
-
-
-
-
80  
22  
16  
13  
11  
-
-
-
-
-
100  
26  
19  
15  
13  
-
-
-
-
-
ns  
I
1
to CP  
Figure 3  
th  
Hold Time, DSA or DSB to V = 0 V or V  
1.2  
2.0  
2.7  
3.0  
4.5  
50  
5
5
5
5
-
-
-
-
-
50  
5
5
5
5
-
-
-
-
-
50  
5
5
5
5
-
-
-
-
-
ns  
I
1
CP  
Figure 3  
trec  
Recovery Time, MR to CP V = 0 V or V  
1.2  
2.0  
2.7  
3.0  
4.5  
70  
15  
11  
9
-
-
-
-
-
100  
19  
14  
11  
10  
-
-
-
-
-
130  
24  
18  
14  
12  
-
-
-
-
-
ns  
I
1
Figure 2  
8
fmax  
Clock Frequency  
Input capacitance  
V = 0 V or V  
Figure 1 and 4  
1.2  
2.0  
2.7  
3.0  
4.5  
-
-
-
-
-
2
-
-
-
-
-
1
-
-
-
-
-
1
MHz  
I
1
16  
22  
27  
32  
14  
19  
24  
27  
12  
16  
20  
24  
CI  
5.0  
5.5  
-
-
7.0  
80  
-
-
-
-
-
-
-
-
pF  
pF  
CPD  
Power dissipation  
capacitance  
V = 0 V or VCC  
I
INTEGRAL  
4
IN74LV164  
tw  
(2)  
V1  
t
t
r
f
(2)  
(1)  
V1  
MR  
Q
VM  
90%  
CP  
(1 )  
VM  
GND  
10%  
GND  
tPHL  
t w  
VOH  
VOL  
( 1)  
VM  
1/f  
max  
tPLH  
tPHL  
VOH  
t rec  
Q
(1 )  
VM  
(2)  
V1  
VOL  
(1)  
CP  
VM  
GND  
Figure 1. Switching Waveforms  
Figure 2. Switching Waveforms  
TEST POINT  
VALID  
(2)  
V
1
(1 )  
OUTPUT  
VM  
DEVICE  
UNDER  
TEST  
DSA or DSB  
CP  
GND  
t
t
h
*
su  
R
(2)  
L
C
L
V
1
( 1)  
VM  
GND  
* Includes all probe and jig capacitance  
Figure 3. Switching Waveforms  
(1)  
Figure 4. Test Circuit  
Note:  
VM = 1.5 V at VCC = 2.7 V  
VM = 0.5 ×VCC at VCC =1.2 V, 2.0 V, 3.0 V, 4.5 V  
(2)  
V = VCC at VCC =1.2 V, 2.0 V, 2.7 V, 4.5 V  
1
V = 2.7 V at VCC = 3.0 V  
1
TIMING DIAGRAM  
CP  
DSA  
DSB  
MR  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
INTEGRAL  
5
IN74LV164  
CHIP PAD DIAGRAM  
06  
08  
09  
07  
05  
04  
03  
10  
11  
12  
02  
14  
01  
13  
Y
Chip marking  
(0,0)  
X
LV164  
1.71 + 0.03  
Location of marking (mm): left lower corner x= 0.960, y= 0.130.  
Chip thickness: 0.46 ± 0.02 (0.35 ± 0.02) mm.  
PAD LOCATION  
Location (left lower corner), mm  
Pad No  
Symbol  
Pad size, mm  
X
1.172  
1.486  
1.486  
1.486  
1.486  
1.486  
0.978  
0.440  
0.127  
0.127  
0.127  
0.127  
0.127  
0.635  
Y
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
DSA  
DSB  
Q0  
0.131  
0.100 õ 0.100  
0.100 õ 0.100  
0.100 õ 0.100  
0.100 õ 0.100  
0.100 õ 0.100  
0.100 õ 0.100  
0.100 õ 0.100  
0.100 õ 0.100  
0.100 õ 0.100  
0.100 õ 0.100  
0.100 õ 0.100  
0.100 õ 0.100  
0.100 õ 0.100  
0.100 õ 0.100  
0.131  
0.363  
0.531  
0.689  
0.885  
0.885  
0.885  
0.885  
0.653  
0.485  
0.326  
0.131  
0.131  
Q1  
Q2  
Q3  
GND  
CP  
MR  
Q4  
Q5  
Q6  
Q7  
VCC  
Note: Pad location is given as per passivation layer  
INTEGRAL  
6
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