PIN NAME
FUNCTION
SYMBOL
CLKI
An input pin for reference clock,
to DOUT (pin 3) of timing LSI
) or
DO (pin 3) of timing LSI; following frequencies ap-
pear on this pin;
Main clock
27
At
mode : 9.534964 MHz when CKMD = L level
12.713285 MHzwhen CKMD = H level
At PAL mode : 9.656250 MHz when CKMD = L level
12.875 MHz when CKMD = H level
—
—
—
Power supply
Vcc
Supply +5 V
28
29
Phase comparator output for input signals RPI (pin
32) and (pin 30). When is advanced, output
is Low level. When CPI is delayed, output is High
level, When phases are equal, the terminal imped-
ance is High.
Phase comparator
output
TO
An input pin for comparison horizontal signal to the
phase comparator. Connect to SCHD (pin 33) when
comparator is used. Set to L level when comparator
is not used.
Horizontal comparison
input
–
30
31
The pulse occurs at the start of lines. Connect to
timing LSI.
Horizontal drive pulse
HD
RPI
o
An input pin for the reference horizontal signal to
the phase comparator. Connect to HD (pin 31) when
comparator is used, Set to L level when comparator
is not used.
Horizontal reference
input
32
A horizontal synchronization pulse obtained by di-
viding 4FSC (pin 43).
At NTSC mode : dividing into 1 /91 O 4FSC.
At PAL mode : dividing into
135 4FSC ordi-
33
34
SCHD
o
Subcarrier HD
V drive pulse
narily and dividing into 1/1 137
4FSC during one horizontal pe-
riod within the V blanking,
The pulse occurs at the start of every field. Con-
nect to VDI (pin 2) of timing
(Pin of timing
) or VDI
VD
0
The pulse is used for detecting field.
At NTSC mode : 1st field; LOW
2nd field; HIGH
At PAL mode : 1st and 3rd field; LOW
2nd and 4th field; HIGH
Filed index
35
36
o
When the input is High, BCPI (pin 37) and BCP2
(pin 36) are Low.
Blanking clamp pulse
CPBL
