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LZ93BE0

型号:

LZ93BE0

描述:

定时脉冲发生器LSI的CCD[ Timing Pulse Generator LSI for CCD ]

品牌:

SHARP[ SHARP ELECTRIONIC COMPONENTS ]

页数:

9 页

PDF大小:

400 K

LZ93BE0  
Timing Pulse Generator  
for  
PIN CONNECTIONS  
20-PIN MFP  
DESCRIPTION  
The LZ93BE0 is a CMOS timing generator LSI  
which provides horizontal transfer pulse, reset  
pulse, and sample-hold pulse used for separate  
camera, in combination with single-chip driver  
LSI (LZ95G55, LZ95G41 ) and timing LSI  
LZ93F50, LZ93N61 or  
TOP VIEW  
FH  
Vcc  
1
=
o
FCDS  
2
3
4
1 8 F S  
GND  
FEATURES  
FH2  
1 7 co  
1 6 c l  
5
between 270  
320000 pixels CCD  
between NTSC  
systems  
Single +5 power supply  
between normal and mirror-image  
pixels  
and  
HDI  
T V MD  
F R  
1 5  
1 4  
s o  
7
8
and PAL  
1 2 S LC T  
11 MI R  
9
G N D  
1 0  
Suitable for separate camera  
Package : 20-pin  
Designed for A-type and B-type CCD area sensors :  
A-type CCD area sensor : LZ2314J, LZ2324J, LZ231 32, LZ23232  
B-type CCD area sensor : LZ2414J, LZ2424J, LZ2313H5,  
LZ2323H5, LZ2413, LZ2423  
BLOCK DIAGRAM  
“in  
of  
by  
sheets, SHARP takes no  
latest version device  
any  
in  
using any of SHARPs  
shown  
256  
data  
etc  
SHARP order to  
using any SHARPs device’  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
Supply voltage  
SYMBOL  
RATING  
– 0.3 to  
–0 ,3 to  
-0 .3 to  
–20 to  
–55 to +150  
UNIT  
v
v
VI  
Vo  
+ 0 .3  
v
Topr  
‘c  
“c  
Operation temperature  
Storaae temperature  
DC CHARACTERISTICS  
PRAMETER  
Ta=–20 to  
TYP.  
CONDITIONS  
MIN.  
MAX.  
NOTE  
SYMBOL  
UNIT  
Input Low voltage  
1 . 5  
v
v
v
v
v
Input High voltage  
3.5  
2.2  
1.0  
+
Input High threshold voltage  
Input Low threshold voltage  
Hysteresis voltage  
3.8  
2.4  
Schmitt Buffer  
v
2
3
4
5
Input Low current  
Vl=o  
v
8.0  
4.0  
4.0  
4.0  
60  
Input High current  
Output High voltage  
Output Low voltage  
Output High voltage  
LOW  
1 , 0  
1
v
v
v
v
v
v
6
7
8
= 4  
0.4  
0.4  
0.4  
IOL = 8  
v 0 L 2  
High voltage  
Output Low voltage  
NOTES :  
1.  
to inputs (IC,  
2. Applied to  
3. Applied to inputs  
4. Applied to  
5. Applied to inputs  
6. Applied to output (0)  
Applied to output  
8 Applied to output (012M)  
NAME  
SYMBOL  
A horizontal transfer pulse for  
area sensor.  
area sensor,  
Horizontal transfer  
pulse 1  
1
FH  
I
012M  
08M  
to  
of CCD area sensor.  
A horizontal transfer pulse for  
Connect to HI of CCD area sensor. If the CCD  
area sensor which corresponds to Mirror mode is  
driven at Normal mode (MIR = L), its drive-pulse is  
Horizontal transfer  
pulse 1 B  
2
the same phase as the pulse of  
(pin 1), and it  
is the same phase as the pulse of FH2 (pin 4) at  
Mirror mode (MIR = H).  
A grounding pin.  
Ground  
3
4
GND  
FH2  
A horizontal transfer pulse for CCD area sensor.  
to HZ of CCD area sensor,  
Horizontal transfer  
pulse 2  
012M  
A horizontal transfer pulse for CCD area sensor.  
to  
area sensor which corresponds to Mirror mode is  
driven at Normal mode = L), its drive-pulse is  
the same phase as the pulse of FH2 (pin it  
of CCD area sensor. If the CCD  
Horizontal transfer  
pulse 2B  
5
08M  
is the same phase as the pulse of FH I (pin 1 ) at  
Mirror mode (MIR = H).  
Put in a horizontal reference pulse from  
to HD terminal of  
Horizontal reference  
pulse  
6
7
8
HDI  
TVMD  
FR  
An input-pin to select TV standards,  
L level : NTSC mode  
TV mode select  
Reset pulse  
H level or  
: PAL mode  
A reset pulse for CCD area sensor,  
of CCD area sensor through the DC offset circuit.  
to  
R
08M  
An input pin for reference clock.  
The frequencies are as follows :  
At EIA mode : 19.06993 MHz (1212 fH)  
Clock input  
9
At  
mode : 19.31250 MHz (1 236 fH)  
A grounding pin.  
10  
11  
Ground  
GND  
An input pin to select Mirror mode or Normal mode.  
L level : Normal Drive mode  
Mirror mode select  
H level or open : Mirror Drive mode  
An input pin to select the type of CCD area  
L level (A type)  
LZ2314Z, LZ23t42, LZ2313A9,  
LZ2324J, LZ2324Z, LZ23242, LZ2323A9,  
H level or open (B type)  
12  
CCD type select  
SLCT  
LZ2314BK,  
LZ2324BK,  
LZ2313H5, LZ2413  
LZ2323B5, LZ2323H5, LZ2423  
FUNCTION  
PIN NAME  
SYMBOL  
An input pin to select the phase of FCDS (pin 19)  
pulse and FS (pin 18) pulse.  
L level : adjustable  
Phase control terminal  
for FCDS and FS  
13  
H level or open : fixed  
An input pin to control the phase of FS (pin 18).  
Phase-adjust input  
for FS  
SO (pin  
pulse put in this terminal after make it  
14  
15  
18  
17  
delay with resistor and capacitor.  
An output pin to control the phase of FS (pin 18).  
Phase-adjust output  
for FS  
The output pulse put in  
(pin 14) after make it  
so  
cl  
o
delay with resistor and capacitor.  
An input pin to control the phase of FCDS (pin 19).  
(pin 17) pulse put in this terminal after make it  
delay with resistor and capacitor.  
Phase-adjust input  
for FCDS  
An output pin to control the phase of FCDS (pin 19).  
The output pulse put in Cl (pin 16) after make it  
delay with resistor and capacitor.  
Phase-adjust output  
for FCDS  
co  
o
o
A pulse to sample-hold the signal from CCD area  
sensor. The phase of FS is fixed if CH (pin 13)  
equals H level and it can be adjustable if CH (pin  
13) equals L level.  
Sample-hold pulse  
output  
FS  
18  
19  
A pulse to clamp the feed-through level form CCD  
area sensor. The phase of FCDS is fixed if CH (pin  
13) equals H level and it can be adjustable if CH  
CDS pulse output  
Power supply  
FCDS  
Vcc  
o
n
(pin  
equals L level.  
Supply +5 V power.  
: Input pin (CMOS level input)  
: Input pin (CMOS level input with pull-up resistor)  
: Input pin (CMOS  
input )  
O, 08M, 012M : Output pin  
NOTE :  
At the input pin, the rising edge of HDI (pin 6) is 20 ns shorter than that of CKI (pin 9).  
TIMING DIAGRAM  
NTSC(EIA) < A-TYPE, NORMAL MODE >  
1
clock = 52.4  
1212,0  
49  
114  
HDI  
CBLK  
CKI  
FH  
FR  
FCDS  
FS  
114  
120  
166  
210  
HDI  
CBLK  
CKI  
FH  
FH2  
X X  
X
X 1 2 1 2 3 4 5 6 7 8  
FR  
FCDS  
< A-TYPE, MIRROR MODE >  
1 clock  
= 52.4  
1212,0  
8
114  
CBLK  
FH  
FH2  
O B I X X X X X X  
FR  
n
FCDS  
FS  
116 120  
210  
CBLK  
CKI  
FH  
FR  
FCDS  
FS  
1 clock= 52.4 ns  
NTSC(EIA)  
B-TYPE, NORMAL MODE  
47  
1212,0  
HDI  
CBLK  
CKI  
I
FH  
1
FH2  
FH2B  
FR  
FCDS  
FS  
210  
163  
120  
14  
CBLK  
FH  
FH2  
FR  
FCDS  
FS  
1
clock  
ns  
B-TYPE, MIRROR MODE  
111 114  
1212,0  
3
HDI  
CBLK  
CKI  
FH  
FH2  
x
OBIXX  
X X  
FCDS  
FS  
210  
114  
120  
HDI  
,
CBLK  
CKI  
FH  
FH2  
OBI 512 510  
500 498 496 494 492  
OB1O  
0B20  
XX  
X X XOB28  
FCDS  
FS  
261  
1
clock  
=
51.8 ns  
114  
< A-TYPE, NORMAL MODE >  
48  
1236,0  
HDI  
CBLK  
FH  
B
FH2B  
0B4  
OB1O  
OB20  
0B28  
FR  
FCDS  
FS  
192  
234  
114 120  
HDI  
CBLK  
m
FH  
FH2  
I
u
J
FH2B  
X X X X 1 2 1 2 3 4 5 8 7 8  
1 4  
FR  
FCDS  
r
FS  
1 clock  
ns  
< A-TYPE, MIRROR MODE >  
114  
3
HDI  
CBLK  
FH  
FH2  
FH2B  
O B I X X X X X X  
FR  
FCDS  
FS  
234  
114  
20  
140  
I
CBLK  
CKI  
m
FH  
I
v
u
F HIB  
XX X  
OB20  
OB1O  
OB1 512 510  
506 504 502  
FR  
FCDS  
FS  
< B-TYPE, NORMAL MODE >  
1
c lo c k  
n s  
7 2 3 6 ,0  
4 7  
1 1 4  
HDI  
CBLK  
FH  
FH2 B  
OB4  
OB1 O  
FR  
FCDS  
FS  
1 1 4 1 2 0  
2 3 4  
HDI  
CBLK  
CKI  
FH  
FH2  
X X X X X X 1 2 1 2 3 4 5 6 7  
8
1 2 1 4  
FR  
FCDS  
FS  
< B-TYPE, MIRROR MODE >  
1
n s  
3
HDI  
CBLK  
CKI  
M
FH  
X X X  
FCDS  
FS  
1 1 4  
1 2 0  
1 3 5  
2 3 4  
CBLK  
FH  
L
OB1 O  
OBI 5 1 2 5 1 0  
5 0 4  
5 0 0  
FR  
FCDS  
FS  
Timing Pulse Generator LSI for CCD  
PIN CONNECTIONS  
DESCRIPTION  
The LZ93F33 is a CMOS timing generator LSI  
which provides timing pulses used to drive a  
area sensor, in combination with the SSG  
LSI (LZ93N19 or LZ93B53).  
TOP VIEW  
48-PIN QFP  
37  
24  
FEATURES  
23 MFS2  
22  
between 270000 pixels CCD and  
320000 pixels CCD  
between NTSC  
systems  
OFDX 39  
FR 40  
21 FS  
20 FCDS  
19 INSL  
18 TO  
17 SE  
16 SINV  
15 SESL  
14 SP2  
13  
41  
and PAL  
FH2 42  
GND 43  
FH  
Built-in EE (Electronic Exposure) control  
Flicker-less function  
Switchable between normal and mirror image  
Single +5 V power supply  
FHIB 45  
CKI 46  
CKO 47  
TEST 48  
0
Package : 48-pin QFP(QFP048-P-101 O)  
TSTO  
GND  
Vcc  
TEST  
TO  
GND  
GND  
VDI  
TVMD  
ACL  
VH3X  
OBCP  
SINV  
SESL  
TOSL  
DO  
CKI  
FH2  
CKO  
FR  
FS  
FCDS  
SE  
SP2  
EEST  
MFSI  
MFS2  
EEUD  
EENR  
UP/DOWN  
CONTROL  
MFR  
MFR2  
INS’  
SHUTTER  
SPEED  
CONTROL  
EEMD  
FLMD  
OFDX  
“In  
of  
by  
SHARP  
of the  
no  
any  
in  
using any of WARPs  
264  
data  
Contact SHARP  
to  
using any SHARPs device”  
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