Preliminary
SZA-5044 4.9-5.9 GHz Power Amp
Pin Out Description
Pin #
Function
Description
1,3,5,9,
N/C
Pins are not used. May be grounded, left open, or connected to adjacent pin.
11,15,17
VPC1 is the bias control pin for the stage 1 active bias circuit and can be run from 2.9V to 5V control. An exter-
nal series resistor is required for proper setting of bias levels depending on control voltage. Refer to the evalu-
ation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is
+1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10 mA.
6
7
8
VPC1
VPC2
VPC3
VPC2 is the bias control pin for the stage 2 active bias circuit and can be run from 2.9V to 5V control. An exter-
nal series resistor is required for proper setting of bias levels depending on control voltage. Refer to the evalu-
ation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is
+1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10 mA.
VPC3 is the bias control pin for the stage 3 active bias circuit and can be run from 2.9V to 5V control. An exter-
nal series resistor is required for proper setting of bias levels depending on control voltage. Refer to the evalu-
ation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is
+1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10 mA.
10
Vdet
Ouput power detector voltage. Load with 10K-100K ohms to ground for best performance.
RF input pins. This is DC grounded internal to the IC. Do not apply voltage to this pin. All three pins must be
used for proper operation.
2,4
RFIN
12,13,14 RFOUT RF output pin. This is also another connection to the 3rd stage collector
16
18
19
20
VC3
VC2
3rd stage collector bias pin. Apply 5V to this pin.
2nd stage collector bias pin. Apply 5V to this pin.
1st stage collector bias pin. Apply 5V to this pin.
Active bias network VCC. Apply 5V to this pin.
VC1
Vbias
Exposed area on the bottom side of the package needs to be soldered to the ground plane of the board for
optimum thermal and RF performance. Several vias should be located under the EPAD as shown in the rec-
ommended land pattern (page 5).
EPAD
Gnd
Simplified Device Schematic
Absolute Maximum Ratings
Parameters
Value
500
225
75
7.0
Unit
mA
mA
mA
V
VC3 Collector Bias Current (pin16)
VC2 Collector Bias Current (pin18)
VC1 Collector Bias Current (pin19)
Pin
6
Pin
20
Pin
19
Pin
7
Pin
18
Pin
8
Pin
16
Device Voltage (V )
D
Stage 1
Bias
Stage 2
Bias
Stage 3
Bias
Power Dissipation
3.4
-40 to +85
15
W
ºC
dBm
Operating Lead Temperature (T )
L
RF Input Power for 50 ohm RF out load
Pin 12,13,14
RF Input Power for 10:1 VSWR RF out
2
dBm
load
Pin 2, 4
Storage Temperature Range
-40 to +150
+150
>1000
ºC
ºC
V
Operating Junction Temperature (T )
J
EPAD
Pin
10
EPAD
EPAD
ESD Human Body Model
Operation of this device beyond any one of these limits may
cause permanent damage. For reliable continuous operation
the device voltage and current must not exceed the maximum
operating values specified in the table on page one.
Caution: ESD Sensitive
Bias conditions should also satisfy the following expression:
I V < (T - T ) / R j-l
TH’
Appropriate precaution in handling, packaging
and testing devices must be observed.
D
D
J
L
303 South Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-103585 Rev C