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CYW2325ZIT

型号：

CYW2325ZIT

品牌：

CYPRESS[ CYPRESS ]

页数：

10 页

PDF大小：

155 K

下载PDF手册
1CYW2325  
CYW2325  
Serial Input PLL with 2.5-GHz Prescaler  
Features  
Applications  
• Operating voltage 2.7V to 5.5V  
The CYW2325 is a serial-input high-performance frequency  
synthesizer which includes a dual modulus prescaler for RF  
applications up to 2.5 GHz. The synthesizer is designed for  
cellular telephone systems, portable wireless communica-  
tions, CATV and other wireless communication systems. The  
device operates from 2.7V and dissipates only 21 mW.  
• Operating frequency: up to 2.5 GHz with prescaler ra-  
tios of 32/33 and 64/65  
• Lock detect feature  
• Power-down mode  
• 20-pin TSSOP (Thin Shrink Small Outline Package)  
• 20-pin MLF (Micro Lead Frame)  
CYW2325 PLL Block Diagram  
V
(5)  
V (4)  
P
GND (7)  
CC  
(6)  
DO  
fp  
Prescaler  
32/33 or  
64/65  
(10)  
Phase  
Detector  
Charge  
Pump  
Binary 6-Bit  
Swallow Counter  
Binary 11-Bit  
Programmable Counter  
F
(16)  
IN  
BISW  
(15)  
FC  
(20)  
r
(18)  
18-Bit  
Latch  
p
fr  
(8)  
(1)  
(3)  
OSC_IN  
LD  
14-Bit  
Reference Counter  
OSC_OUT  
Latch  
Selector  
15-Bit  
Latch  
(14)  
(13)  
LE  
Divider  
(17)  
Output  
(fr/fp)  
MUX  
F
OUT  
DATA  
Cntrl 19-Bit  
Shift  
Reg  
(11)  
(19)  
CLOCK  
PWDN  
Pin Configuration  
OSC_IN  
NC  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
r
PWDN  
OSC_OUT  
3
p
1
2
3
4
5
15  
14  
13  
12  
11  
Vp  
φp  
V
4
F
out  
P
Vcc  
Do  
Fout  
BISW  
FC  
V
5
BISW  
FC  
CC  
(Top View)  
D
6
GND  
LD  
O
LE  
GND  
7
LE  
LD  
8
DATA  
NC  
NC  
9
F
10  
CLOCK  
IN  
MLF  
TSSOP  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
February 12, 2001. Rev. *A  
CYW2325  
Pin Definitions  
Pin  
No.  
(TSSOP)  
Pin  
No.  
(MLF)  
Pin  
Type  
Pin Name  
Pin Description  
OSC_IN  
1
18  
I
Oscillator Input: This input has a VCC/2 threshold and CMOS logic level  
sensitivity.  
OSC_OUT  
VP  
3
4
5
20  
1
O
P
P
Oscillator Output  
Charge Pump Rail Voltage: This supply for charge pump. Must be > VCC  
.
VCC  
2
Power Supply Connection for PLL: When power is removed from VCC  
all latched data is lost.  
DO  
6
3
O
Charge Pump Output: The phase detector gain is IP/2π. Sense polarity  
can be reversed by setting FC LOW (pin 15).  
GND  
LD  
7
8
4
5
G
O
Analog and Digital Ground Connection: This pin must be grounded.  
Lock Detect Pin: This output is HIGH with narrow LOW pulses when the  
loop is locked.  
FIN  
10  
11  
7
8
I
I
Input to Prescaler: Maximum frequency 2.5 GHz.  
CLOCK  
Data Clock Input: One bit of data is loaded into the Shift Register on the  
rising edge of this signal.  
DATA  
LE  
13  
14  
10  
11  
I
I
Serial Data Input  
Load Enable: On the rising edge of this signal, the data stored in the Shift  
Register is latched into the counters and configuration controls.  
FC  
15  
16  
12  
13  
I
Phase Sense Control for Phase Detector with Internal Pull-up: When  
pulled LOW, the polarity of the Phase Detector is reversed.  
BISW  
O
Analog Switch Output: Connects to output of charge pump when LE is  
HIGH.  
FOUT  
17  
18  
14  
15  
O
O
Monitor Point for Phase Detector Input  
External Charge Pump Output: Open drain N-Channel FET, pull-up re-  
P
sistor required.  
PWDN  
19  
16  
I
Power-Down Pin with Internal Pull-up: When pin is HIGH, device is in  
normal state. When pin is LOW, device is in power-down mode. When  
device enters power-down mode the charge pump is in the High-Imped-  
ance condition.  
20  
17  
O
External Change Pump: (CMOS logic output).  
R
NC  
2, 9, 12  
6, 9, 19  
No Connect  
2
CYW2325  
only. Operation of the device at these or any other conditions  
above those specified in the operating sections of this specifi-  
cation is not implied. Maximum conditions for extended peri-  
ods may affect reliability.  
Absolute Maximum Ratings  
Stresses greater than those listed in this table may cause per-  
manent damage to the device. These represent a stress rating  
Parameter  
VCC or VP  
VOUT  
Description  
Power Supply Voltage  
Rating  
–0.5 to +6.5  
–0.5 to VCC+0.5  
±15  
Unit  
V
Output Voltage  
V
IOUT  
Output Current  
mA  
°C  
°C  
TL  
Lead Temperature  
Storage Temperature  
+260  
TSTG  
–55 to +150  
Always turn off power before adding or removing devices from  
system.  
Handling Precautions  
Devices should be transported and stored in antistatic con-  
tainers.  
Protect leads with a conductive sheet when handling or trans-  
porting PC boards with devices.  
These devices are static sensitive. Ensure that equipment and  
personnel contacting the devices are properly grounded.  
If devices are removed from the moisture protective bags for  
more than 36 hours, they should be baked at 85°C in a mois-  
ture free environment for 24 hours prior to assembly in less  
than 24 hours.  
Cover workbenches with grounded conductive mats.  
Recommended Operating Conditions  
Parameter  
Description  
Power Supply Voltage  
Test Condition  
Rating  
2.7 to 5.5  
VCC to +5.5  
–40 to +85  
Unit  
V
VCC  
VP  
Charge Pump Voltage  
Operating Temperature  
V
TA  
Ambient air at 0 CFM flow  
°C  
3
CYW2325  
Electrical Characteristics: VCC = 3.0V, VP = 3.0V, TA = –40°C to +85°C, Unless otherwise specified  
Parameter  
Description  
Power Supply Current  
Power-down Current  
Test Condition  
Pin  
Min.  
Typ.  
Max.  
Unit  
mA  
ICC  
IPD  
FIN  
VCC  
VCC  
FIN  
8
6
µA  
Power-down, VCC = 3.0V  
100  
Maximum Operating  
Frequency  
100  
2500  
GHz  
FOSC  
Oscillator Input Frequency No load on OSC_OUT  
With OSC_OUT loaded  
OSC_IN  
5
5
45  
25  
10  
MHz  
MHz  
MHz  
Fφ  
Phase Detector  
Frequency  
PFIN  
Input Sensitivity  
VCC = 2.7V  
VCC = 5.5V  
FIN  
–15  
–10  
4
4
dBm  
dBm  
VP–P  
µA  
V
VOSC  
IIH, IIL  
VIH  
Oscillator Input Sensitivity  
Oscillator Input Current  
High Level Input Voltage  
Low Level Input Voltage  
High Level Input Current  
Low Level Input Current  
High Level Output Voltage  
Low Level Output Voltage  
IDO, Source Current  
OSC_IN  
0.5  
–100  
100  
VCC = 5.0V  
DATA,  
CLOCK,  
LE  
VCC * 0.8  
VIL  
VCC * 0.2  
V
µA  
µA  
V
IIH  
–10  
–10  
2.2  
1
1
10  
10  
IIL  
VCC = 3.0V, IOH = –1mA  
VOH  
VOL  
IDO(SO)  
FO  
DO  
VCC = 3.0V, IOL = 1mA  
0.4  
V
VP = 3.0V, VDO = VP/2  
VP = 5.0V, VDO = VP/2  
–3.7  
–4.1  
mA  
mA  
IDOH(SI)  
IDO, Sink Current  
VP = 3.0V, VDO = VP/2  
VP = 5.0V, VDO = VP/2  
DO  
3.7  
4.1  
mA  
mA  
∆IDO  
IDO Charge Pump Sink  
and Source Mismatch  
VDO = VP/2  
[IIDO(SI)I – IIDO(SO)I]/  
[1/2*{IIDO(SI)]I+IIDO(SO)I}]*100%  
5
%
–40°C<T<85°C, VDO = VP/2[1]  
5
%
IDO vs T  
IDO-tri  
Charge Pump Current  
Variation vs. Temperature  
nA  
Charge Pump High-  
Impedance Leakage  
Current  
±2  
Note:  
1. IDOVS T; Charge pump current variation vs. temperature.  
[IIDO(SI)@TI – IIDO(SI)@25° CI]/IIDO(SI)@25°CI * 100% and  
[IIDO(SO)@TI – IIDO(SO)@25°CI]/IIDO(SO)@25°CI *100%.  
4
 
CYW2325  
Timing Waveforms  
Phase Characteristics  
For normal operation, the FC pin is used to select the output polarity of the  
phase detector. Both the internal and any external charge pump are affected.  
(1)  
Depending upon VCO characteristics, FC pin should be set accordingly:  
When VCO characteristics are like (1), FC should be set HIGH or OPEN  
CIRCUIT:  
VCO  
Output  
Frequency  
When VCO characteristics are like (2), FC should be set LOW.  
When FC is set HIGH or OPEN CIRCUIT, Fout pin is set to the reference  
divider output, Fr. When FC is set LOW, Fout pin is set to the programmable  
divider output Fp.  
(2)  
VCO Input Voltage  
Phase Comparator Sense  
Phase Detector Output Waveform  
F
F
R
P
tw  
tw  
LD  
DO Charge Pump Output Current Waveform  
F
F
R
P
tw  
tw  
D
o
ID  
O
High-Impedance State  
5
CYW2325  
Timing Waveforms (continued)  
Serial Data Input Timing Waveform[2, 3, 4, 5]  
//  
//  
//  
//  
PD = MSB  
PRE  
B1  
A7  
CNT2  
CNT1 = LSB  
DATA  
//  
//  
CLOCK  
t5  
t4  
t3  
t2  
t1  
//  
//  
//  
//  
LE  
t6  
Serial Data Input  
Data is input serially using the DATA, CLOCK, and LE pins.  
Two control bits direct data into the locations given in Table 1.  
Table 1. Control Configuration  
CNT  
Function  
1
0
Reference Counter: R = 3 to 16383, set prescaler ratio PRE =0:64/65, PRE=1:32/33  
Program Counter: A = 0 to 63, B = 3 to 2047  
Table 2. Shift Register Configuration[6]  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Reference Counter and Configuration Bits  
CNT R1  
R2  
R3  
R4  
R5  
R6  
R7  
R8  
R9 R10 R11 R12 R13 R14 PRE  
Programmable Counter Bits  
CNT A1  
A2  
A3  
A4  
A5  
A6  
A7  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9 B10 B11  
Bit(s) Name  
CNT  
Function  
Control Bit: Directs programming data to reference or programmable counters.  
Reference Counter Setting Bits: 14 bits, R = 3 to 16383.[7]  
Prescaler Divide Bit: LOW = 64/65 and HIGH = 32/33.  
Swallow Counter Divide Ratio: A = 0 to 63.  
R1–R14  
PRE  
A1–A7  
B1–B11  
Notes:  
Programmable Counter Divide Ratio: B = 3 to 2047.[7]  
2. t1–t6 = t > 50 ns.  
3. CLOCK may remain HIGH after latching in data.  
4. DATA is shifted in with the MSB first.  
5. For DATA definitions, refer to Table 2.  
6. The MSB is loaded in first.  
7. Low count ratios may violate frequency limits of the phase detector.  
6
 
 
 
 
 
 
 
 
CYW2325  
Table 3. 6-Bit Swallow Counter (A) Truth Table[8]  
Divide Ratio A  
A7  
X
A6  
0
A5  
0
A4  
0
A3  
0
A2  
0
A1  
0
0
1
X
0
0
0
0
0
1
:::  
:::  
X
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
62  
63  
X
1
1
1
1
1
1
Table 4. 11-Bit Programmable Counter (B) Truth Table[9]  
Divide Ratio B  
B11  
0
B10  
0
B9  
0
B8  
0
B7  
0
B6  
0
B5  
0
B4  
0
B3  
B2  
1
B1  
1
3
4
0
1
0
0
0
0
0
0
0
0
0
0
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
2046  
2047  
1
1
1
1
1
1
1
1
1
1
1
Table 5. 14-Bit Programmable Reference Counter Truth Table[9]  
Divide Ratio R  
R14  
0
R13  
0
R12  
0
R11  
0
R10  
0
R9  
0
R8  
0
R7  
0
R6  
R5  
0
R4  
0
R3  
0
R2  
1
R1  
3
4
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
16382  
16383  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Ordering Information[10]  
Package  
Name  
Ordering Code  
Package Type  
Tape and Reel Option  
ZI  
LFI  
20-pin TSSOP (0.173” wide)  
20-pin MLF (4 mm x 4 mm)  
CYW2325  
TR  
Notes:  
8. B is greater than or equal to A.  
9. Divide ratio less than 3 is prohibited. The divide ratio can be calculated using the following equation:  
fvco = {(P * B) + A} * fosc / R where (A < B)  
fvco: Output frequency of the external VCO.  
fosc: The crystal reference oscillator frequency.  
A: Preset divide ratio of the 6-bit swallow counter.  
B: Preset ratio of the 11-bit programmable counter (3 to 2047).  
P: Preset divide ratio of the dual modulus prescaler.  
R: Preset ratio of the 15-bit programmable reference counter (3 to 16383).  
The divide ratio N = (P * B) + A.  
10. Operating temperature range: –40°C to +85°C.  
Document #: 38-00920-*A  
7
 
 
 
CYW2325  
Examples  
Charge Pump Current vs Do Voltage  
5.0  
4.0  
Vp = 3V  
Vp = 5V  
3.0  
2.0  
1.0  
1
0.0  
-1.0  
-2.0  
-3.0  
-4.0  
Vp = 3V  
Vp = 5V  
2
3
4
-5.0  
0.0  
1.0  
2.0  
3.0  
4.0  
5.0  
Do Voltage (V)  
Vp  
(V)  
3V  
3V  
5V  
5V  
Icp  
Marker  
Number  
Marker 1  
Marker 2  
Marker 3  
Marker 4  
Input  
Frequency  
100 MHz  
1000 MHz  
1800 MHz  
2500 MHz  
(mA)  
3.60  
-3.65  
4.15  
-4.10  
S11 (  
)
Ω
Source  
Sink  
Source  
Sink  
501 - j688  
36 - j158  
30 - j98  
20 - j38  
Figure 2. Input Impedance  
VCC=2.7V to 5.5V  
Figure 1. Charge Pump Current  
FIN=100 MHz to 2700 MHz  
-85 dBc  
Offset  
Frequency  
1 KHz  
Phase noise  
(dBc/Hz)  
-80  
Re fe re nce  
S pur  
250 K Hz  
Le ve l  
(dBc/Hz )  
-85  
10 KHz  
-86  
100 KHz  
-115  
Figure 4. Re fe re nce S pur  
Figure 3. Phase Noise  
vs Offset Frequency  
8
CYW2325  
Package Diagram  
20-Pin Thin Shrink Small Outline Package (TSSOP, 0.173” wide)  
9
CYW2325  
Package Diagram  
20-Pin Micro Lead Frame Package (MLF 4 mm X 4 mm)  
2X  
0.25  
C A  
A
D
10  
D/2  
4
0.05  
C
4X P  
M
D1  
b
0.10  
D2/2  
C A  
B
A
R
A1  
A3  
D2  
D1/2  
A2  
2X  
8.  
N
N
0.25  
C B  
4X P  
5
6
E1/2  
E/2  
1
2
3
1
2
3
0.50 DIA.  
(Ne-1)Xe  
REF.  
4X Q  
E1  
E
B
E2  
E2/2  
L
0.20  
C B  
0
2X  
e
C
0.20  
C A  
SEATING  
PLANE  
(Nd-1)Xe  
REF.  
2X  
TOP VIEW  
C
C
BOTTOM VIEW  
11  
C
C
A1  
L
L
b
4
SECTION "C-C"  
SCALE: NONE  
e
e
TERMINAL TIP  
FOR ODD TERMINAL/SIDE  
FOR EVEN TERMINAL/SIDE  
S
Y
1. DIE THICKNESS ALLOWABLE IS 0.305mm MAXIMUM(.012 INCHES MAXIMUM)  
2. DIMENSIONING & TOLERANCES CONFORM TO ASME Y14.5M. - 1994.  
COMMON  
NOTES:  
M
B
O
N
DIMENSIONS  
O
T
E
L
MIN.  
NOM.  
MAX.  
1.00  
0.05  
3. N IS THE NUMBER OF TERMINALS.  
Nd IS THE NUMBER OF TERMINALS IN X-DIRECTION &  
-
0.00  
-
0.85  
A
A1  
A2  
A3  
0.01  
0.65  
0.20 REF.  
11  
0.80  
Ne IS THE NUMBER OF TERMINALS IN Y-DIRECTION.  
4. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED  
BETWEEN 0.20 AND 0.25mm FROM TERMINAL TIP.  
D
D1  
E
E1  
4.00 BSC  
3.75 BSC  
4.00 BSC  
3.75 BSC  
5. THE PIN #1 IDENTIFIER MUST BE EXISTED ON THE TOP SURFACE OF THE  
PACKAGE BY USING INDENTATION MARK OR OTHER FEATURE OF PACKAGE BODY.  
6. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.  
7. ALL DIMENSIONS ARE IN MILLIMETERS.  
12  
0.60  
0
P
0.24  
0.13  
0.42  
0.17  
0.50 BSC  
20  
0.23  
R
e
N
Nd  
Ne  
L
8. THE SHAPE SHOWN ON FOUR CORNERS ARE NOT ACTUAL I/O.  
9. PACKAGE WARPAGE MAX 0.05mm.  
3
3
3
5
5
10. APPLIED FOR EXPOSED PAD AND TERMINALS.  
EXCLUDE EMBEDDING PART OF EXPOSED  
PAD FROM MEASURING.  
0.50  
0.18  
0.30  
1.55  
1.55  
0.60  
0.23  
0.40  
1.70  
1.70  
0.75  
0.30  
0.65  
1.85  
1.85  
b
Q
4
D2  
E2  
11. APPLIED ONLY FOR TERMINALS.  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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