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TXN174310850F36

型号：

TXN174310850F36

品牌：

EMCORE[ EMCORE CORPORATION ]

页数：

44 页

PDF大小：

1183 K

下载PDF手册
Intel® TXN17431 (0850) 10.3 Gbps 850 nm  
Optical Transceiver Compliant with XENPAK  
MSA  
Datasheet  
Product Features  
„ 10BASE-SR 10.3 Gbps Optical  
„ Faceplate, Z-Axis Hot-Plug Capability  
Transceiver, IEEE 802.3ae Compliant  
„ Digital Management Interface (MDIO)  
Compatible with the IEEE Standard  
and XENPAK MSA  
„ Available for 10.3 Gpbs Ethernet Bit  
Rate (up to 300 m multi-mode fiber)  
Applications  
„ Class 1 Laser Safety Product  
„ XENPAK Multisource Agreement (MSA)  
Compliant Form Factor and Pin  
Configuration  
„ IEC/UL 60950-1 Safety Certified  
„ Designed and verified as RoHS  
compliant  
„ XAUI Data Interface via standard 70-  
„ China RoHS compliant with 30-year  
Pin Connector  
EFUP  
Applications  
„ 10 Gigabit Ethernet equipment, high density data-center applications, including:  
— Enterprises Switches  
— Optical Router  
— Enterprise Stackable Switches  
— Optical Test Equipment  
Document Number: 306424-005  
2-Nov-2007  
Legal Lines and Disclaimers  
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR  
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS  
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING  
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,  
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.  
UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE  
FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.  
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics  
of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for  
conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with  
this information.  
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published  
specifications. Current characterized errata are available on request.  
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.  
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-  
4725, or by visiting Intel’s Web Site.  
BunnyPeople, Celeron, Celeron Inside, Centrino, Centrino logo, Core Inside, FlashFile, i960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740,  
IntelDX2, IntelDX4, IntelSX2, Intel Core, Intel Inside, Intel Inside logo, Intel. Leap ahead., Intel. Leap ahead. logo, Intel NetBurst, Intel NetMerge, Intel  
NetStructure, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel Viiv, Intel vPro, Intel XScale, Itanium, Itanium Inside, MCS, MMX, Oplus,  
OverDrive, PDCharm, Pentium, Pentium Inside, skoool, Sound Mark, The Journey Inside, VTune, Xeon, and Xeon Inside are trademarks of Intel  
Corporation in the U.S. and other countries.  
*Other names and brands may be claimed as the property of others.  
Copyright © 2007, Intel Corporation. All rights reserved.  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
2
2-Nov-2007  
Document Number: 306424-005  
Intel® TXN17431 (0850) Optical Transceiver  
Contents  
1.0 Introduction..............................................................................................................7  
2.0 Ratings......................................................................................................................8  
3.0 Optical Specifications ................................................................................................9  
4.0 Control and Monitoring Functions............................................................................ 10  
5.0 Data Output/Input Configuration ............................................................................ 11  
6.0 MDIO Interface ....................................................................................................... 14  
6.1  
6.2  
6.3  
MDIO Physical Interface ..................................................................................... 14  
MDIO Access Frame Format................................................................................ 14  
MDIO Register Set............................................................................................. 15  
6.3.1 Register Set .......................................................................................... 16  
6.3.2 PMA/PMD Control Registers (Device ID = 1h)............................................. 17  
6.3.3 PCS Control Registers (Device ID = 3h)..................................................... 22  
6.3.4 PHY_XS Control Registers (Device ID = 4h) ............................................... 26  
6.3.5 XENPAK NVR Registers and NVR EEPROM Description.................................. 30  
6.3.6 XENPAK DOM/LASI Control and Status Registers ........................................ 31  
7.0 Digital Optical Monitoring........................................................................................ 35  
8.0 Loopback Capability................................................................................................. 37  
9.0 Mechanical Layout and Configuration ...................................................................... 38  
10.0 Regulatory Compliance............................................................................................ 40  
10.1 Electromagnetic Compatibility Compliance ............................................................ 40  
10.2 Safety Compliance............................................................................................. 40  
10.3 Compliance with Restriction of Hazardous Substances ............................................ 41  
10.4 Product Certification Markings and Compliance Statements ..................................... 41  
10.5 Management Methods on Control of Pollution from Electronic Information Products (a.k.a.  
China RoHS)..................................................................................................... 43  
11.0 Ordering Information .............................................................................................. 43  
12.0 Acronyms ................................................................................................................ 44  
Figures  
1
2
3
Block Diagram...........................................................................................................8  
DOM Access State Diagram ....................................................................................... 37  
Mechanical Outline for a Heat Sink ............................................................................. 39  
Tables  
1
2
3
5
6
4
7
8
9
Absolute Maximum Ratings .........................................................................................8  
Power Supply Characteristics (10GBASE-SR) .................................................................9  
Optical Specifications — Transmitter.............................................................................9  
Optical Specifications — Link ..................................................................................... 10  
Optical Specifications — Receiver ............................................................................... 10  
Minimum OMA (dBm) as a Function of Center Wavelength and Spectral Width.................. 10  
Digital Control and Monitoring Signals ........................................................................ 11  
Data Input/Output Configuration ............................................................................... 11  
Pin Configuration ..................................................................................................... 12  
10 MDIO Frame Format................................................................................................. 15  
11 PMA/PMD Control Register Set: Device ID = 1h............................................................ 16  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
Document Number: 306424-005  
Datasheet  
3
Intel® TXN17431 (0850) Optical Transceiver  
12 PCS Control Register Set: Device ID = 3h....................................................................16  
13 PHY_XS Control Register Set: Device ID = 4h ..............................................................16  
14 XENPAK NVR Register Set and NVR EEPROM Description................................................17  
15 XENPAK DOM/LASI Control and Status Register Set ......................................................17  
16 PMA/PMD Control 1 Register (DID = 1h, Address = 0h) .................................................17  
17 PMA/PMD Status 1 Register (DID = 1h, Address = 1h) ..................................................18  
18 PMA/PMD Speed Ability Register (DID = 1h, Address = 4h)............................................18  
19 PMA/PMD Devices in Package Register (DID = 1h, Address = 5h) ...................................18  
20 PMA/PMD Control 2 Register (DID = 1h, Address = 7h) .................................................19  
21 PMA/PMD Status 2 Register (DID = 1h, Address = 8h) ..................................................19  
22 PMD Transmit Disable Register (DID = 1h, Address = 9h)..............................................20  
23 PMD Receive Signal OK Register (DID = 1h, Address = ah)............................................20  
24 Package Identifier OUI Register (DID = 1h, Address = eh).............................................20  
25 Package Identifier OUI Register (DID = 1h, Address = fh)..............................................20  
26 PMA Network Loopback Register (DID = 1h, Address = c001h).......................................21  
27 EEPROM Control Register (DID = 1h, Address = c003h).................................................21  
28 EEPROM Checksum Register (DID = 1h, Address = c004h) ............................................22  
29 PCS Control 1 Register (DID = 3h, Address = 0h).........................................................22  
30 PCS Status 1 Register (DID = 3h, Address = 1h)..........................................................22  
31 PCS Speed Ability Register (DID = 3h, Address = 4h)....................................................23  
32 PCS Devices in Package Register (DID = 3h, Address = 5h) ...........................................23  
33 PCS Control 2 Register (DID = 3h, Address = 7h).........................................................23  
34 10 G PCS Status 2 Register (DID = 3h, Address = 8h) ..................................................23  
35 10GBASE-R PCS Status 1 Register (DID = 3h, Address = 20h) .......................................24  
36 10GBASE-R PCS Status Register 2 (DID = 3h, Address = 21h) .......................................24  
37 10GBASE-R PCS Jitter Test Pattern Seed A Registers (DID = 3h, Address = 22h to 25h)....24  
38 10GBASE-R PCS Jitter Test Pattern Seed B Registers (DID = 3h, Address = 26h to 29h)....25  
39 10GBASE-R PCS Test Control Register (DID = 3h, Address = 2ah)..................................25  
40 10GBASE-R PCS Jitter Test Counter Register (DID = 3h, Address = 2bh) .........................25  
41 10GBASE-R PCS Test Register (DID = 3h, Address = c000h)..........................................26  
42 Fiber PRBS Mode Register (DID = 3h, Address = c006h) ...............................................26  
43 PHY_XS Control 1 Register (DID = 4h, Address = 0h) ...................................................26  
44 PHY_XS Status 1 Register (DID = 4h, Address = 1h).....................................................27  
45 PHY_XS Speed Ability Register (DID = 4h, Address = 4h)..............................................27  
46 PHY_XS Devices in Package Register (DID = 4h, Address = 5h)......................................27  
47 PHY_XS Status 2 Register (DID = 4h, Address = 8h).....................................................27  
48 PHY_XS Lane Status Register (DID = 4h, Address = 18h)..............................................28  
49 PHY_XS Test Control Register (DID = 4h, Address = 19h)..............................................28  
50 PHY_XS Control 2 Register (DID = 4h, Address = c000h)...............................................28  
51 PHY_XS XAUI PRBS Status Register (DID = 4h, Address = c001h) ..................................29  
52 PHY_XS Rate Adjust Register (DID = 4h, Address = c002h) ...........................................29  
53 PHY_XS Receive Code Violation Counter Register (DID = 4h, Address = c008h)................30  
54 PMA/PMD EEPROM Control Register (DID = 1h, Address = 8000h) ..................................30  
55 EEPROM Registers (DID = 1h, from Address = 8007h to Address = 8106h)......................30  
56 EEPROM Register Mapping Information (DID = 1h) .......................................................31  
57 RX_ALARM Enable Register (DID = 1h, Address = 9000h)..............................................31  
58 TXALARM Enable Register (DID = 1h, Address = 9001h)................................................32  
59 LASI Control Register (DID = 1h, Address = 9002h) .....................................................32  
60 RXALARM Status Register (DID = 1h, Address = 9003h)................................................32  
61 TXALARM Status Register (DID = 1h, Address = 9004h)................................................33  
62 LASI Status Register (DID = 1h, Address = 9005h).......................................................33  
63 DOM Tx_flag Control Register (DID = 1h, Address = 9006h) ..........................................34  
64 DOM Rx_flag Control Register (DID = 1, Address = 9007h)............................................34  
65 DOM Registers (DID = 1, Address = A000h to A069h, A072h to A0FFh)...........................34  
66 DOM – Tx_flag Status Register (DID = 1, Address = A070h) ..........................................34  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
4
2-Nov-2007  
Document Number: 306424-005  
Intel® TXN17431 (0850) Optical Transceiver  
67 DOM – Rx_flag Status Register (DID = 1, Address = A071h) ......................................... 35  
68 DOM Command and Status Register (DID = 1, Address = A100h) .................................. 35  
69 DOM Update Rates (DID = 1, Address = A100h) .......................................................... 36  
70 Loopback Capability ................................................................................................. 37  
71 Electromagnetic Compatibility Compliance................................................................... 40  
72 Safety Compliance ................................................................................................... 40  
73 Product Certification Markings and Compliance Statements............................................ 42  
74 Hazardous Substances Table ..................................................................................... 43  
75 Ordering Information ............................................................................................... 44  
76 Acronyms ............................................................................................................... 44  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
Document Number: 306424-005  
Datasheet  
5
Intel® TXN17431 (0850) Optical Transceiver  
Revision History  
Date  
Revision  
Description  
Updated Section 10.0, “Regulatory Compliance” on page 40 and Section 11.0, “Ordering  
Information” on page 43. Change bars indicate areas of change.  
2-Nov-2007  
005  
004  
27-Sep-2007  
Updated “Regulatory Compliance”.  
Modified “Optical Specifications — Transmitter”; changed Transmitter and Dispersion Penalty to  
Transmiter Dispersion Penalty and removed TDP; added table note.  
12-Jul-2005  
003  
Modified “Optical Specifications — Receiver”: Removed “Receiver Sensitivity.”  
Updated Part Number and MM Number in “Ordering Information” and “Addendum for Cisco  
Systems Only”.  
26-May-2005  
29-Apr-2005  
002  
001  
Initial release.  
Related Hardware and Documents  
Part Number  
Description  
XENPAK Evaluation board: Provides access to all XAUI interfaces, control, and monitor signals.  
TXNEB17431  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
6
2-Nov-2007  
Document Number: 306424-005  
Intel® TXN17431 (0850) Optical Transceiver  
1.0  
Introduction  
The Intel® TXN17431 (0850) Optical Transceiver is a 10.3 Gbps 850 nm Optical  
Transceiver compliant with the XENPAK Multisource Agreement (MSA). The TXN17431  
Optical Transceiver provides an IEEE 802.3ae 2002-compliant 10GBASE-SR interface  
between the photonic physical layer and the electrical section layer.  
The TXN17431 Optical Transceiver is comprised of an optical transmitter and receiver  
pair integrated with XAUI-to-serial conversion. PCS, PMA, and PMD functions are  
included.  
Note:  
Unless otherwise noted, the Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical  
Transceiver Compliant with XENPAK MSA will be called the TXN17431 Optical  
Transceiver throughout the remainder of this document.  
The TXN17431 Optical Transceiver transmitter section decodes four 8B/10B-encoded  
channels running at 3.125 Gbps for Ethernet from a XAUI parallel data bus, performs a  
64B/66B scrambling and multiplexes the results into a 10.3125 Gbps optical signal  
launched into a multi-mode optical fibre using an 850 nm Vertical Cavity Surface  
Emitting Laser (VCSEL).  
The TXN17431 Optical Transceiver receiver section de-multiplexes a single 10.3 Gbps  
(Ethernet) optical signal and converts it back to four channels of 3.125 Mbps (Ethernet)  
XAUI. The receiver includes a photodiode, transimpedance amplifier, clock recovery,  
decision circuit, and de-multiplexer. The receiver operates over an 850 nm band for  
10GBASE-SR.  
Figure 1 illustrates the TXN17431 Optical Transceiver block diagram.  
The TXN17431 Optical Transceiver is assembled in a XENPAK MSA-compatible 4.8 in. L  
× 1.4 in. W × 0.7 in. H package. The heat sink is designed for a 50 °C ambient  
temperature with 200 linear feet-per-minute airflow. A XENPAK MSA-compliant, 70-pin,  
board edge connector provides/supplies the electrical interface. Optical connections are  
made with standard SC-UPC optical connectors.  
The TXN17431 Optical Transceiver is designed for link spans up to 300 m and uses an  
850 nm Transistor Outline (TO)-can laser source.  
An IEEE 802.3ae version 5 and XENPAK MSA-compliant Management Data Interface  
(MDIO) with Digital Optical Monitoring (DOM) support is included.  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
2-Nov-2007  
Document Number: 306424-005  
7
Intel® TXN17431 (0850) Optical Transceiver  
Figure 1.  
Block Diagram  
DOM  
EEPROM  
LASI  
PRTAD<04: >  
MDC/MDIO  
Management  
Laser  
Diode  
Control  
MDC  
MDIO  
XAUI  
Receive /  
Demux /  
Deskew  
8B/10B  
Decoder  
64/66  
Encoder /  
Scrambler  
Transmit  
Laser Diode  
Driver  
XAIP(N),  
XBIP(N),  
XCIP(N),  
XDIP(N)  
Laser  
Mux  
Data  
Output  
REFCLK  
Mux /  
XAUI  
Transmit  
8B/10B  
Encoder  
Descrambler /  
66/64  
Decoder  
XAOP(N),  
XBOP(N),  
XCOP(N),  
XDOP(N)  
Demux  
Receive PIN  
Diode / TIA  
CDR  
2.0  
Ratings  
Table 1 lists the absolute maximum ratings for the TXN17431 Optical Transceiver. Table  
2 lists the required power supplies. Minimum and maximum values listed in Table 3  
through Table 6 apply over the recommended operating conditions specified in Table 2.  
Table 1.  
Absolute Maximum Ratings  
Parameter  
Symbol  
Min.  
Max.  
Unit  
Case operating temperature range  
Case storage temperature range  
Positive supply voltage (+3.3 V)  
Positive supply voltage (+1.8 V APS)  
Positive supply voltage (+5 V)  
Relative humidity (non-condensing)  
Receiver input power  
T
T
0
40  
0
+70  
+85  
+3.6  
+2.0  
5.5  
°C  
°C  
V
C
S
V
V
+
+
3.3  
1.8  
0
V
V +  
5
0
V
RH  
–
–
85  
%
dBm  
–
-1  
Caution:  
Exceeding these values may cause permanent damage. Functional  
operation under these conditions is not implied. Exposure to maximum  
rating conditions for extended periods may affect device reliability.  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
8
2-Nov-2007  
Document Number: 306425-005  
Intel® TXN17431 (0850) Optical Transceiver  
Table 2.  
Power Supply Characteristics (10GBASE-SR)  
Parameter  
Symbol  
V +  
Min.  
Nom.  
Max.  
Unit  
Positive supply voltage (+5.0 V)  
4.75  
–
5.0  
5.25  
0.22  
V
A
V
A
V
A
5
Positive supply current drain (+5.0 V)  
Positive supply voltage (+3.3 V)  
I +  
5
V
+
+3.135  
+3.3  
+3.465  
0.6  
3.3  
Positive supply current drain (+3.3 V)  
Positive supply voltage (+1.8 V) APS  
Positive supply current drain (+1.8 V) APS  
I
+
3.3  
V
+
+1.728  
–
+1.8  
–
+1.872  
0.50  
1.8  
I
+
1.8  
Negative Voltage due to transient current  
for all supplies  
V
–
–
–
–
-0.3  
6
V
tran  
Total Power Dissipation  
Pdiss  
W
NOTE: Case operating temperature = 0 °C to 70 °C.  
3.0  
Optical Specifications  
The TXN17431 Optical Transceiver is designed for applications consistent with  
IEEE 802.3ae version 5.0 recommendations for 10GBASE-SR. Table 3 through Table 6  
list the transmitter, link, and receiver specifications.  
Table 3.  
Optical Specifications — Transmitter  
Parameter  
Symbol  
Min.  
Typ.  
Max.  
Unit  
Operating Wavelength  
λ
840  
–
–
860  
–
nm  
Signaling Speed (nominal)  
–
10.3125  
GBd  
Signaling Speed Variation from  
nominal  
–
–
-100  
-7.3  
–
–
100  
-1  
ppm  
Average Launch Power  
(Meets Class 1 safety limits)  
dBm  
dBm  
Average Launch Power of Off Tx  
Minimum OMA1  
–
–
–
–
–
–
3
–
–
–
–
-30  
–
see Table 4  
Transmitter Dispersion Penalty3  
Extinction Ratio  
–
–
–
–
–
3.9  
–
dBm  
dB  
r
e
RIN12OMA (maximum)  
RMS Spectral Width  
RIN  
–
-128  
0.45  
12  
dB/Hz  
nm  
Optical Return Loss  
ORLT  
dB  
Eye Mask of Optical Output  
Encircled Flux  
Compliant with IEEE 802.3ae 2002 specifications  
See Note 2  
1.  
2.  
Per triple trade-off curves for 10G BASE-SR.  
The encircled flux at 19 μm shall be greater than or equal to 86% and the encircled flux at 4.5 μm  
shall be less than or equal to 30% when measured into type A1a (50/125 μm multi-mode) fiber per  
TIA-455-203.  
3.  
Transmitter Dispersion Penalty was tested using the two worst-case links from Table 52-6 in  
IEEE 802.3ae.  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
2-Nov-2007  
Document Number: 306424-005  
9
Intel® TXN17431 (0850) Optical Transceiver  
Table 4.  
Minimum OMA (dBm) as a Function of Center Wavelength and Spectral Width  
RMS Spectral Width (nm)  
Center  
Wavelength  
Up to  
0.05  
0.05to  
0.1  
0.1 to  
0.15  
0.15 to  
0.2  
0.2 to  
0.25  
0.25  
to 0.3  
0.3 to  
0.35  
0.35 to  
0.4  
0.4 to  
0.45  
(nm)  
840 to 842  
842 to 844  
844 to 846  
846 to 848  
848 to 850  
850 to 852  
852 to 854  
854 to 856  
856 to 858  
858 to 860  
-4.2  
-4.2  
-4.2  
-4.3  
-4.3  
-4.3  
-4.3  
-4.3  
-4.3  
-4.3  
-4.2  
-4.2  
-4.2  
-4.2  
-4.2  
-4.2  
-4.2  
-4.3  
-4.3  
-4.3  
-4.1  
-4.2  
-4.2  
-4.2  
-4.2  
-4.2  
-4.2  
-4.2  
-4.2  
-4.2  
-4.1  
-4.1  
-4.1  
-4.1  
-4.1  
-4.1  
-4.1  
-4.1  
-4.1  
-4.2  
-3.9  
-3.9  
-4.0  
-4.0  
-4.0  
-4.0  
-4.0  
-4.0  
-4.0  
-4.1  
-3.8  
-3.8  
-3.8  
-3.8  
-3.8  
-3.8  
-3.9  
-3.9  
-3.9  
-3.9  
-3.5  
-3.6  
-3.6  
-3.6  
-3.6  
-3.6  
-3.7  
-3.7  
-3.7  
-3.7  
-3.2  
-3.3  
-3.3  
-3.3  
-3.3  
-3.4  
-3.4  
-3.4  
-3.5  
-3.5  
-2.8  
-2.9  
-2.9  
-2.9  
-3.0  
-3.0  
-3.1  
-3.1  
-3.1  
-3.2  
Table 5.  
Optical Specifications — Link  
Parameter  
62.5 µm MMF  
50 µm MMF  
Unit  
Modal bandwidth as measured at 850 nm  
Power budget  
160  
7.3  
26  
200  
7.3  
33  
400  
500  
7.3  
82  
2000  
MHz.km  
dB  
7.3  
66  
12  
7.3  
300  
12  
Link distance  
meter  
dB  
Link overall optical return loss  
12  
12  
12  
Table 6.  
Optical Specifications — Receiver  
Parameter  
Symbol  
Min.  
Typ.  
Max.  
Unit  
Average receive power (maximum)  
Stressed receiver sensitivity (OMA)1  
Receiver reflectance  
–
–
–
–
–
-1.0  
-7.5  
-12  
dBm  
dBm  
dB  
PRS  
OMA  
–
–
–
Center wavelength  
λ
840  
850  
860  
nm  
10.3125,  
10.51875  
Signaling Speed Nominal  
–
–
–
–
–
–
–
GBd  
ppm  
GHz  
Signaling Speed Variation from nominal  
–
–
100  
12.3  
Receive Electrical 3 dB upper cutoff  
frequency  
1. Measured with 3.5 dB vertical eye closure penalty and 0.3UI pk-pk stressed eye jitter.  
4.0  
Control and Monitoring Functions  
The TXN17431 Optical Transceiver provides digital control and monitoring functions as  
listed in Table 7.  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
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2-Nov-2007  
Document Number: 306425-005  
Intel® TXN17431 (0850) Optical Transceiver  
Table 7.  
Digital Control and Monitoring Signals  
Function  
Pin Name  
Pin #  
Description  
Interface  
Digital interface provides  
access to management data  
as specified in IEEE 802.3ae 1.2 V CMOS compatible  
XAUI interface specifications  
Management  
data interface  
MDIO  
17  
and XENPAK MSA  
Management  
data clock  
Clock for management data  
1.2 V CMOS compatible  
interface  
MDC  
18  
Input pins for  
setting module  
port address  
Allows the MDIO address to  
1.2 V CMOS compatible  
be set  
PRTAD  
19–23  
Logic low indicates status  
Open drain compatible  
interrupt triggered, logic  
10–22 k pull-up on host  
high indicates normal  
1.2 V CMOS compatible  
operation  
Link alarm  
status  
interrupt  
LASI  
9
Turns off laser. Optical  
Open drain compatible  
output power with laser  
14.7 k pull-up on transceiver  
turned off is less than -30  
1.2 V CMOS compatible  
dBm.  
Transmitter  
on/off  
TX ON/OFF  
RESET  
12  
Open drain compatible  
Logic high for normal  
Module reset  
Module detect  
10  
14  
14.7 K pull-up on transceiver  
operation, logic low for reset  
1.2 V CMOS compatible  
Indicates presence of  
module  
Connected to signal ground inside  
module through 1 KΩ resistor  
MOD DETECT  
APS  
7-8  
28–29  
Adaptive  
power supply  
The device requires 1.8V at these  
pins.  
Adaptive power supply input  
This pin is a direct sense of the  
APS voltage on pins 7–8 and  
28–29 at an internal point  
APS sense  
connection  
Adaptive power supply  
voltage select pin  
APS_SENSE  
APS_SET  
27  
25  
This pin will be connected to the  
ground inside module to direct an  
adaptive power supply to provide  
1.8 V.  
APS  
configuration  
Feedback input for APS  
5.0  
Data Output/Input Configuration  
The TXN17431 Optical Transceiver is fully compliant with IEEE 802.3ae standards for  
XAUI data format. Table 8 lists the I/O configuration. Table 9 lists the complete pinout  
for the TXN17431 Optical Transceiver.  
Table 8.  
Data Input/Output Configuration (Sheet 1 of 2)  
Pin Name  
In/Out  
Description  
Logic  
TX LANE0+  
TX LANE0-  
Transmitter XAUI input differential  
pair—Lane 0  
In  
Compliant with IEEE 802.3ae clause 47  
TX LANE1+  
TX LANE1-  
Transmitter XAUI input differential  
pair—Lane 1  
In  
In  
Compliant with IEEE 802.3ae clause 47  
Compliant with IEEE 802.3ae clause 47  
Compliant with IEEE 802.3ae clause 47  
Compliant with IEEE 802.3ae clause 47  
TX LANE2+  
TX LANE2-  
Transmitter XAUI input differential  
pair—Lane 2  
TX LANE3+  
TX LANE3-  
Transmitter XAUI input differential  
pair—Lane 3  
In  
RX LANE0+  
RX LANE0-  
Receiver XAUI output differential  
pair—Lane 0  
Out  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
Document Number: 306424-005  
Datasheet  
11  
Intel® TXN17431 (0850) Optical Transceiver  
Table 8.  
Data Input/Output Configuration (Sheet 2 of 2)  
Pin Name  
In/Out  
Description  
Logic  
RX LANE1+  
RX LANE1-  
Receiver XAUI output differential  
pair—Lane 1  
Out  
Compliant with IEEE 802.3ae clause 47  
RX LANE2+  
RX LANE2-  
Receiver XAUI output differential  
pair—Lane 2  
Out  
Out  
Compliant with IEEE 802.3ae clause 47  
Compliant with IEEE 802.3ae clause 47  
RX LANE3+  
RX LANE3-  
Receiver XAUI output differential  
pair—Lane 3  
Table 9.  
Pin Configuration (Sheet 1 of 3)  
Pin #  
Name  
In/Out  
Function  
Notes  
1
2
3
4
5
6
GND  
GND  
GND  
5.0 V  
3.3 V  
3.3 V  
–
–
–
–
–
–
Electrical ground  
Electrical ground  
Electrical ground  
Power  
1
1
1
2
2
2
Power  
Power  
Adaptive power supply input.  
7
8
APS  
APS  
I
I
The Intel® TXN17431(0850) 10.3 Gbps 850 nm Optical  
Transceiver uses 1.8 V  
–
–
Adaptive power supply input.  
The Intel® TXN17431(0850) 10.3 Gbps 850 nm Optical  
Transceiver uses 1.8 V  
9
LASI  
RESET  
NC  
O
I
Link alarm status interrupt  
Module reset  
–
–
–
–
–
10  
11  
12  
13  
–
I
Vendor specific, do not connect  
Transmitter shutoff  
TX ON/OFF  
NC  
–
Vendor specific, do not connect  
MOD  
DETECT  
14  
O
Indicates presence of module  
–
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
I2C_CLK  
I2C_DATA  
MDIO  
I
I
Clock line for I2C bus (Do not connect)  
Data line for I2C bus (Do not connect)  
Management data interface  
Clock for management data interface  
Port address bit 4  
–
–
–
–
–
–
–
–
–
–
I/O  
I
MDC  
PRTAD4  
PRTAD3  
PRTAD2  
PRTAD1  
PRTAD0  
NC  
I
I
Port address bit 3  
I
Port address bit 2  
I
Port address bit 1  
I
Port address bit 0  
–
Vendor specific, do not connect  
This pin is connected to ground inside the module through a  
0 Ω resistor for 1.8 V APS SENSE pin  
25  
APS_SET  
I
–
26  
27  
NC  
–
I
No Connect  
–
–
APS SENSE  
This pin is a direct sense of the APS voltage  
1. Ground connections are common for transmit and receive.  
2. VCC contacts are each rated at 0.5 A.  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
12  
2-Nov-2007  
Document Number: 306425-005  
Intel® TXN17431 (0850) Optical Transceiver  
Table 9.  
Pin Configuration (Sheet 2 of 3)  
Pin #  
Name  
In/Out  
Function  
Notes  
Adaptive power supply input.  
The TXN17431 Optical Transceiver uses 1.8 V.  
28  
APS  
I
–
Adaptive power supply input.  
The TXN17431 Optical Transceiver uses 1.8 V.  
29  
APS  
I
–
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
3.3 V  
3.3 V  
–
–
–
–
–
–
–
–
–
–
–
O
O
–
O
O
–
O
O
–
O
O
–
–
–
I
Power  
2
2
2
1
1
1
1
1
–
–
1
–
–
1
–
–
1
–
–
1
–
–
1
1
1
–
–
1
–
–
1
–
–
1
–
–
Power  
5.0 V  
Power  
GND  
Electrical ground  
GND  
Electrical ground  
GND  
Electrical ground  
GND  
Electrical ground  
GND  
Electrical ground  
NC  
No connect  
NC  
No connect  
GND  
Electrical ground  
RX LANE0+  
RX LANE0-  
GND  
Module XAUI output lane 0+  
Module XAUI output lane 0-  
Electrical ground  
RX LANE1+  
RX LANE1-  
GND  
Module XAUI output lane 1+  
Module XAUI output lane 1-  
Electrical ground  
RX LANE2+  
RX LANE2-  
GND  
Module XAUI output lane 2+  
Module XAUI output lane 2-  
Electrical ground  
RX LANE3+  
RX LANE3-  
GND  
Module XAUI output lane 3+  
Module XAUI output lane 3-  
Electrical ground  
GND  
Electrical ground  
GND  
Electrical ground  
TX LANE0+  
TX LANE0-  
GND  
Module XAUI input lane 0+  
Module XAUI input lane 0-  
Electrical ground  
I
–
I
TX LANE1+  
TX LANE1-  
GND  
Module XAUI input lane 1+  
Module XAUI input lane 1-  
Electrical ground  
I
–
I
TX LANE2+  
TX LANE2-  
GND  
Module XAUI input lane 2+  
Module XAUI input lane 2-  
Electrical ground  
I
–
I
TX LANE3+  
TX LANE3-  
Module XAUI input lane 3+  
Module XAUI input lane 3-  
I
1. Ground connections are common for transmit and receive.  
2. VCC contacts are each rated at 0.5 A.  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
Document Number: 306424-005  
Datasheet  
13  
Intel® TXN17431 (0850) Optical Transceiver  
Table 9.  
Pin Configuration (Sheet 3 of 3)  
Pin #  
Name  
In/Out  
Function  
Notes  
66  
67  
68  
69  
70  
GND  
NC  
–
–
–
–
–
Electrical ground  
No connect  
1
–
–
1
1
NC  
No connect  
GND  
GND  
Electrical ground  
Electrical ground  
1. Ground connections are common for transmit and receive.  
2. VCC contacts are each rated at 0.5 A.  
6.0  
MDIO Interface  
The TXN17431 Optical Transceiver supports the management data input/output (MDIO)  
interface as defined by IEEE 802.3ae Clause 45 and XENPAK MSA. This interface  
consists of the following:  
• A two-wire physical interface  
• A frame format  
• An MDIO register set  
• A timing relationship for reads and writes to the MDIO registers  
6.1  
6.2  
MDIO Physical Interface  
The two wires of the physical interface are the management data clock (MDC) and the  
MDIO. The MDC is an input clock signal to synchronize the MDIO data stream. The  
minimum clock period required is 400 ns with a minimum high pulse level and low  
pulse level at each 160 ns.  
The MDIO data stream is a serial bi-directional signal to send control and receive  
management status information. Please refer to the frame format section for exact bit  
transferring sequence.  
MDIO Access Frame Format  
The MDIO read and write operations use indirect register addressing. Thus, register  
addresses need to be pre-written as a setup for a subsequent read or write operation. A  
possible operation sequence uses the ADDRESS frame to reference the register location  
and then performs address incrementing (READ INC) for subsequent reads.  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
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2-Nov-2007  
Document Number: 306425-005  
Intel® TXN17431 (0850) Optical Transceiver  
Note: A single read only or write only does not automatically increment the address.  
Table 10.  
MDIO Frame Format  
Transaction Type  
PRE1  
ST2 Opcode3  
PRTAD4  
DID5  
TA6  
AD7  
IDLE8  
ADDRESS  
WRITE  
1…1  
1…1  
1…1  
1…1  
00  
00  
00  
00  
00  
01  
11  
10  
PRTAD[4:0]  
PRTAD[4:0]  
PRTAD[4:0]  
PRTAD[4:0]  
DID[4:0]  
DID[4:0]  
DID[4:0]  
DID[4:0]  
10  
10  
Z0  
Z0  
AD[15:0]  
AD[15:0]  
AD[15:0]  
AD[15:0]  
Z
Z
Z
Z
READ  
READ INC  
1. Preamble (PRE): A pattern of 32 logic one bits used for clock and data synchronization.  
2. Start of Frame (ST): Two bit logic 0 ensures transitions from default logic one to zero.  
3. Opcode: Indicates the MDIO transaction type. “00” indicates register addressing command, “01” indicates  
write data to register command, “11” indicates read data from register command, “10” indicates read data  
return and address increment.  
4. PRTAD: A 5-bit port address set through PRTAD[4:0] pins at the connector level.  
5. DID: Device address is 5 bits but only valid combinations are “00001” for accessing PMA/PMD, “00011” for  
accessing PCS and “00100” for accessing PHY XS.  
6. TA: Two bit time spacing between the addressing and data fields to avoid contention during a read  
transaction.  
7. AD: This address/data field is 16 bits; the most significant bit is transmitted/received first.  
8. IDLE: MDIO high impedance state will disable all three state drivers.  
6.3  
MDIO Register Set  
This section provides information on the location and functionality of the TXN17431  
Optical Transceiver Registers. The MDIO Register set is divided into the following five  
register sections:  
• “PMA/PMD Control Registers (Device ID = 1h)” on page 17  
Physical Medium Attachment/Physical Medium Dependent (PMA/PMD) control  
• “PCS Control Registers (Device ID = 3h)” on page 22  
Physical Coding Sublayer (PCS) control  
• “PHY_XS Control Registers (Device ID = 4h)” on page 26  
XGMII Extender Sublayer (PHY XGXS) control  
• “XENPAK NVR Registers and NVR EEPROM Description” on page 30  
• “XENPAK DOM/LASI Control and Status Registers” on page 31  
Unique device IDs address the various registers.  
Abbreviations under the register Access column are described as follows:  
Abbreviation Register Access Description  
RO  
Read only register: Writes are ignored  
Read and write register: Reads and writes are allowed with the proper read/write  
sequence  
R/W  
Read only register: The latched low bit is reset to high by a read unless the input low state  
is present  
RO, LL  
R/W, SC  
RO, LH  
Self clearing read/write register: The bit clears itself after transaction  
Read only register: Latched high bit is reset to low by a read unless the input high state is  
present  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
Document Number: 306424-005  
Datasheet  
15  
Intel® TXN17431 (0850) Optical Transceiver  
6.3.1  
Register Set  
Table 11 through Table 15 list the five register sets for the TXN17431 Optical  
Transceiver Register sets.  
Table 11.PMA/PMD Control Register Set: Device ID = 1h  
Address Register Name  
Reference  
0h  
1h  
“PMA/PMD Control 1 Register (DID = 1h, Address = 0h)”  
“PMA/PMD Status 1 Register (DID = 1h, Address = 1h)”  
“PMA/PMD Speed Ability Register (DID = 1h, Address = 4h)”  
“PMA/PMD Devices in Package Register (DID = 1h, Address = 5h)”  
“PMA/PMD Control 2 Register (DID = 1h, Address = 7h)”  
“PMA/PMD Status 2 Register (DID = 1h, Address = 8h)”  
“PMD Transmit Disable Register (DID = 1h, Address = 9h)”  
“PMD Receive Signal OK Register (DID = 1h, Address = ah)”  
“Package Identifier OUI Register (DID = 1h, Address = eh)”  
“Package Identifier OUI Register (DID = 1h, Address = fh)”  
“PMA Network Loopback Register (DID = 1h, Address = c001h)”  
“EEPROM Control Register (DID = 1h, Address = c003h)”  
“EEPROM Checksum Register (DID = 1h, Address = c004h)”  
Table 16 on page 17  
Table 17 on page 18  
Table 19 on page 18  
Table 20 on page 19  
Table 21 on page 19  
Table 22 on page 20  
Table 23 on page 20  
Table 24 on page 20  
Table 25 on page 20  
Table 26 on page 21  
Table 26 on page 21  
Table 27 on page 21  
Table 28 on page 22  
4h  
5h  
7h  
8h  
9h  
ah  
eh  
fh  
c001h  
c003h  
c004h  
Table 12.PCS Control Register Set: Device ID = 3h  
Address Register Name  
Reference  
0h  
1h  
4h  
5h  
7h  
“PCS Control 1 Register (DID = 3h, Address = 0h)”  
“PCS Status 1 Register (DID = 3h, Address = 1h)”  
“PCS Speed Ability Register (DID = 3h, Address = 4h)”  
“PCS Devices in Package Register (DID = 3h, Address = 5h)”  
“PCS Control 2 Register (DID = 3h, Address = 7h)”  
Table 29 on page 22  
Table 30 on page 22  
Table 31 on page 23  
Table 32 on page 23  
Table 33 on page 23  
“10GBASE-R PCS Jitter Test Pattern Seed A Registers (DID = 3h, Address  
= 22h to 25h)”  
22h-25h  
29h  
Table 37 on page 24  
Table 38 on page 25  
“10GBASE-R PCS Jitter Test Pattern Seed B Registers (DID = 3h, Address  
= 26h to 29h)”  
2bh  
“10GBASE-R PCS Jitter Test Counter Register (DID = 3h, Address = 2bh)” Table 40 on page 25  
c006h  
“Fiber PRBS Mode Register (DID = 3h, Address = c006h)”  
Table 42 on page 26  
Table 13.PHY_XS Control Register Set: Device ID = 4h (Sheet 1 of 2)  
Address Register Name  
Reference  
0h  
1h  
“PHY_XS Control 1 Register (DID = 4h, Address = 0h)”  
“PHY_XS Status 1 Register (DID = 4h, Address = 1h)”  
“PHY_XS Status 2 Register (DID = 4h, Address = 8h)”  
“PHY_XS Lane Status Register (DID = 4h, Address = 18h)”  
“PHY_XS Test Control Register (DID = 4h, Address = 19h)”  
“PHY_XS Control 2 Register (DID = 4h, Address = c000h)”  
Table 43 on page 26  
Table 44 on page 27  
Table 47 on page 27  
Table 48 on page 28  
Table 49 on page 28  
Table 50 on page 28  
8h  
18h  
19h  
c000h  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
16  
2-Nov-2007  
Document Number: 306425-005  
Intel® TXN17431 (0850) Optical Transceiver  
Table 13.PHY_XS Control Register Set: Device ID = 4h (Sheet 2 of 2)  
Address Register Name  
Reference  
c001h  
c002h  
“PHY_XS XAUI PRBS Status Register (DID = 4h, Address = c001h)”  
“PHY_XS Rate Adjust Register (DID = 4h, Address = c002h)”  
Table 51 on page 29  
Table 52 on page 29  
“PHY_XS Receive Code Violation Counter Register (DID = 4h, Address =  
c008h)”  
c008h  
Table 53 on page 30  
Table 14.XENPAK NVR Register Set and NVR EEPROM Description  
Address Register Name  
Reference  
8000h  
8106h  
1h  
“PMA/PMD EEPROM Control Register (DID = 1h, Address = 8000h)”  
Table 54 on page 30  
“EEPROM Registers (DID = 1h, from Address = 8007h to Address =  
8106h)”  
Table 55 on page 30  
Table 56 on page 31  
“EEPROM Register Mapping Information (DID = 1h)”  
Table 15.XENPAK DOM/LASI Control and Status Register Set  
Address Register Name  
Reference  
9000h  
9001h  
9002h  
9003h  
9004h  
9005h  
9006h  
9007h  
“RX_ALARM Enable Register (DID = 1h, Address = 9000h)”  
“TXALARM Enable Register (DID = 1h, Address = 9001h)”  
“LASI Control Register (DID = 1h, Address = 9002h)”  
“RXALARM Status Register (DID = 1h, Address = 9003h)”  
“TXALARM Status Register (DID = 1h, Address = 9004h)”  
“LASI Status Register (DID = 1h, Address = 9005h)”  
“DOM Tx_flag Control Register (DID = 1h, Address = 9006h)”  
“DOM Rx_flag Control Register (DID = 1, Address = 9007h)”  
Table 57 on page 31  
Table 58 on page 32  
Table 59 on page 32  
Table 60 on page 32  
Table 61 on page 33  
Table 62 on page 33  
Table 63 on page 34  
Table 64 on page 34  
A000h-  
A069h,  
A072h-  
A0FFh  
“DOM Registers (DID = 1, Address = A000h to A069h, A072h to A0FFh)”  
Table 65 on page 34  
A070h  
A071h  
A100h  
“DOM – Tx_flag Status Register (DID = 1, Address = A070h)”  
“DOM – Rx_flag Status Register (DID = 1, Address = A071h)”  
“DOM Command and Status Register (DID = 1, Address = A100h)”  
Table 66 on page 34  
Table 67 on page 35  
Table 68 on page 35  
6.3.2  
PMA/PMD Control Registers (Device ID = 1h)  
Using MDIO to access registers listed in Section 6.3.2 monitors and controls the PMA  
and PMD portion of the TXN17431 Optical Transceiver (see Table 16 through Table 28).  
Table 16.  
PMA/PMD Control 1 Register (DID = 1h, Address = 0h) (Sheet 1 of 2)  
Bit  
Functionality  
Description  
Access  
0 = Normal operation  
1 = Reset  
15  
14  
13  
12  
PMA/PMD reset  
Reserved  
R/W, SC  
–
–
R/W  
–
0 = Ignored  
1 = Operation at 10 Gbps and above  
Speed selection  
Reserved  
–
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
Document Number: 306424-005  
Datasheet  
17  
Intel® TXN17431 (0850) Optical Transceiver  
Table 16.  
PMA/PMD Control 1 Register (DID = 1h, Address = 0h) (Sheet 2 of 2)  
Bit  
Functionality  
Description  
Access  
0 = Normal operation (default)  
1 = Low power mode  
11  
Low power  
R/W  
10:7  
6
Reserved  
–
–
Speed selection  
1 = Operation at 10 Gbps and above (writes ignored)  
R/W  
1 = Ignored; 0 = operation at 10 Gbps and above  
(writes ignored)  
5
4
3
Speed selection  
Speed selection  
Speed selection  
R/W  
R/W  
R/W  
0 = Operation at 10 Gbps and above (writes ignored)  
1 = Ignored  
1 = Ignored; 0 = operation at 10 Gbps and above  
(writes ignored)  
0 = Operation at 10 Gbps and above (writes ignored)  
1 = Ignored  
2
1
0
Speed Selection  
Reserved  
R/W  
R/W  
R/W  
–
0 = Disable PMA loopback  
1 = Enable PMA loopback  
PMA loopback  
Table 17.  
PMA/PMD Status 1 Register (DID = 1h, Address = 1h)  
Bit  
Functionality  
Description  
Access  
15:8  
Reserved  
–
–
0 = No PMA/PMD fault detected  
1 = PMA/PMD fault detected  
7
6:3  
2
Local PMA/PMD fault  
Reserved  
RO  
–
–
0 = PMA not locked to receive signal  
1 = PMA locked to receive signal  
Receive link status  
RO,LL  
0 = PMA/PMD does not support low power mode  
1 = PMA/PMD supports low power mode  
1
0
Low power capability  
Reserved  
RO  
–
–
Table 18.  
Table 19.  
PMA/PMD Speed Ability Register (DID = 1h, Address = 4h)  
Bit  
Functionality  
Description  
Access  
15:1  
Reserved  
–
–
1 = PMA/PMD capable of operating at 10 Gbps  
(default)  
0
Speed ability  
RO  
PMA/PMD Devices in Package Register (DID = 1h, Address = 5h) (Sheet 1 of  
2)  
Bit  
Functionality  
Description  
Access  
15:6  
Reserved  
–
–
5
4
3
DTE_XS presence  
PHY_XS presence  
PCS_presence  
0 = DTE_XS not present in package  
1 = PHY_XS present in package  
1 = PCS present in package  
RO  
RO  
RO  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
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2-Nov-2007  
Document Number: 306425-005  
Intel® TXN17431 (0850) Optical Transceiver  
Table 19.  
PMA/PMD Devices in Package Register (DID = 1h, Address = 5h) (Sheet 2 of  
2)  
Bit  
Functionality  
Description  
Access  
2
1
WIS_presence  
0 = WIS not present in package  
1 = PMA/PMD present in package  
RO  
RO  
PMA/PMD presence  
Clause 22 registers  
presence  
0
0 = IEEE clause 22 registers not present in package  
RO  
Table 20.  
PMA/PMD Control 2 Register (DID = 1h, Address = 7h)  
Bit  
Functionality  
Description  
Access  
15:3  
Reserved  
–
–
110 = indicates 10GBASE-LR PMA/PMD Type  
101 = indicates 10GBASE-ER PMA/PMD Type  
111 = indicates 10GBASE-SR PMA/PMD Type (default)  
2:0  
PMA/PMD type  
RO  
Table 21.  
PMA/PMD Status 2 Register (DID = 1h, Address = 8h)  
Bit  
Functionality  
Description  
Access  
15  
14  
Device present  
Device present  
1 = Default  
0 = Default  
RO  
RO  
Transmit fault  
detectability  
1 = Default, indicate PMA/PMD has ability to detect  
transmit fault  
13  
12  
11  
RO  
RO  
Receive fault  
detectability  
1 = Default, indicate PMA/PMD has ability to detect  
receive fault  
0 = No transmit local fault detected  
1 = Transmit local fault detected  
Transmit fault  
RO, LH  
0 = No receive local fault detected  
1 = Receiver local fault detected  
10  
9
Receive fault  
Reserved  
RO,LH  
–
–
PMD transmit disable  
ability  
8
1 = Default  
RO  
7
6
5
4
3
2
1
0
10GBASE-SR ability  
10GBASE-LR ability  
10GBASE-ER ability  
10GBASE-LX4 ability  
10GBASE-SW ability  
10GBASE-LW ability  
10GBASE-EW ability  
PMA loopback ability  
1 = Default  
0 = Default  
0 = Default  
0 = Default  
0 = Default  
0 = Default  
0 = Default  
1 = Default  
RO  
RO  
RO  
RO  
RO  
RO  
RO  
RO  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
Document Number: 306424-005  
Datasheet  
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Intel® TXN17431 (0850) Optical Transceiver  
Table 22.  
PMD Transmit Disable Register (DID = 1h, Address = 9h)  
Bit  
Functionality  
Description  
Access  
15:5  
Reserved  
–
–
PMD transmit disable  
lane 3  
4
3
2
1
0
0 = Default (no PMD lane 3 support)  
0 = Default (no PMD lane 2 support)  
0 = Default (no PMD lane 1 support)  
0 = Default (no PMD lane 0 support)  
RO  
RO  
PMD transmit disable  
lane 2  
PMD transmit disable  
lane 1  
RO  
PMD transmit disable  
lane 0  
RO  
Global PMD transmit  
disable  
0 = Transmitter enable  
1 = Transmitter disable  
R/W  
Table 23.  
PMD Receive Signal OK Register (DID = 1h, Address = ah)  
Bit  
Functionality  
Description  
Access  
15:5  
Reserved  
–
–
PMD receive signal OK  
lane 3  
4
3
2
1
0
0 = Default, no PMD lane 3 support  
0 = Default, no PMD lane 2 support  
0 = Default, no PMD lane 1 support  
0 = Default, no PMD lane 0 support  
RO  
RO  
RO  
RO  
RO  
PMD receive signal OK  
lane 2  
PMD receive signal OK  
lane 1  
PMD receive signal OK  
lane 0  
Global PMD receive  
signal OK  
0 = Signal not OK on receive  
1 = Signal OK on receive  
Table 24.  
Package Identifier OUI Register (DID = 1h, Address = eh)  
Bit  
Functionality  
Description  
Access  
Package identifier OUI byte (pre-programmed), also  
mapped to 1.8033H.7:0  
15:8  
EEPROM register 44  
RO  
Package identifier OUI byte (pre-programmed), also  
mapped to 1.8032H7:0  
7:0  
EEPROM register 43  
RO  
Table 25.  
Package Identifier OUI Register (DID = 1h, Address = fh)  
Bit  
Functionality  
Description  
Access  
Package identifier OUI byte (pre-programmed), also  
mapped to 1.8035H.7:0  
15:8  
EEPROM register 46  
RO  
Package identifier OUI byte (pre-programmed), also  
mapped to 1.8034H.7:0  
7:0  
EEPROM register 45  
RO  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
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2-Nov-2007  
Document Number: 306425-005  
Intel® TXN17431 (0850) Optical Transceiver  
Table 26.  
PMA Network Loopback Register (DID = 1h, Address = c001h)  
Bit  
Functionality  
Description  
Access  
15:11  
Reserved  
–
–
0 = No override (default)  
1 = RXLOSB_I override  
10  
RxLOSB_I override  
R/W  
0 = Received data at RxXAUI when in network loopback  
mode (default)  
1 = Transmit all idles at RxXAUI when in network  
loopback mode  
Network loopback data  
out enable  
9
R/W  
8:5  
4
Reserved  
–
–
Network loopback  
enable  
0 = Disable network loopback  
1 = Enable network loopback  
R/W  
3
2
1
0
Reserved  
erefmon  
sync_err  
txlock  
–
RO  
RO  
1 = EREFCLK present  
1 = Recovered clock rate error  
1 = Fiber transmit PLL in lock  
RO,LH  
RO  
Table 27.  
EEPROM Control Register (DID = 1h, Address = c003h)  
Bit  
Functionality  
Description  
Access  
15  
Reserved  
–
–
EEPROM test mode  
frequency  
0 = 37 kHz (default)  
14  
R/W  
1 = High frequency test mode  
1 = EEPROM detected  
1 = EEPROM error (clear on read)  
1 = EEPROM access in progress  
–
13  
12  
11  
10:8  
7
EEPROM detected  
EEPROM error  
EEPROM active  
Reserved  
RO  
RO, LH  
RO  
–
EEPROM checksum OK  
Reserved  
1 = OK (clear on read)  
–
RO, LH  
–
6
00 =1 byte  
01 =8 bytes  
10 =16 bytes  
11 = 256 bytes (default)  
5:4  
3:2  
1:0  
EEPROM burst read size  
Reserved  
R/W  
–
–
00 =1 byte  
01 =8 bytes (default)  
10 =16 bytes  
11 = 1 byte  
EEPROM burst write size  
R/W  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
Document Number: 306424-005  
Datasheet  
21  
Intel® TXN17431 (0850) Optical Transceiver  
Table 28.  
EEPROM Checksum Register (DID = 1h, Address = c004h)  
Bit  
Functionality  
Description  
Access  
EEPROM calculated  
checksum  
Checksum value calculated over EEPROM addresses 0-  
99  
15:8  
7:4  
RO  
–
Reserved  
–
00 =1 byte  
01 =8 bytes (default)  
10 =16 byte  
11 = 1 byte  
DOM 256 byte write  
burst size  
3:2  
1:0  
R/W  
R/W  
00 =Reserved  
01 =Reserved  
10 =Reserved  
DOM Write Command  
11 = Write 256 bytes  
6.3.3  
PCS Control Registers (Device ID = 3h)  
Using MDIO to access registers listed in Section 6.3.3 will monitor and control the  
TXN17431 Optical Transceiver Physical Coding Sublayer (PCS) portion (see Table 29  
through Table 42).  
Table 29.  
PCS Control 1 Register (DID = 3h, Address = 0h)  
Bit  
Functionality  
Description  
Access  
0 = Normal operation  
1 = Reset  
15  
PCS 64/66 reset  
R/W, SC  
0 = Disable PCS loopback  
1 = Enable PCS loopback mode  
14  
PCS loopback  
R/W  
13  
12  
Speed selection  
Reserved  
1 = Operation at 10 Gbps and above (default)  
Value always 0, write ignored  
RO  
R/W  
0 = Normal operation  
1 = Low power mode  
11  
Low power  
R/W  
10:7  
6
Reserved  
–
–
Speed selection  
Speed selection  
Speed selection  
Speed selection  
Speed selection  
Reserved  
1 = Operation at 10 Gbps and above (default)  
0 = Operation at 10 Gbps and above (default)  
0 = Operation at 10 Gbps and above (default)  
0 = Operation at 10 Gbps and above (default)  
0 = Operation at 10 Gbps and above (default)  
–
RO  
RO  
RO  
RO  
RO  
–
5
4
3
2
1:0  
Table 30.  
PCS Status 1 Register (DID = 3h, Address = 1h) (Sheet 1 of 2)  
Bit  
Functionality  
Description  
Access  
15:8  
Reserved  
–
–
Local fault condition  
detected  
0 = No fault detected  
1 = Fault detected  
7
RO  
–
6:3  
Reserved  
–
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
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2-Nov-2007  
Document Number: 306425-005  
Intel® TXN17431 (0850) Optical Transceiver  
Table 30.  
PCS Status 1 Register (DID = 3h, Address = 1h) (Sheet 2 of 2)  
Bit  
Functionality  
Description  
Access  
0 = PCS receive link status down  
1 = PCS receive link status up  
2
PCS receive link status  
RO,LL  
0 = PCS does not support low power mode  
1 = PCS supports low power mode  
1
0
Low power ability  
Reserved  
RO  
–
–
Table 31.  
Table 32.  
PCS Speed Ability Register (DID = 3h, Address = 4h)  
Bit  
Functionality  
Description  
Access  
15:1  
0
Reserved  
–
–
10 G capable  
1 = PCS capable of operating at 10 G (default)  
RO  
PCS Devices in Package Register (DID = 3h, Address = 5h)  
Bit  
Functionality  
Description  
Access  
15:6  
Reserved  
–
–
5
4
3
2
1
DTE_XS presence  
PHY_XS presence  
PCS_presence  
WIS_presence  
PMA/PMD presence  
0 = DTE_XS not present in package  
1 = PHY_XS present in package  
1 = PCS present in package  
RO  
RO  
RO  
RO  
RO  
0 = WIS not present in package  
1 = PMA/PMD present in package  
Clause 22 registers  
presence  
0
0 = IEEE clause 22 registers not present in package  
RO  
Table 33.  
PCS Control 2 Register (DID = 3h, Address = 7h)  
Bit  
Functionality  
Description  
Access  
15:2  
Reserved  
–
–
1
0
PCS type selection  
PCS type selection  
0 = Select 10GBASE-R PCS type  
0 = Select 10GBASE-R PCS type  
R/W  
R/W  
Table 34.  
10 G PCS Status 2 Register (DID = 3h, Address = 8h) (Sheet 1 of 2)  
Bit  
Functionality  
Description  
Access  
15  
14  
Device present  
Device present  
Reserved  
1 = Default  
0 = Default  
–
RO  
RO  
–
13:12  
Transmit local fault  
detect  
0 = No fault detected  
1 = PCS transmit local fault detected  
11  
RO, LH  
Receive local fault  
detect  
0 = No fault detected  
1 = PCS receive local fault detected  
10  
RO,LH  
–
9:3  
Reserved  
–
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
Document Number: 306424-005  
Datasheet  
23  
Intel® TXN17431 (0850) Optical Transceiver  
Table 34.  
10 G PCS Status 2 Register (DID = 3h, Address = 8h) (Sheet 2 of 2)  
Bit  
Functionality  
Description  
Access  
10GBASE-W PCS  
capable  
2
1
0
0 = Default (10GBASE-W PCS not supported)  
RO  
RO  
RO  
10GBASE-X PCS capable 0 = Default (10GBASE-X PCS not supported)  
10GBASE-R PCS  
1 = Default (10GBASE-R PCS supported)  
capable  
Table 35.  
10GBASE-R PCS Status 1 Register (DID = 3h, Address = 20h)  
Bit  
Functionality  
Description  
Access  
15:13  
Reserved  
–
–
0 = 10GBASE-R PCS Receive link down  
1 = 10GBASE-R PCS Receive link up  
12  
11:3  
2
Receive link status  
Reserved  
RO  
–
–
PRBS31 test mode  
support  
0 = PRBS mode not supported  
1 = PRBS mode supported;  
RO  
10GBASE-R PCS high  
BER  
0 = 10GBASE-R PCS not reporting high BER  
1 = 10GBASE-R PCS reporting high BER  
1
0
RO  
RO  
10GBASE-R PCS block  
lock  
0 = 10GBASE-R PCS not locked to received blocks  
1 = 10GBASE-R PCS locked to received blocks  
Table 36.  
10GBASE-R PCS Status Register 2 (DID = 3h, Address = 21h)  
Bit  
Functionality  
Description  
Access  
0 = 10GBASE-R PCS does not have block lock  
1 = 10GBASE-R PCS has block lock  
15  
Latched block lock  
RO,LL  
0 = 10GBASE-R PCS has not reported high BER  
1 = 10GBASE-R PCS has reported high BER  
14  
13:8  
7:0  
Latched high BER  
BER counter  
RO,LH  
RO,NR  
RO,NR  
BER Counter in binary (MSB at bit 13, LSB at bit 8)  
Errored blocks counter  
(MSB)  
Errored blocks counter in binary (MSB at bit 7, LSB at bit  
0)  
Table 37.  
10GBASE-R PCS Jitter Test Pattern Seed A Registers (DID = 3h, Address = 22h  
to 25h)  
Bit  
Functionality  
Description  
Access  
15:0  
(22h)  
Bit 15 to Bit 0  
Jitter Test Pattern (bit 15 to Bit 0) Reg A0  
R/W  
15:0  
Bit 31 to Bit 16  
Bit 47 to Bit 32  
Reserved  
Jitter Test Pattern (bit 31 to bit 16) Reg A1  
Jitter Test Pattern (bit 47 to Bit 32) Reg A2  
–
R/W  
R/W  
R/W  
R/W  
(23h)  
15:0  
(24h)  
15:10  
(24h)  
9:0  
(24h)  
Bit 57 to Bit 48  
Jitter Test Pattern (bit 57 to bit 48) Reg A3  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
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Document Number: 306425-005  
Intel® TXN17431 (0850) Optical Transceiver  
Table 38.  
10GBASE-R PCS Jitter Test Pattern Seed B Registers (DID = 3h, Address = 26h  
to 29h)  
Bit  
Functionality  
Description  
Access  
15:0  
(26h)  
Bit 15 to Bit 0  
Jitter Test Pattern (bit 15 to Bit 0) Reg B0  
R/W  
15:0  
Bit 31 to Bit 16  
Bit 47 to Bit 32  
Reserved  
Jitter Test Pattern (bit 31 to bit 16) Reg B1  
Jitter Test Pattern (bit 47 to Bit 32) Reg B2  
–
R/W  
R/W  
R/W  
R/W  
(27h)  
15:0  
(28h)  
15:10  
(29h)  
9:0  
(29h)  
Bit 57 to Bit 48  
Jitter Test Pattern (bit 57 to bit 48) Reg B3  
Table 39.  
10GBASE-R PCS Test Control Register (DID = 3h, Address = 2ah)  
Bit  
Functionality  
Description  
Access  
15:6  
Reserved  
–
–
Receive PRBS31 checker 0 = Not enabled (default)  
5
4
3
2
1
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
enable  
1 = Enable Rx PRBS31 checker  
Transmit PRBS31  
generator enable  
0 = Not enabled (default)  
1 = Enable Tx PRBS31  
Transmit jitter test  
pattern enable  
0 = Disable transmit jitter test  
1 = Enable transmit jitter test  
Receive jitter test  
pattern enable  
0 = Disable receive jitter test  
1 = Enable receive jitter test  
Jitter test pattern data  
select  
0 = Pseudo random test pattern  
1 = Square wave test pattern  
0 = LF data pattern  
1 = Zeros data pattern  
Jitter test pattern select  
Table 40.  
10GBASE-R PCS Jitter Test Counter Register (DID = 3h, Address = 2bh)  
Bit  
Functionality  
Description  
Access  
15:0  
Jitter test error counter Jitter test error count (MSB at bit 15, LSB at bit 0)  
RO, NR  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
Document Number: 306424-005  
Datasheet  
25  
Intel® TXN17431 (0850) Optical Transceiver  
Table 41.  
10GBASE-R PCS Test Register (DID = 3h, Address = c000h)  
Bit  
Functionality  
Description  
1 = BER Test Completed  
Access  
15  
14  
13  
BER Test Complete  
BER Test in Progress  
Reserved  
RO/LH  
RO  
1 = BER Test in Progress  
–
RO  
0 = Disabled (default)  
1 = Enabled  
12  
BER TEST Enable  
Reserved  
R/W  
RO  
11:6  
–
0 = Transmit square wave (00ffh) when in PCS loopback  
PCS loopback data out  
enable  
mode  
5
R/W  
1 = Transmit data at output when in PCS loopback  
mode  
0 = Reset  
4
3
2
1
0
Reset transmit PCS  
Reset receive PCS  
R/W  
R/W  
1 = Not reset (default) not self clearing  
0 = Reset  
1 = Not reset (default) not self clearing  
Transmit scrambler  
bypass  
0 = No operation  
1 = Bypass activated  
R/W  
Receive descrambler  
bypass  
0 = No operation  
1 = Bypass activated  
R/W  
0 = No error detected  
1 = Error detected  
64/66 encoder error  
RO,LH  
Table 42.  
Fiber PRBS Mode Register (DID = 3h, Address = c006h)  
Bit  
Functionality  
Description  
Access  
Bit 15 = MSB  
Bit 8 = LSB  
15:8  
6:0  
Fiber PRBS error count  
Receive frame offset  
RO  
RO  
–
6.3.4  
PHY_XS Control Registers (Device ID = 4h)  
Using MDIO to access registers listed in Section 6.3.4 will monitor and control the PHY  
XGMII Extender Sublayer portion of the TXN17431 Optical Transceiver (see Table 43  
through  
Table 53).  
Table 43.  
PHY_XS Control 1 Register (DID = 4h, Address = 0h) (Sheet 1 of 2)  
Bit  
Functionality  
Description  
Access  
0 = Normal operation  
1 = Reset  
15  
Reset  
R/W, SC  
PHY_XS loopback  
enable  
0 = No loopback enable  
1 = Enable PHY_XS loopback  
14  
R/W  
13  
12  
Speed selection  
Reserved  
1 = Operation at 10 Gbps and above  
–
RO  
–
0 = Do not power down  
1 = Power down  
11  
Power down  
RW  
10:7  
6
Reserved  
–
–
Speed selection  
1 = Operation at 10 Gbps and above  
RO  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
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Document Number: 306425-005  
Intel® TXN17431 (0850) Optical Transceiver  
Table 43.  
PHY_XS Control 1 Register (DID = 4h, Address = 0h) (Sheet 2 of 2)  
Bit  
Functionality  
Description  
Access  
5
4
Speed selection  
Speed selection  
Speed selection  
Speed selection  
Reserved  
0 = Operation at 10 Gbps and above  
0 = Operation at 10 Gbps and above  
0 = Operation at 10 Gbps and above  
0 = Operation at 10 Gbps and above  
–
RO  
RO  
RO  
RO  
–
3
2
1:0  
Table 44.  
PHY_XS Status 1 Register (DID = 4h, Address = 1h)  
Bit  
Functionality  
Description  
Access  
15:8  
Reserved  
–
–
0 = No fault condition  
7
6:3  
2
Local fault  
RO  
–
1 = Fault condition detected  
Reserved  
–
0 = Transmit link down  
1 = Transmit link up  
Transmit link status  
RO, LL  
0 = No capability to power down  
1 = Ability to power down  
1
0
Power down capability  
Reserved  
RO  
–
–
Table 45.  
Table 46.  
PHY_XS Speed Ability Register (DID = 4h, Address = 4h)  
Bit  
Functionality  
Description  
Access  
15:1  
0
Reserved  
–
–
Speed ability  
1 = PHY_XS capable of operating at 10 Gbps  
RO  
PHY_XS Devices in Package Register (DID = 4h, Address = 5h)  
Bit  
Functionality  
Description  
Access  
15:6  
Reserved  
–
–
5
4
3
2
1
DTE_XS presence  
PHY_XS presence  
PCS_presence  
WIS_presence  
PMA/PMD presence  
0 = DTE_XS not present in package  
1 = PHY_XS present in package  
1 = PCS present in package  
RO  
RO  
RO  
RO  
RO  
0 = WIS not present in package  
1 = PMA/PMD present in package  
Clause 22 registers  
presence  
0
0 = IEEE clause 22 registers not present in package  
RO  
Table 47.  
PHY_XS Status 2 Register (DID = 4h, Address = 8h) (Sheet 1 of 2)  
Bit  
Functionality  
Device present  
Description  
Access  
15  
14  
1 = Device responding at this address (default)  
RO  
RO  
–
Device present  
Reserved  
0 = Device responding at this address (default)  
–
13:12  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
Document Number: 306424-005  
Datasheet  
27  
Intel® TXN17431 (0850) Optical Transceiver  
Table 47.  
PHY_XS Status 2 Register (DID = 4h, Address = 8h) (Sheet 2 of 2)  
Bit  
Functionality  
Description  
Access  
Transmit local fault  
detect  
0 = No fault detected  
1 = Transmit local fault detected  
11  
RO, LH  
Receive local fault  
detect  
0 = No fault detected  
10  
RO, LH  
–
1 = Receive local fault detected  
9:0  
Reserved  
–
Table 48.  
PHY_XS Lane Status Register (DID = 4h, Address = 18h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:13  
–
–
XGXS transmit lane  
alignment  
0 = Lanes no aligned  
1 = Lanes aligned  
12  
11  
RO  
RO  
PHY_XS pattern testing  
ability  
0 = Capable of PHY_XS pattern testing  
10  
PHY_XS loopback ability 1 = Capable of PHY_XS loopback ability  
RO  
–
9:4  
Reserved  
–
0 = Lane not in synch  
1 = Lane in synch  
3
2
1
0
Lane 3 synchronization  
RO  
RO  
RO  
RO  
0 = Lane not in synch  
1 = Lane in synch  
Lane 2 synchronization  
Lane 1 synchronization  
Lane 0 synchronization  
0 = Lane not in synch  
1 = Lane in synch  
0 = Lane not in synch  
1 = Lane in synch  
Table 49.  
PHY_XS Test Control Register (DID = 4h, Address = 19h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:3  
–
–
XGXS test pattern  
enable  
0 = Disable  
1 = Enable  
2
R/W  
00 =High speed  
01 =Low speed  
10 =Mixed speed  
11 = Reserved  
1:0  
Test pattern select  
R/W  
Table 50.  
PHY_XS Control 2 Register (DID = 4h, Address = c000h) (Sheet 1 of 2)  
Bit  
Functionality  
Description  
Access  
0 = Transmit all ones when in PHY_XS loopback mode  
1 = Transmit data at TXOUT when in PHY_XS loopback  
mode  
XAUI system loopback  
data out enable  
15  
R/W  
14  
13  
XAUI system loopback  
XAUI PRBS enable  
1 = Enable loopback (transmit -> receive path)  
R/W  
R/W  
0 = Not enabled  
1 = Enable PRBS  
XAUI Analog Monitor  
Point Control  
0 = XAUI lane 3 recovered clock  
1 = XAUI lane 3 recovered data  
12  
R/W  
–
11:8  
Reserved  
–
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Datasheet  
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Intel® TXN17431 (0850) Optical Transceiver  
Table 50.  
PHY_XS Control 2 Register (DID = 4h, Address = c000h) (Sheet 2 of 2)  
Bit  
Functionality  
Lane 3 lock  
Description  
Access  
0 = Lane 3 not in lock  
7
RO  
1 = Lane 3 in lock  
0 = Lane 2 not in lock  
1 = Lane 2 in lock  
6
5
4
Lane 2 lock  
Lane 1 lock  
Lane 0 lock  
RO  
RO  
RO  
0 = Lane 1 not in lock  
1 = Lane 1 in lock  
0 = Lane 0 not in lock  
1 = Lane 0 in lock  
Receive path XAUI PLL  
lock  
0 = PLL not locked  
1 = PLL locked  
3
2
1
RO  
–
Reserved  
–
0 = Reset  
1 = Not reset (default) not self clearing  
Receive XGXS reset  
R/W  
0 = Reset  
1 = Not reset (default) not self clearing  
0
Transmit XGXS reset  
R/W  
Table 51.  
PHY_XS XAUI PRBS Status Register (DID = 4h, Address = c001h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:4  
–
–
0 = No error detected  
3
2
1
0
XAUI lane 3 PRBS error  
XAUI lane 2 PRBS error  
XAUI lane 1 PRBS error  
XAUI lane 0 PRBS error  
RO, LH  
RO, LH  
RO, LH  
RO, LH  
1 = Error detected (cleared on read)  
0 = No error detected  
1 = Error detected (cleared on read)  
0 = No error detected  
1 = Error detected (cleared on read)  
0 = No error detected  
1 = Error detected (cleared on read)  
Table 52.  
PHY_XS Rate Adjust Register (DID = 4h, Address = c002h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:10  
–
–
XGXS transmit rate  
adjust overflow  
9
8
7
1 = Overflow  
RO, LH  
RO, LH  
RO, LH  
XGXS transmit rate  
adjust underflow  
1 = Underflow  
1 = Overflow  
XGXS receive rate  
adjust overflow  
XGXS receive rate  
adjust underflow  
6
1 = Underflow  
–
RO,LH  
–
5:0  
Reserved  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
Document Number: 306424-005  
Datasheet  
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Intel® TXN17431 (0850) Optical Transceiver  
Table 53.  
PHY_XS Receive Code Violation Counter Register (DID = 4h, Address =  
c008h)  
Bit  
Functionality  
Description  
Access  
Bit 15 = MSB  
Bit 0 = LSB; clear on read  
PHY_XS receive code  
violation counter  
15:0  
RO, NR  
6.3.5  
XENPAK NVR Registers and NVR EEPROM Description  
Table 54 through Table 56 provide the XENPAK NVR Registers and NVR EEPROM  
Register description.  
Table 54.  
PMA/PMD EEPROM Control Register (DID = 1h, Address = 8000h)  
Bit  
Functionality  
Description  
EEPROM register number  
Access  
EEPROM address for  
single byte write/read  
15:8  
7:6  
5
RW  
–
Reserved  
–
0 = Read mode  
1 = Write mode  
R/W command  
Reserved  
R/W  
–
4
–
00 =No command  
01 =Previous command  
10 =Reserved  
11 = Previous command failed  
3:2  
1:0  
Command status  
RO, LH  
R/W  
00 =Reserved  
01 =Reserved  
10 =Read or write one byte  
11 = Read or write 256 bytes  
EEPROM command  
A total of 256 registers are mapped into this address range. Table 55 lists an example  
of how each 16 bits are arranged.  
Table 55.  
EEPROM Registers (DID = 1h, from Address = 8007h to Address = 8106h)  
Bit  
Functionality  
Description  
Access  
Address = 8007h  
15:8  
7:0  
Reserved  
–
RO  
RO  
EEPROM register 0  
Bit 7 is MSB, Bit 0 is LSB  
Address = 8106h  
15:8  
7:0  
Reserved  
–
RO  
RO  
EEPROM register 255  
Bit 7 is MSB, Bit 0 is LSB  
The TXN17431 Optical Transceiver has an EEPROM with 256 register locations. Out of  
the 256 register locations, 48 registers are designated as customer writable areas and  
four registers are for package identifier OUI. The remaining registers are for internal  
operation.  
The customer writable EEPROM area is accessed through the standard MDIO read/write  
interface per IEEE 802.3ae clause 45. Data must first be written into the corresponding  
MDIO registers designated as a customer writable area. The MDIO data is then  
transferred to the EEPROM through transactions in 1.C003 and 1.8000 (EEPROM  
control registers).  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
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Intel® TXN17431 (0850) Optical Transceiver  
Table 56.  
EEPROM Register Mapping Information (DID = 1h)  
EEPROM  
Register #  
(dec.)  
MDIO Address  
(hex.)  
Description  
Access  
0
6
8007  
800d  
800e  
8018  
First register used for checksum calculation  
Customer field address  
RO  
RO  
RO  
RO  
7
Vendor field address  
17  
10GBASE type  
Package identifier OUI (mapped to MDIO 1.14 lower  
byte)  
43  
44  
45  
8032  
8033  
8034  
RO  
RO  
RO  
Package identifier OUI (mapped to MDIO 1.14 upper  
byte)  
Package identifier OUI (mapped to MDIO 1.15 lower  
byte)  
Package identifier OUI (mapped to MDIO 1.15 upper  
byte)  
46  
82  
8035  
8059  
807A  
RO  
RO  
RO  
Default last lower protected EEPROM register  
DOM capability bits 2:0 are DOM device address  
LSB, bit 6 indicate if DOM is implemented  
115  
116  
117  
807B  
807C  
DOM control/status  
RO  
RO  
RO  
R/W  
R/W  
–
Last register used for checksum calculation  
Basic field checksum value  
Start of customer writable area  
End of customer writable area  
Reserved  
118  
807D  
119  
807e  
166  
80ad  
167 to 255  
80ae to 8106  
6.3.6  
XENPAK DOM/LASI Control and Status Registers  
Table 57 through Table 68 cover the XENPAK DOM/LASI Control and Status Registers.  
Table 57.  
RX_ALARM Enable Register (DID = 1h, Address = 9000h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:7  
–
R/W  
PHY_XS receive buffer  
over/underflow error  
enable  
0 = Disable (default)  
1 = Enable  
6
R/W  
5
4
Reserved  
–
–
PMA/PMD receive local  
fault enable  
0 = Disable  
1 = Enable (default)  
R/W  
PCS receive local fault  
enable  
0 = Disable  
1 = Enable (default)  
3
2
1
0
R/W  
R/W  
R/W  
R/W  
PCS receive code  
violation enable  
0 = Disable (default)  
1 = Enable  
0 = Disable (default)  
1 = Enable  
Rx_flag enable  
PHY_XS receive local  
fault enable  
0 = Disable  
1 = Enable (default)  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
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Intel® TXN17431 (0850) Optical Transceiver  
Table 58.  
TXALARM Enable Register (DID = 1h, Address = 9001h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:11  
–
–
PHY XS Code Violation  
Error Enable  
0 = Disable (default)  
1 = Enable  
10  
9:7  
6
R/W  
–
Reserved  
–
0 = Disable  
1 = Enable (default)  
Transmitter fault enable  
R/W  
Transmitter loss of lock  
enable  
0 = Disable (default)  
1 = Enable  
5
4
3
2
1
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
PMA/PMD transmit local 0 = Disable  
fault enable  
1 = Enable (default)  
PCS transmit local fault  
enable  
0 = Disable  
1 = Enable (default)  
PCS buffer over/  
underflow error enable  
0 = Disable (default)  
1 = Enable  
0 = Disable (default)  
1 = Enable  
tx_flag enable  
PHY_XS transmit local  
fault enable  
0 = Disable  
1 = Enable (default)  
Table 59.  
LASI Control Register (DID = 1h, Address = 9002h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:7  
–
R/W  
Monitor 3.3 V_IN supply 0 = Disable (default)  
6
5
4
3
2
1
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
too low enable  
1 = Enable  
0 = Disable (default)  
1 = Enable  
3.3 V  
0 = Disable (default)  
1 = Enable  
1.8 V low detect enable  
LASI test data enable  
RX_ALARM enable  
0 = Disable (default)  
1 = Enable  
0 = Disable (default)  
1 = Enable  
0 = Disable (default)  
1 = Enable  
TX_ALARM enable  
0 = Disable (default)  
1 = Enable  
Link status alarm enable  
Table 60.  
RXALARM Status Register (DID = 1h, Address = 9003h) (Sheet 1 of 2)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:7  
–
R/W  
PHY_XS receive buffer  
over/underflow value  
error  
0 = No error detected  
1 = Error detected  
6
RO, LH  
5
4
Reserved  
–
R/W  
PMA/PMD receive local  
fault  
0 = No fault detected  
1 = Fault detected  
RO, LH  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
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Intel® TXN17431 (0850) Optical Transceiver  
Table 60.  
RXALARM Status Register (DID = 1h, Address = 9003h) (Sheet 2 of 2)  
Bit  
Functionality  
Description  
Access  
0 = No fault detected  
1 = Fault detected  
3
PCS receive local fault  
RO, LH  
PCS receive code  
violation  
0 = No violation  
2
1
0
RO, LH  
RO, LH  
RO, LH  
1 = Violation detected  
0 = No error detected  
1 = Error detected  
Rx_flag  
PHY_XS receive local  
fault  
0 = No error detected  
1 = Error detected  
Table 61.  
TXALARM Status Register (DID = 1h, Address = 9004h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:11  
–
–
PHY XS Code Violation  
Error Enable  
0 = Disable (default)  
1 = Enable  
10  
9:7  
6
RO, LH  
–
Reserved  
–
0 = No fault detected  
1 = Fault detected  
Transmit fault  
RO, LH  
0 = No loss of lock  
1 = Loss of lock  
5
4
3
2
1
0
Transmitter loss of lock  
RO, LH  
RO, LH  
RO, LH  
RO, LH  
RO,LH  
RO  
PMA/PMD transmit local 0 = No fault detected  
fault  
1 = Fault detected  
0 = No fault detected  
1 = Fault detected  
PCS transmit local fault  
PCS buffer over/  
underflow error  
0 = No flow error detected  
1 = Flow error detected  
0 = No error detected  
1 = Error detected  
tx_flag  
PHY_XS transmit local  
fault  
0 = No fault detected  
1 = Fault detected  
Table 62.  
LASI Status Register (DID = 1h, Address = 9005h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:7  
–
RO  
Monitor 3.3 V_IN supply 0 = No alarm  
6
5
RO, LH  
RO, LH  
too low  
1 = 3.3 V supply too low  
0 = No alarm  
3.3 V supply too low  
1 = 3.3 V supply too low  
0 = No alarm  
1 = 1.8 V supply too low  
4
3
2
1.8 V supply too low  
LASI test data  
RO, LH  
R/W  
–
0 = No alarm  
1 = RX_ALARM condition  
RXALARM status  
RO  
0 = No alarm  
1
0
TXALARM status  
RO  
1 = TX_ALARM condition  
0 = No status change  
1 = Status change  
Link status change  
RO,LH  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
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Intel® TXN17431 (0850) Optical Transceiver  
Table 63.  
DOM Tx_flag Control Register (DID = 1h, Address = 9006h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:8  
–
R/W  
0 = Disabled (default)  
1 = Enabled  
7
Temp High Alarm Enable  
R/W  
0 = Disabled (default)  
1 = Enabled  
6
5:4  
3
Temp Low Alarm Enable  
Reserved  
R/W  
R/W  
R/W  
–
Laser Bias current high  
alarm enable  
0 = Disabled (default)  
1 = Enabled  
Laser Bias current low  
alarm enable  
0 = Disabled (default)  
1 = Enabled  
2
1
0
R/W  
R/W  
R/W  
Laser Output power  
high alarm enable  
0 = Disabled (default)  
1 = Enabled  
Laser output power low 0 = Disabled (default)  
alarm enable 1 = Enabled  
Table 64.  
DOM Rx_flag Control Register (DID = 1, Address = 9007h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:8  
–
–
Rx Optical Power High  
Alarm Enable  
0 = Disable (default)  
1 = Enable  
7
R/W  
Rx Optical Power Low  
Alarm Enable  
0 = Disable (default)  
1 = Enable  
6
R/W  
R/W  
5:0  
Reserved  
–
Table 65.  
Table 66.  
DOM Registers (DID = 1, Address = A000h to A069h, A072h to A0FFh)  
Bit  
Functionality  
Description  
Access  
15:8  
7:0  
Reserved  
MSB bit 7 to LSB bit 0  
–
–
–
–
DOM – Tx_flag Status Register (DID = 1, Address = A070h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:8  
7
–
–
–
–
–
Temp High Alarm  
Temp Low Alarm  
Reserved  
RO  
RO  
RO  
6
5:4  
Laser Bias Current High  
Alarm  
3
2
1
0
–
–
–
–
RO  
RO  
RO  
RO  
Laser Bias Current Low  
Alarm  
Laser Output Power High  
Alarm  
Laser Output Power Low  
Alarm  
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Table 67.  
DOM – Rx_flag Status Register (DID = 1, Address = A071h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:8  
–
–
–
Rx Optical Power High  
Alarm  
7
RO  
Rx Optical Power Low  
Alarm  
6
–
–
RO  
RO  
5:0  
Reserved  
Table 68.  
DOM Command and Status Register (DID = 1, Address = A100h)  
Bit  
Functionality  
Reserved  
Description  
Access  
15:14  
–
RO  
00 =Idle, no command  
01 =Command completed  
10 =Command in progress  
11 = Previous command failed  
DOM Write Command  
Status  
13:12  
11:4  
3:2  
RO, LH  
RO  
Reserved  
–
00 =Idle, no command  
01 =Command completed  
10 =Command in progress  
11 = Previous command failed  
DOM Command Status  
RO, LH  
00 =Write, single DOM update (default)  
01 =Write, slow periodic update  
10 =Write, inter periodic update  
11 = Write, fast periodic update  
1:0  
DOM Update commands  
R/W  
7.0  
Digital Optical Monitoring  
The TXN17431 Optical Transceiver supports Digital Optical Monitoring (DOM) according  
to the XENPAK MSA 1.0b specification. This feature allows diagnostic monitoring of the  
transmitter and receiver optical power, bias current, transceiver operating temperature  
and state. The threshold alarm can be set appropriately to trigger LASI.  
There are 256 8-bit registers resident in MDIO register space 1.A000h to 1.A0FFh that  
support DOM. These registers store the digitized value of analog temperature/bias  
current measurements, warning and threshold values, and control/status settings. A  
DOM agent (microcontroller on board) loads these registers upon reset and polls these  
registers periodically for status checks. Layout of DOM registers can be found in  
Table 55 “EEPROM Registers (DID = 1h, from Address = 8007h to Address = 8106h)”  
on page 30 through Table 59 “LASI Control Register (DID = 1h, Address = 9002h)” on  
page 32, and also in XENPAK MSA 1.0b, Tables 27-28.  
The following two flag values (ref 1.9006h and 1.9007h) trigger LASI alarms when  
DOM fault conditions occur:  
• Rx_flag: Register 1.A071h contains bits to indicate the receiver Fault Status.  
Register 1.9007h selects the fault conditions in register 1.A071 to be reported via  
the Rx Flag bit (1.A071 AND 1.9007). The logic OR of any of the selected fault  
conditions is then reflected by Rx Flag.  
• Tx_flag. Register 1.A070h contains bits to indicate the transmitter Fault Status.  
Register 1.9006h selects the fault conditions in register 1.A071 to be reported via  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
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Intel® TXN17431 (0850) Optical Transceiver  
the Rx Flag bit (1.A070 AND 1.9006). The logic OR of any of the selected fault  
conditions is then reflected by Tx flag.  
These two flag values are fed directly to RX_ALARM and TX_ALARM, respectively. LASI  
is asserted when either RX_ALARM or TX_ALARM is set and enabled.  
The DOM register update rate can be set by register 1.A100.1:0 contents. Writing a  
“00” to these bits initiates a single upload of DOM registers. The DOM registers  
periodically update if these bits are set to any other state (see Table 69).  
Table 69.  
DOM Update Rates (DID = 1, Address = A100h)  
Bits (1:0)  
Description  
Initiate a single update of MDIO DOM registers; default update interval  
value  
00  
01  
10  
11  
Periodic update of MDIO DOM registers every 60 seconds  
Periodic update of MDIO DOM registers every 10 seconds  
Periodic update of MDIO DOM registers every 1 second  
If a DOM update is requested while a Non Volatile Register (NVR) read or write is in  
progress, the NVR transaction is allowed to complete and the DOM update begins.  
While the DOM update is pending, the DOM command register (1.A100h) indicates a  
transaction in progress. The same applies if an NVR transaction is requested while a  
DOM update is in progress. While an NVR or DOM update is queued, the associated  
command register is put in the command-in-progress state. Figure 2 shows a state  
diagram.  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
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Intel® TXN17431 (0850) Optical Transceiver  
Figure 2.  
DOM Access State Diagram  
8.0  
Loopback Capability  
The TXN17431 Optical Transceiver features five loopback modes for diagnostic and test  
purposes. This feature is enabled and configured by writing appropriate values to the  
MDIO registers (see Table 70).  
Table 70.  
Loopback Capability (Sheet 1 of 2)  
Data Path Output  
Data Path Output  
Data Output  
Enable  
Register  
(Data Output Enable (Data Output Enable  
Loopback  
Control Register  
Loopback Type  
Register = 0 and  
Loopback Control  
Register Enabled)  
Register = 1 and  
Loopback Control  
Register Enabled)  
PMA loopback  
(transmit ->  
receive)  
DID = 1h,  
Address = 0h, Bit  
0
None  
Loopback transmit data NA  
PCS loopback  
(transmit ->  
receive)  
DID = 3,  
Address = 0h, Bit  
14  
DID = 3h,  
Address =  
c000h, Bit 5  
0F0F  
Loopback transmit data  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
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Table 70.  
Loopback Capability (Sheet 2 of 2)  
Data Path Output  
Data Path Output  
Data Output  
(Data Output Enable (Data Output Enable  
Loopback  
Control Register  
Loopback Type  
Enable  
Register = 0 and  
Loopback Control  
Register Enabled)  
Register = 1 and  
Loopback Control  
Register Enabled)  
Register  
PHY_XS loopback DID = 4h,  
(receive ->  
transmit)  
Address = 0h, Bit  
None  
Receive data at RxXAUI None  
14  
PHY_XS system  
loopback  
(transmit ->  
receive)  
DID = 4h,  
Address = c000h,  
Bit 14  
DID = 4h,  
Address =  
c000h, Bit 15  
ffffh at TXOUT  
Transmit data  
PMA network  
DID = 1h,  
DID = 1h,  
Address =  
c001h, Bit 9  
Received data at  
RxXAUI  
Transmit all idles at  
RxXAUI  
loopback (receive Address = c001h,  
-> transmit)  
Bit 4  
Typically, data from the transmit path is rerouted to the receive path when the loopback  
mode is enabled. However, for PCS loopback and PHY_XS loopback, you can observe a  
fixed data pattern (listed in Table 70 as bypassed path output) instead of the looped  
back data by setting the Data Output Enable Register to logic 0.  
In PMA network loopback mode, the recovered and re-timed 10 G signal, (that is, the  
receiving signal) is looped back to the transmitter output. The receive path XAUI output  
data is XAUI idle codes. If the Data Output Enable Register is asserted, the output is  
received data instead of idle codes.  
Note: Enabling more than one loopback path is invalid and should not be part of normal  
operation.  
9.0  
Mechanical Layout and Configuration  
The TXN17431 Optical Transceiver comes standard with an integrated heat sink  
designed for nominal operation of the module at 200 linear feet per minute (lfm) of 50  
°C ambient temperature airflow. These conditions produce a worst-case 70 °C case  
temperature, which keeps the optical and electrical components within their specified  
operating temperature requirements.  
Warning:  
Do not use an “Aqueous Wash” with the TXN17431 Optical Transceiver.  
Figure 3 shows the form factor and dimensions of the TXN17431 Optical Transceiver.  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
38  
2-Nov-2007  
Document Number: 306425-005  
Intel® TXN17431 (0850) Optical Transceiver  
Figure 3.  
Mechanical Outline for a Heat Sink  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
2-Nov-2007  
Document Number: 306424-005  
Datasheet  
39  
Intel® TXN17431 (0850) Optical Transceiver  
10.0  
Regulatory Compliance  
This section discusses the following topics:  
• Section 10.1, “Electromagnetic Compatibility Compliance” on page 40  
• Section 10.2, “Safety Compliance” on page 40  
• Section 10.3, “Compliance with Restriction of Hazardous Substances” on page 41  
• Section 10.4, “Product Certification Markings and Compliance Statements” on  
page 41  
• Section 10.5, “Management Methods on Control of Pollution from Electronic  
Information Products (a.k.a. China RoHS)” on page 43  
10.1  
Electromagnetic Compatibility Compliance  
Table 71 lists emissions and immunity regulations with which the Intel® TXN17431  
(0850) Optical Transceiver complies when tested in a representative chassis.  
Table 71.  
Electromagnetic Compatibility Compliance  
Requirement  
Regulation  
Performance Level  
•
•
FCC rules, Part 15,  
subpart B  
EN 55022  
Meets Class B limits with a minimum  
6 dB margin  
Electromagnetic interference (EMI)  
JEDEC JESD22-A114-B  
Human Body Model  
± 400 V contact discharge to connector  
electrical pins  
Electrostatic discharge (ESD)  
•
•
±15 kV air discharge  
± 8 kV contact discharge to face  
plate  
EN 61000-4-2  
EN 61000-4-3  
10 V/m from 80 MHz to 1G Hz with no  
degradation of performance or loss of  
function  
Radio frequency electromagnetic  
field (Radiated immunity)  
10.2  
Safety Compliance  
Table 72 lists and describes the relevant safety regulations with which the Intel®  
TXN17431 (0850) Optical Transceiver complies.  
Table 72.  
Safety Compliance (Sheet 1 of 2)  
Requirement  
Regulation  
Title  
UL 60950-1CSA C22.2 No.  
60950-1-03  
Information Technology Equipment – Safety - Part 1:  
General Requirements (USA and Canada)  
Information Technology Equipment – Safety - Part 1:  
General Requirements (European Union)  
EN 60950-1 +A11  
IEC 60950-1  
Product Safety  
Information Technology Equipment – Safety - Part 1:  
General Requirements (International)  
Compliant with the fire resistance requirements of  
Telcordia Technologies Generic Requirements GR-63-CORE  
document for discrete electronic components.  
GR-63-CORE Section 4.2,  
Clause 4.2.3.1  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
40  
2-Nov-2007  
Document Number: 306425-005  
Intel® TXN17431 (0850) Optical Transceiver  
Table 72.  
Safety Compliance (Sheet 2 of 2)  
Requirement  
Regulation  
Title  
Code of Federal Regulations Title 21 Chapter I Subchapter  
J – Radiological Health Part 1040:  
Performance Standards for Light-Emitting Products  
21CFR1040.10  
Safety of Laser Products - Part 1:  
Equipment Classification, Requirements and User's Guide  
EN 60825-1 +A1 +A2  
IEC 60825-1 +A1 +A2  
EN 60825-2  
Laser Safety  
Safety of Laser Products - Part 1:  
Equipment Classification, Requirements and User's Guide  
Safety of Laser Products - Part 2:  
Safety of Optical Fiber Communication Systems  
Safety of Laser Products - Part 2:  
Safety of Optical Fiber Communication Systems  
IEC 60825-2  
10.3  
Compliance with Restriction of Hazardous Substances  
This product complies with the European Union directive for Restriction of Hazardous  
Substances (RoHS) – Restriction on the Use of Certain Hazardous Substances in  
Electrical and Electronic Equipment, Directive 2002/95/EC plus amendments.  
However, certain discrete components do contain lead (a RoHS-restricted substance) in  
amounts that exceed threshold concentration levels. This product uses the following  
applicable RoHS technology exemptions:  
• Lead in optical and filter glass  
• Lead in glass of electronic components  
• Lead in electronic ceramic parts  
• Lead in solders for servers, storage and storage array systems, network  
infrastructure equipment for switching, signaling, transmission, as well as network  
management for telecommunications  
Note:  
RoHS implementation details are subject to change.  
10.4  
Product Certification Markings and Compliance  
Statements  
Table 73 lists the Intel® TXN17431 (0850) Optical Transceiver product certification  
markings and compliance statements.  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
2-Nov-2007  
Document Number: 306424-005  
41  
Intel® TXN17431 (0850) Optical Transceiver  
Table 73.  
Product Certification Markings and Compliance Statements  
Origin and Description  
Markings and Compliance Statements  
Markings  
CE mark.  
The CE (Conformité Européene*) mark indicates compliance  
to the European Union Low Voltage directive (73/23/EEC).  
TÜV Rheinland type approval mark for components and  
subassemblies for the European Union.  
The Technischer Überwachungsverein* (TÜV – German for  
“Technical Inspection Association”) Rheinland type approval  
mark is for components and subassemblies for the European  
Union.  
Where space does not permit, the smaller alternate TÜV  
mark (see the next row in this table) may be used.  
Alternate TÜV mark:  
TÜV Rheinland type approval mark for components and  
subassemblies for the European Union – Alternate.  
This alternate mark may be used where space constraints  
exist that do not permit use of the TUV Rheinland mark in  
the previous row of this table.  
UL Recognized Component mark for the USA and Canada.  
China Environmental Friendly Use Period (EFUP) mark,  
where 30 in the marking denotes 30 years. The number  
provided as the EFUP is provided solely to comply with  
applicable laws of the People’s Republic of China. It does not  
create any warranties or liabilities on behalf of Intel  
Corporation to customers.  
Compliance Statements  
Complies with 21CFR 1040.10 except for  
deviations pursuant to Laser Notice No. 50,  
dated July 26, 2001.  
USA Food and Drug Administration (FDA), Center for  
Devices and Radiological Health compliance statement.  
Alternate FDA compliance statement:  
USA FDA, Center for Devices and Radiological Health  
Complies with FDA performance standards for  
laser products except for deviations pursuant  
to Laser Notice No. 50, dated July 26, 2001.  
compliance statement – Alternate.  
Use the alternate statement listed, as needed.  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
42  
2-Nov-2007  
Document Number: 306425-005  
Intel® TXN17431 (0850) Optical Transceiver  
10.5  
Management Methods on Control of Pollution from  
Electronic Information Products (a.k.a. China RoHS)  
关于符合中国《电子信息产品污染控制管理办法》的声明  
Table 74.  
Hazardous Substances Table  
产品中有毒有害物质的名称及含量  
有毒有害物质或元素 (Hazardous Substance)  
多溴二苯醚  
(PBDE)  
铅
(Pb)  
汞
(Hg)  
镉
(Cd)  
多溴联苯  
(PBB)  
部件名称  
(Parts)  
六价铬  
(Cr(VI))  
集成光电器件  
Integrated optical circuit board  
×
○
○
○
○
○
○
○
○
○
○
assembly  
金属盒件  
Metal enclosure  
○
○：表示该有毒有害物质在该部件所有均质材料中的含量均在SJ/T 11363-  
2006标准规定的限量要求以下。  
○：Indicates that this hazardous substance contained in all homogeneous materials of this part is below the  
limit requirement in SJ/T 11363-2006.  
×：表示该有毒有害物质至少在该部件的某一均质材料中的含量超出SJ/T 11363-  
2006标准规定的限量要求。  
×：Indicates that this hazardous substance contained in at least one of the homogeneous materials of this  
part is above the limit requirement in SJ/T 11363-2006.  
对销售之日的所售产品,本表显示我公司供应链的电子信息产品可能包含这些物质。注意：在所售产  
品中可能会也可能不会含有所有所列的部件。  
This table shows where these substances may be found in the supply chain of our electronic information  
products, as of the date of sale of the enclosed product. Note that some of the component types listed above  
may or may not be a part of the enclosed product.  
除非另外特别的标注,此标志为针对所涉及产品的环保使用期限标志.此环保使用  
期限只适用于产品在产品手册中所规定的条件下工作.  
The Environment-Friendly Use Period (EFUP) for all enclosed products and their parts are per  
the symbol shown here, unless otherwise marked. The Environment-Friendly Use Period is  
valid only when the product is operated under the conditions defined in the product manual.  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
2-Nov-2007  
Document Number: 306424-005  
43  
Intel® TXN17431 (0850) Optical Transceiver  
11.0  
Ordering Information  
Specify the complete TXN17431 Optical Transceiver part number defined in Table 75  
when ordering.  
Table 75.  
Ordering Information  
Part Number  
MM Number  
Description  
TXN174310850F16  
(obsolete, replaced by  
TXN174310850F36)  
300 m, 850 nm Serial, 10.3 Gbps Ethernet Optical Transceiver  
Compliant with XENPAK MSA, manufactured in Malaysia.  
872628  
300 m, 850 nm Serial, 10.3 Gbps Ethernet Optical Transceiver  
Compliant with XENPAK MSA, manufactured in Thailand.  
TXN174310850F36  
891472  
12.0  
Acronyms  
Table 76.  
Acronyms  
Acronym  
Meaning  
CDR  
Clock and Data Recovery  
DFB  
Distributed Feedback  
DOM  
EEPROM  
IEEE  
LASI  
MDIO  
PCS  
Digital Optical Monitoring  
Electrically Erasable Programmable Read Only Memory  
Institute of Electrical and Electronics Engineers  
Link Alarm Status Interrupt  
Management Data Input/Output  
Physical Coding Sublayer (PCS)  
Multisouorce Agreement  
MSA  
NVR  
Non Volatile Register  
PMA  
Physical Medium Attachment (PMA)  
Physical Medium Dependent (PMD)  
Snap-on Connector with Ultra-Physical Contact  
Serializer-Deserializer  
PMD  
SC-UPC  
SerDes  
TO  
Transmitter Optical  
XAUI  
10 Gigabit Attachment Unit Interface  
§ §  
Intel® TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA  
Datasheet  
44  
2-Nov-2007  
Document Number: 306425-005  
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